1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "InstrInfoEmitter.h"
16 #include "CodeGenTarget.h"
22 static void PrintDefList(const std::vector<Record*> &Uses,
23 unsigned Num, std::ostream &OS) {
24 OS << "static const unsigned ImplicitList" << Num << "[] = { ";
25 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
26 OS << getQualifiedName(Uses[i]) << ", ";
30 //===----------------------------------------------------------------------===//
31 // Instruction Itinerary Information.
32 //===----------------------------------------------------------------------===//
34 struct RecordNameComparator {
35 bool operator()(const Record *Rec1, const Record *Rec2) const {
36 return Rec1->getName() < Rec2->getName();
40 void InstrInfoEmitter::GatherItinClasses() {
41 std::vector<Record*> DefList =
42 Records.getAllDerivedDefinitions("InstrItinClass");
43 std::sort(DefList.begin(), DefList.end(), RecordNameComparator());
45 for (unsigned i = 0, N = DefList.size(); i < N; i++)
46 ItinClassMap[DefList[i]->getName()] = i;
49 unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
50 return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
53 //===----------------------------------------------------------------------===//
54 // Operand Info Emission.
55 //===----------------------------------------------------------------------===//
57 std::vector<std::string>
58 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
59 std::vector<std::string> Result;
61 for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
62 // Handle aggregate operands and normal operands the same way by expanding
63 // either case into a list of operands for this op.
64 std::vector<CodeGenInstruction::OperandInfo> OperandList;
66 // This might be a multiple operand thing. Targets like X86 have
67 // registers in their multi-operand operands. It may also be an anonymous
68 // operand, which has a single operand, but no declared class for the
70 DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
72 if (!MIOI || MIOI->getNumArgs() == 0) {
73 // Single, anonymous, operand.
74 OperandList.push_back(Inst.OperandList[i]);
76 for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
77 OperandList.push_back(Inst.OperandList[i]);
79 Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
80 OperandList.back().Rec = OpR;
84 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
85 Record *OpR = OperandList[j].Rec;
88 if (OpR->isSubClassOf("RegisterClass"))
89 Res += getQualifiedName(OpR) + "RegClassID, ";
92 // Fill in applicable flags.
95 // Ptr value whose register class is resolved via callback.
96 if (OpR->getName() == "ptr_rc")
97 Res += "|(1<<TOI::LookupPtrRegClass)";
99 // Predicate operands. Check to see if the original unexpanded operand
100 // was of type PredicateOperand.
101 if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
102 Res += "|(1<<TOI::Predicate)";
104 // Optional def operands. Check to see if the original unexpanded operand
105 // was of type OptionalDefOperand.
106 if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
107 Res += "|(1<<TOI::OptionalDef)";
109 // Fill in constraint info.
110 Res += ", " + Inst.OperandList[i].Constraints[j];
111 Result.push_back(Res);
118 void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
119 OperandInfoMapTy &OperandInfoIDs) {
120 // ID #0 is for no operand info.
121 unsigned OperandListNum = 0;
122 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
125 const CodeGenTarget &Target = CDP.getTargetInfo();
126 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
127 E = Target.inst_end(); II != E; ++II) {
128 std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
129 unsigned &N = OperandInfoIDs[OperandInfo];
130 if (N != 0) continue;
132 N = ++OperandListNum;
133 OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
134 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
135 OS << "{ " << OperandInfo[i] << " }, ";
140 //===----------------------------------------------------------------------===//
141 // Instruction Analysis
142 //===----------------------------------------------------------------------===//
145 const CodeGenDAGPatterns &CDP;
148 bool &HasSideEffects;
150 InstAnalyzer(const CodeGenDAGPatterns &cdp,
151 bool &maystore, bool &mayload, bool &hse)
152 : CDP(cdp), mayStore(maystore), mayLoad(mayload), HasSideEffects(hse){
155 /// Analyze - Analyze the specified instruction, returning true if the
156 /// instruction had a pattern.
157 bool Analyze(Record *InstRecord) {
158 const TreePattern *Pattern = CDP.getInstruction(InstRecord).getPattern();
161 return false; // No pattern.
164 // FIXME: Assume only the first tree is the pattern. The others are clobber
166 AnalyzeNode(Pattern->getTree(0));
171 void AnalyzeNode(const TreePatternNode *N) {
173 if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) {
174 Record *LeafRec = DI->getDef();
175 // Handle ComplexPattern leaves.
176 if (LeafRec->isSubClassOf("ComplexPattern")) {
177 const ComplexPattern &CP = CDP.getComplexPattern(LeafRec);
178 if (CP.hasProperty(SDNPMayStore)) mayStore = true;
179 if (CP.hasProperty(SDNPMayLoad)) mayLoad = true;
180 if (CP.hasProperty(SDNPSideEffect)) HasSideEffects = true;
187 for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i)
188 AnalyzeNode(N->getChild(i));
190 // Ignore set nodes, which are not SDNodes.
191 if (N->getOperator()->getName() == "set")
194 // Get information about the SDNode for the operator.
195 const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator());
197 // Notice properties of the node.
198 if (OpInfo.hasProperty(SDNPMayStore)) mayStore = true;
199 if (OpInfo.hasProperty(SDNPMayLoad)) mayLoad = true;
200 if (OpInfo.hasProperty(SDNPSideEffect)) HasSideEffects = true;
202 if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) {
203 // If this is an intrinsic, analyze it.
204 if (IntInfo->ModRef >= CodeGenIntrinsic::ReadArgMem)
205 mayLoad = true;// These may load memory.
207 if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem)
208 mayStore = true;// Intrinsics that can write to memory are 'mayStore'.
210 if (IntInfo->ModRef >= CodeGenIntrinsic::WriteMem)
211 // WriteMem intrinsics can have other strange effects.
212 HasSideEffects = true;
218 void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
219 bool &MayStore, bool &MayLoad,
220 bool &HasSideEffects) {
221 MayStore = MayLoad = HasSideEffects = false;
224 InstAnalyzer(CDP, MayStore, MayLoad, HasSideEffects).Analyze(Inst.TheDef);
226 // InstAnalyzer only correctly analyzes mayStore/mayLoad so far.
227 if (Inst.mayStore) { // If the .td file explicitly sets mayStore, use it.
228 // If we decided that this is a store from the pattern, then the .td file
229 // entry is redundant.
232 "Warning: mayStore flag explicitly set on instruction '%s'"
233 " but flag already inferred from pattern.\n",
234 Inst.TheDef->getName().c_str());
238 if (Inst.mayLoad) { // If the .td file explicitly sets mayLoad, use it.
239 // If we decided that this is a load from the pattern, then the .td file
240 // entry is redundant.
243 "Warning: mayLoad flag explicitly set on instruction '%s'"
244 " but flag already inferred from pattern.\n",
245 Inst.TheDef->getName().c_str());
249 if (Inst.neverHasSideEffects) {
251 fprintf(stderr, "Warning: neverHasSideEffects set on instruction '%s' "
252 "which already has a pattern\n", Inst.TheDef->getName().c_str());
253 HasSideEffects = false;
256 if (Inst.hasSideEffects) {
258 fprintf(stderr, "Warning: hasSideEffects set on instruction '%s' "
259 "which already inferred this.\n", Inst.TheDef->getName().c_str());
260 HasSideEffects = true;
265 //===----------------------------------------------------------------------===//
267 //===----------------------------------------------------------------------===//
269 // run - Emit the main instruction description records for the target...
270 void InstrInfoEmitter::run(std::ostream &OS) {
273 EmitSourceFileHeader("Target Instruction Descriptors", OS);
274 OS << "namespace llvm {\n\n";
276 CodeGenTarget Target;
277 const std::string &TargetName = Target.getName();
278 Record *InstrInfo = Target.getInstructionSet();
280 // Keep track of all of the def lists we have emitted already.
281 std::map<std::vector<Record*>, unsigned> EmittedLists;
282 unsigned ListNumber = 0;
284 // Emit all of the instruction's implicit uses and defs.
285 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
286 E = Target.inst_end(); II != E; ++II) {
287 Record *Inst = II->second.TheDef;
288 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
290 unsigned &IL = EmittedLists[Uses];
291 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
293 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
295 unsigned &IL = EmittedLists[Defs];
296 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
300 OperandInfoMapTy OperandInfoIDs;
302 // Emit all of the operand info records.
303 EmitOperandInfo(OS, OperandInfoIDs);
305 // Emit all of the TargetInstrDesc records in their ENUM ordering.
307 OS << "\nstatic const TargetInstrDesc " << TargetName
309 std::vector<const CodeGenInstruction*> NumberedInstructions;
310 Target.getInstructionsByEnumValue(NumberedInstructions);
312 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
313 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
316 OS << "} // End llvm namespace \n";
319 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
321 std::map<std::vector<Record*>, unsigned> &EmittedLists,
322 const OperandInfoMapTy &OpInfo,
324 // Determine properties of the instruction from its pattern.
325 bool mayStore, mayLoad, HasSideEffects;
326 InferFromPattern(Inst, mayStore, mayLoad, HasSideEffects);
329 if (!Inst.OperandList.empty())
330 // Each logical operand can be multiple MI operands.
331 MinOperands = Inst.OperandList.back().MIOperandNo +
332 Inst.OperandList.back().MINumOperands;
335 OS << Num << ",\t" << MinOperands << ",\t"
336 << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
337 << ",\t\"" << Inst.TheDef->getName() << "\", 0";
339 // Emit all of the target indepedent flags...
340 if (Inst.isReturn) OS << "|(1<<TID::Return)";
341 if (Inst.isBranch) OS << "|(1<<TID::Branch)";
342 if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
343 if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
344 if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
345 if (Inst.isCall) OS << "|(1<<TID::Call)";
346 if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
347 if (mayLoad) OS << "|(1<<TID::MayLoad)";
348 if (mayStore) OS << "|(1<<TID::MayStore)";
349 if (Inst.isImplicitDef)OS << "|(1<<TID::ImplicitDef)";
350 if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
351 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
352 if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
353 if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
354 if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
355 if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)";
356 if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)";
357 if (Inst.usesCustomDAGSchedInserter)
358 OS << "|(1<<TID::UsesCustomDAGSchedInserter)";
359 if (Inst.isVariadic) OS << "|(1<<TID::Variadic)";
360 if (Inst.mayHaveSideEffects) OS << "|(1<<TID::MayHaveSideEffects)";
361 if (!HasSideEffects) OS << "|(1<<TID::NeverHasSideEffects)";
364 // Emit all of the target-specific flags...
365 ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
366 ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
367 if (LI->getSize() != Shift->getSize())
368 throw "Lengths of " + InstrInfo->getName() +
369 ":(TargetInfoFields, TargetInfoPositions) must be equal!";
371 for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
372 emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
373 dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
377 // Emit the implicit uses and defs lists...
378 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
382 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
384 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
388 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
390 // Emit the operand info.
391 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
392 if (OperandInfo.empty())
395 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
397 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
401 void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
402 IntInit *ShiftInt, std::ostream &OS) {
403 if (Val == 0 || ShiftInt == 0)
404 throw std::string("Illegal value or shift amount in TargetInfo*!");
405 RecordVal *RV = R->getValue(Val->getValue());
406 int Shift = ShiftInt->getValue();
408 if (RV == 0 || RV->getValue() == 0) {
409 // This isn't an error if this is a builtin instruction.
410 if (R->getName() != "PHI" &&
411 R->getName() != "INLINEASM" &&
412 R->getName() != "LABEL" &&
413 R->getName() != "EXTRACT_SUBREG" &&
414 R->getName() != "INSERT_SUBREG")
415 throw R->getName() + " doesn't have a field named '" +
416 Val->getValue() + "'!";
420 Init *Value = RV->getValue();
421 if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
422 if (BI->getValue()) OS << "|(1<<" << Shift << ")";
424 } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
425 // Convert the Bits to an integer to print...
426 Init *I = BI->convertInitializerTo(new IntRecTy());
428 if (IntInit *II = dynamic_cast<IntInit*>(I)) {
429 if (II->getValue()) {
431 OS << "|(" << II->getValue() << "<<" << Shift << ")";
433 OS << "|" << II->getValue();
438 } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
439 if (II->getValue()) {
441 OS << "|(" << II->getValue() << "<<" << Shift << ")";
443 OS << II->getValue();
448 std::cerr << "Unhandled initializer: " << *Val << "\n";
449 throw "In record '" + R->getName() + "' for TSFlag emission.";