1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
16 #include "CodeGenDAGPatterns.h"
17 #include "CodeGenTarget.h"
18 #include "SequenceToOffsetTable.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/TableGen/Record.h"
21 #include "llvm/TableGen/TableGenBackend.h"
29 class InstrInfoEmitter {
30 RecordKeeper &Records;
31 CodeGenDAGPatterns CDP;
32 std::map<std::string, unsigned> ItinClassMap;
35 InstrInfoEmitter(RecordKeeper &R) : Records(R), CDP(R) { }
37 // run - Output the instruction set description.
38 void run(raw_ostream &OS);
41 void emitEnums(raw_ostream &OS);
43 typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
44 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
46 std::map<std::vector<Record*>, unsigned> &EL,
47 const OperandInfoMapTy &OpInfo,
50 // Itinerary information.
51 void GatherItinClasses();
52 unsigned getItinClassNumber(const Record *InstRec);
54 // Operand information.
55 void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
56 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
58 } // End anonymous namespace
60 static void PrintDefList(const std::vector<Record*> &Uses,
61 unsigned Num, raw_ostream &OS) {
62 OS << "static const uint16_t ImplicitList" << Num << "[] = { ";
63 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
64 OS << getQualifiedName(Uses[i]) << ", ";
68 //===----------------------------------------------------------------------===//
69 // Instruction Itinerary Information.
70 //===----------------------------------------------------------------------===//
72 void InstrInfoEmitter::GatherItinClasses() {
73 std::vector<Record*> DefList =
74 Records.getAllDerivedDefinitions("InstrItinClass");
75 std::sort(DefList.begin(), DefList.end(), LessRecord());
77 for (unsigned i = 0, N = DefList.size(); i < N; i++)
78 ItinClassMap[DefList[i]->getName()] = i;
81 unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
82 return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
85 //===----------------------------------------------------------------------===//
86 // Operand Info Emission.
87 //===----------------------------------------------------------------------===//
89 std::vector<std::string>
90 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
91 std::vector<std::string> Result;
93 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
94 // Handle aggregate operands and normal operands the same way by expanding
95 // either case into a list of operands for this op.
96 std::vector<CGIOperandList::OperandInfo> OperandList;
98 // This might be a multiple operand thing. Targets like X86 have
99 // registers in their multi-operand operands. It may also be an anonymous
100 // operand, which has a single operand, but no declared class for the
102 DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
104 if (!MIOI || MIOI->getNumArgs() == 0) {
105 // Single, anonymous, operand.
106 OperandList.push_back(Inst.Operands[i]);
108 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
109 OperandList.push_back(Inst.Operands[i]);
111 Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
112 OperandList.back().Rec = OpR;
116 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
117 Record *OpR = OperandList[j].Rec;
120 if (OpR->isSubClassOf("RegisterOperand"))
121 OpR = OpR->getValueAsDef("RegClass");
122 if (OpR->isSubClassOf("RegisterClass"))
123 Res += getQualifiedName(OpR) + "RegClassID, ";
124 else if (OpR->isSubClassOf("PointerLikeRegClass"))
125 Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
127 // -1 means the operand does not have a fixed register class.
130 // Fill in applicable flags.
133 // Ptr value whose register class is resolved via callback.
134 if (OpR->isSubClassOf("PointerLikeRegClass"))
135 Res += "|(1<<MCOI::LookupPtrRegClass)";
137 // Predicate operands. Check to see if the original unexpanded operand
138 // was of type PredicateOperand.
139 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
140 Res += "|(1<<MCOI::Predicate)";
142 // Optional def operands. Check to see if the original unexpanded operand
143 // was of type OptionalDefOperand.
144 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
145 Res += "|(1<<MCOI::OptionalDef)";
147 // Fill in operand type.
149 assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type.");
150 Res += Inst.Operands[i].OperandType;
152 // Fill in constraint info.
155 const CGIOperandList::ConstraintInfo &Constraint =
156 Inst.Operands[i].Constraints[j];
157 if (Constraint.isNone())
159 else if (Constraint.isEarlyClobber())
160 Res += "(1 << MCOI::EARLY_CLOBBER)";
162 assert(Constraint.isTied());
163 Res += "((" + utostr(Constraint.getTiedOperand()) +
164 " << 16) | (1 << MCOI::TIED_TO))";
167 Result.push_back(Res);
174 void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
175 OperandInfoMapTy &OperandInfoIDs) {
176 // ID #0 is for no operand info.
177 unsigned OperandListNum = 0;
178 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
181 const CodeGenTarget &Target = CDP.getTargetInfo();
182 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
183 E = Target.inst_end(); II != E; ++II) {
184 std::vector<std::string> OperandInfo = GetOperandInfo(**II);
185 unsigned &N = OperandInfoIDs[OperandInfo];
186 if (N != 0) continue;
188 N = ++OperandListNum;
189 OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
190 for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
191 OS << "{ " << OperandInfo[i] << " }, ";
196 //===----------------------------------------------------------------------===//
198 //===----------------------------------------------------------------------===//
200 // run - Emit the main instruction description records for the target...
201 void InstrInfoEmitter::run(raw_ostream &OS) {
202 emitSourceFileHeader("Target Instruction Enum Values", OS);
207 emitSourceFileHeader("Target Instruction Descriptors", OS);
209 OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n";
210 OS << "#undef GET_INSTRINFO_MC_DESC\n";
212 OS << "namespace llvm {\n\n";
214 CodeGenTarget &Target = CDP.getTargetInfo();
215 const std::string &TargetName = Target.getName();
216 Record *InstrInfo = Target.getInstructionSet();
218 // Keep track of all of the def lists we have emitted already.
219 std::map<std::vector<Record*>, unsigned> EmittedLists;
220 unsigned ListNumber = 0;
222 // Emit all of the instruction's implicit uses and defs.
223 for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
224 E = Target.inst_end(); II != E; ++II) {
225 Record *Inst = (*II)->TheDef;
226 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
228 unsigned &IL = EmittedLists[Uses];
229 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
231 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
233 unsigned &IL = EmittedLists[Defs];
234 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
238 OperandInfoMapTy OperandInfoIDs;
240 // Emit all of the operand info records.
241 EmitOperandInfo(OS, OperandInfoIDs);
243 // Emit all of the MCInstrDesc records in their ENUM ordering.
245 OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
246 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
247 Target.getInstructionsByEnumValue();
249 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
250 emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
254 // Build an array of instruction names
255 SequenceToOffsetTable<std::string> InstrNames;
256 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
257 const CodeGenInstruction *Instr = NumberedInstructions[i];
258 InstrNames.add(Instr->TheDef->getName());
262 OS << "extern const char " << TargetName << "InstrNameData[] = {\n";
263 InstrNames.emit(OS, printChar);
266 OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
267 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
270 const CodeGenInstruction *Instr = NumberedInstructions[i];
271 OS << InstrNames.get(Instr->TheDef->getName()) << "U, ";
276 // MCInstrInfo initialization routine.
277 OS << "static inline void Init" << TargetName
278 << "MCInstrInfo(MCInstrInfo *II) {\n";
279 OS << " II->InitMCInstrInfo(" << TargetName << "Insts, "
280 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
281 << NumberedInstructions.size() << ");\n}\n\n";
283 OS << "} // End llvm namespace \n";
285 OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
287 // Create a TargetInstrInfo subclass to hide the MC layer initialization.
288 OS << "\n#ifdef GET_INSTRINFO_HEADER\n";
289 OS << "#undef GET_INSTRINFO_HEADER\n";
291 std::string ClassName = TargetName + "GenInstrInfo";
292 OS << "namespace llvm {\n";
293 OS << "struct " << ClassName << " : public TargetInstrInfoImpl {\n"
294 << " explicit " << ClassName << "(int SO = -1, int DO = -1);\n"
296 OS << "} // End llvm namespace \n";
298 OS << "#endif // GET_INSTRINFO_HEADER\n\n";
300 OS << "\n#ifdef GET_INSTRINFO_CTOR\n";
301 OS << "#undef GET_INSTRINFO_CTOR\n";
303 OS << "namespace llvm {\n";
304 OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
305 OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
306 OS << "extern const char " << TargetName << "InstrNameData[];\n";
307 OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
308 << " : TargetInstrInfoImpl(SO, DO) {\n"
309 << " InitMCInstrInfo(" << TargetName << "Insts, "
310 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
311 << NumberedInstructions.size() << ");\n}\n";
312 OS << "} // End llvm namespace \n";
314 OS << "#endif // GET_INSTRINFO_CTOR\n\n";
317 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
319 std::map<std::vector<Record*>, unsigned> &EmittedLists,
320 const OperandInfoMapTy &OpInfo,
323 if (!Inst.Operands.size() == 0)
324 // Each logical operand can be multiple MI operands.
325 MinOperands = Inst.Operands.back().MIOperandNo +
326 Inst.Operands.back().MINumOperands;
329 OS << Num << ",\t" << MinOperands << ",\t"
330 << Inst.Operands.NumDefs << ",\t"
331 << getItinClassNumber(Inst.TheDef) << ",\t"
332 << Inst.TheDef->getValueAsInt("Size") << ",\t0";
334 // Emit all of the target indepedent flags...
335 if (Inst.isPseudo) OS << "|(1<<MCID::Pseudo)";
336 if (Inst.isReturn) OS << "|(1<<MCID::Return)";
337 if (Inst.isBranch) OS << "|(1<<MCID::Branch)";
338 if (Inst.isIndirectBranch) OS << "|(1<<MCID::IndirectBranch)";
339 if (Inst.isCompare) OS << "|(1<<MCID::Compare)";
340 if (Inst.isMoveImm) OS << "|(1<<MCID::MoveImm)";
341 if (Inst.isBitcast) OS << "|(1<<MCID::Bitcast)";
342 if (Inst.isBarrier) OS << "|(1<<MCID::Barrier)";
343 if (Inst.hasDelaySlot) OS << "|(1<<MCID::DelaySlot)";
344 if (Inst.isCall) OS << "|(1<<MCID::Call)";
345 if (Inst.canFoldAsLoad) OS << "|(1<<MCID::FoldableAsLoad)";
346 if (Inst.mayLoad) OS << "|(1<<MCID::MayLoad)";
347 if (Inst.mayStore) OS << "|(1<<MCID::MayStore)";
348 if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)";
349 if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)";
350 if (Inst.isCommutable) OS << "|(1<<MCID::Commutable)";
351 if (Inst.isTerminator) OS << "|(1<<MCID::Terminator)";
352 if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)";
353 if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)";
354 if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)";
355 if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)";
356 if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)";
357 if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)";
358 if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)";
359 if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)";
360 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)";
361 if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)";
363 // Emit all of the target-specific flags...
364 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
365 if (!TSF) throw "no TSFlags?";
367 for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
368 if (BitInit *Bit = dynamic_cast<BitInit*>(TSF->getBit(i)))
369 Value |= uint64_t(Bit->getValue()) << i;
371 throw "Invalid TSFlags bit in " + Inst.TheDef->getName();
377 // Emit the implicit uses and defs lists...
378 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
382 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
384 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
388 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
390 // Emit the operand info.
391 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
392 if (OperandInfo.empty())
395 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
397 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
400 // emitEnums - Print out enum values for all of the instructions.
401 void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
403 OS << "\n#ifdef GET_INSTRINFO_ENUM\n";
404 OS << "#undef GET_INSTRINFO_ENUM\n";
406 OS << "namespace llvm {\n\n";
408 CodeGenTarget Target(Records);
410 // We must emit the PHI opcode first...
411 std::string Namespace = Target.getInstNamespace();
413 if (Namespace.empty()) {
414 fprintf(stderr, "No instructions defined!\n");
418 const std::vector<const CodeGenInstruction*> &NumberedInstructions =
419 Target.getInstructionsByEnumValue();
421 OS << "namespace " << Namespace << " {\n";
423 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
424 OS << " " << NumberedInstructions[i]->TheDef->getName()
425 << "\t= " << i << ",\n";
427 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
429 OS << "} // End llvm namespace \n";
431 OS << "#endif // GET_INSTRINFO_ENUM\n\n";
436 void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
437 InstrInfoEmitter(RK).run(OS);
440 } // End llvm namespace