1 //===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a "fast" instruction selector.
12 // This instruction selection method is designed to emit very poor code
13 // quickly. Also, it is not designed to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations (e.g. calls) are not
15 // supported and cannot easily be added. Blocks containing operations
16 // that are not supported need to be handled by a more capable selector,
17 // such as the SelectionDAG selector.
19 // The intended use for "fast" instruction selection is "-O0" mode
20 // compilation, where the quality of the generated code is irrelevant when
21 // weighed against the speed at which the code can be generated.
23 // If compile time is so important, you might wonder why we don't just
24 // skip codegen all-together, emit LLVM bytecode files, and execute them
25 // with an interpreter. The answer is that it would complicate linking and
26 // debugging, and also because that isn't how a compiler is expected to
27 // work in some circles.
29 // If you need better generated code or more lowering than what this
30 // instruction selector provides, use the SelectionDAG (DAGISel) instruction
31 // selector instead. If you're looking here because SelectionDAG isn't fast
32 // enough, consider looking into improving the SelectionDAG infastructure
33 // instead. At the time of this writing there remain several major
34 // opportunities for improvement.
36 //===----------------------------------------------------------------------===//
38 #include "FastISelEmitter.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/Streams.h"
42 #include "llvm/ADT/VectorExtras.h"
47 /// OperandsSignature - This class holds a description of a list of operand
48 /// types. It has utility methods for emitting text based on the operands.
50 struct OperandsSignature {
51 std::vector<std::string> Operands;
53 bool operator<(const OperandsSignature &O) const {
54 return Operands < O.Operands;
57 bool empty() const { return Operands.empty(); }
59 /// initialize - Examine the given pattern and initialize the contents
60 /// of the Operands array accordingly. Return true if all the operands
61 /// are supported, false otherwise.
63 bool initialize(TreePatternNode *InstPatNode,
64 const CodeGenTarget &Target,
65 MVT::SimpleValueType VT,
66 const CodeGenRegisterClass *DstRC) {
67 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
68 TreePatternNode *Op = InstPatNode->getChild(i);
69 // For now, filter out any operand with a predicate.
70 if (!Op->getPredicateFn().empty())
72 // For now, filter out any operand with multiple values.
73 if (Op->getExtTypes().size() != 1)
75 // For now, all the operands must have the same type.
76 if (Op->getTypeNum(0) != VT)
79 if (Op->getOperator()->getName() == "imm") {
80 Operands.push_back("i");
83 // For now, ignore fpimm and other non-leaf nodes.
86 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
89 Record *OpLeafRec = OpDI->getDef();
90 // TODO: handle instructions which have physreg operands.
91 if (OpLeafRec->isSubClassOf("Register"))
93 // For now, the only other thing we accept is register operands.
94 if (!OpLeafRec->isSubClassOf("RegisterClass"))
96 // For now, require the register operands' register classes to all
98 const CodeGenRegisterClass *RC = &Target.getRegisterClass(OpLeafRec);
101 // For now, all the operands must have the same register class.
104 Operands.push_back("r");
109 void PrintParameters(std::ostream &OS) const {
110 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
111 if (Operands[i] == "r") {
112 OS << "unsigned Op" << i;
113 } else if (Operands[i] == "i") {
114 OS << "uint64_t imm" << i;
116 assert("Unknown operand kind!");
124 void PrintArguments(std::ostream &OS) const {
125 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
126 if (Operands[i] == "r") {
128 } else if (Operands[i] == "i") {
131 assert("Unknown operand kind!");
139 void PrintManglingSuffix(std::ostream &OS) const {
140 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
146 /// InstructionMemo - This class holds additional information about an
147 /// instruction needed to emit code for it.
149 struct InstructionMemo {
151 const CodeGenRegisterClass *RC;
156 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
157 return CGP.getSDNodeInfo(Op).getEnumName();
160 static std::string getLegalCName(std::string OpName) {
161 std::string::size_type pos = OpName.find("::");
162 if (pos != std::string::npos)
163 OpName.replace(pos, 2, "_");
167 void FastISelEmitter::run(std::ostream &OS) {
168 EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
169 Target.getName() + " target", OS);
171 OS << "#include \"llvm/CodeGen/FastISel.h\"\n";
173 OS << "namespace llvm {\n";
175 OS << "namespace " << InstNS.substr(0, InstNS.size() - 2) << " {\n";
178 typedef std::map<std::string, InstructionMemo> PredMap;
179 typedef std::map<MVT::SimpleValueType, PredMap> TypePredMap;
180 typedef std::map<std::string, TypePredMap> OpcodeTypePredMap;
181 typedef std::map<OperandsSignature, OpcodeTypePredMap> OperandsOpcodeTypePredMap;
182 OperandsOpcodeTypePredMap SimplePatterns;
184 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
185 E = CGP.ptm_end(); I != E; ++I) {
186 const PatternToMatch &Pattern = *I;
188 // For now, just look at Instructions, so that we don't have to worry
189 // about emitting multiple instructions for a pattern.
190 TreePatternNode *Dst = Pattern.getDstPattern();
191 if (Dst->isLeaf()) continue;
192 Record *Op = Dst->getOperator();
193 if (!Op->isSubClassOf("Instruction"))
195 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op->getName());
196 if (II.OperandList.empty())
199 // For now, ignore instructions where the first operand is not an
201 Record *Op0Rec = II.OperandList[0].Rec;
202 if (!Op0Rec->isSubClassOf("RegisterClass"))
204 const CodeGenRegisterClass *DstRC = &Target.getRegisterClass(Op0Rec);
208 // Inspect the pattern.
209 TreePatternNode *InstPatNode = Pattern.getSrcPattern();
210 if (!InstPatNode) continue;
211 if (InstPatNode->isLeaf()) continue;
213 Record *InstPatOp = InstPatNode->getOperator();
214 std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
215 MVT::SimpleValueType VT = InstPatNode->getTypeNum(0);
217 // For now, filter out instructions which just set a register to
218 // an Operand or an immediate, like MOV32ri.
219 if (InstPatOp->isSubClassOf("Operand"))
221 if (InstPatOp->getName() == "imm" ||
222 InstPatOp->getName() == "fpimm")
225 // For now, filter out any instructions with predicates.
226 if (!InstPatNode->getPredicateFn().empty())
229 // Check all the operands.
230 OperandsSignature Operands;
231 if (!Operands.initialize(InstPatNode, Target, VT, DstRC))
234 // Get the predicate that guards this pattern.
235 std::string PredicateCheck = Pattern.getPredicateCheck();
237 // Ok, we found a pattern that we can handle. Remember it.
238 InstructionMemo Memo = {
239 Pattern.getDstPattern()->getOperator()->getName(),
242 assert(!SimplePatterns[Operands][OpcodeName][VT].count(PredicateCheck) &&
243 "Duplicate pattern!");
244 SimplePatterns[Operands][OpcodeName][VT][PredicateCheck] = Memo;
247 // Declare the target FastISel class.
248 OS << "class FastISel : public llvm::FastISel {\n";
249 for (OperandsOpcodeTypePredMap::const_iterator OI = SimplePatterns.begin(),
250 OE = SimplePatterns.end(); OI != OE; ++OI) {
251 const OperandsSignature &Operands = OI->first;
252 const OpcodeTypePredMap &OTM = OI->second;
254 for (OpcodeTypePredMap::const_iterator I = OTM.begin(), E = OTM.end();
256 const std::string &Opcode = I->first;
257 const TypePredMap &TM = I->second;
259 for (TypePredMap::const_iterator TI = TM.begin(), TE = TM.end();
261 MVT::SimpleValueType VT = TI->first;
263 OS << " unsigned FastEmit_" << getLegalCName(Opcode)
264 << "_" << getLegalCName(getName(VT)) << "_";
265 Operands.PrintManglingSuffix(OS);
267 Operands.PrintParameters(OS);
271 OS << " unsigned FastEmit_" << getLegalCName(Opcode) << "_";
272 Operands.PrintManglingSuffix(OS);
273 OS << "(MVT::SimpleValueType VT";
274 if (!Operands.empty())
276 Operands.PrintParameters(OS);
280 OS << " unsigned FastEmit_";
281 Operands.PrintManglingSuffix(OS);
282 OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
283 if (!Operands.empty())
285 Operands.PrintParameters(OS);
290 // Declare the Subtarget member, which is used for predicate checks.
291 OS << " const " << InstNS.substr(0, InstNS.size() - 2)
292 << "Subtarget *Subtarget;\n";
295 // Declare the constructor.
297 OS << " explicit FastISel(MachineFunction &mf)\n";
298 OS << " : llvm::FastISel(mf),\n";
299 OS << " Subtarget(&TM.getSubtarget<" << InstNS.substr(0, InstNS.size() - 2)
300 << "Subtarget>()) {}\n";
304 // Define the target FastISel creation function.
305 OS << "llvm::FastISel *createFastISel(MachineFunction &mf) {\n";
306 OS << " return new FastISel(mf);\n";
310 // Now emit code for all the patterns that we collected.
311 for (OperandsOpcodeTypePredMap::const_iterator OI = SimplePatterns.begin(),
312 OE = SimplePatterns.end(); OI != OE; ++OI) {
313 const OperandsSignature &Operands = OI->first;
314 const OpcodeTypePredMap &OTM = OI->second;
316 for (OpcodeTypePredMap::const_iterator I = OTM.begin(), E = OTM.end();
318 const std::string &Opcode = I->first;
319 const TypePredMap &TM = I->second;
321 OS << "// FastEmit functions for " << Opcode << ".\n";
324 // Emit one function for each opcode,type pair.
325 for (TypePredMap::const_iterator TI = TM.begin(), TE = TM.end();
327 MVT::SimpleValueType VT = TI->first;
328 const PredMap &PM = TI->second;
329 bool HasPred = false;
331 OS << "unsigned FastISel::FastEmit_"
332 << getLegalCName(Opcode)
333 << "_" << getLegalCName(getName(VT)) << "_";
334 Operands.PrintManglingSuffix(OS);
336 Operands.PrintParameters(OS);
339 // Emit code for each possible instruction. There may be
340 // multiple if there are subtarget concerns.
341 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
343 std::string PredicateCheck = PI->first;
344 const InstructionMemo &Memo = PI->second;
346 if (PredicateCheck.empty()) {
347 assert(!HasPred && "Multiple instructions match, at least one has "
348 "a predicate and at least one doesn't!");
350 OS << " if (" + PredicateCheck + ")\n";
354 OS << " return FastEmitInst_";
355 Operands.PrintManglingSuffix(OS);
356 OS << "(" << InstNS << Memo.Name << ", ";
357 OS << InstNS << Memo.RC->getName() << "RegisterClass";
358 if (!Operands.empty())
360 Operands.PrintArguments(OS);
363 // Return 0 if none of the predicates were satisfied.
365 OS << " return 0;\n";
370 // Emit one function for the opcode that demultiplexes based on the type.
371 OS << "unsigned FastISel::FastEmit_"
372 << getLegalCName(Opcode) << "_";
373 Operands.PrintManglingSuffix(OS);
374 OS << "(MVT::SimpleValueType VT";
375 if (!Operands.empty())
377 Operands.PrintParameters(OS);
379 OS << " switch (VT) {\n";
380 for (TypePredMap::const_iterator TI = TM.begin(), TE = TM.end();
382 MVT::SimpleValueType VT = TI->first;
383 std::string TypeName = getName(VT);
384 OS << " case " << TypeName << ": return FastEmit_"
385 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
386 Operands.PrintManglingSuffix(OS);
388 Operands.PrintArguments(OS);
391 OS << " default: return 0;\n";
397 // Emit one function for the operand signature that demultiplexes based
398 // on opcode and type.
399 OS << "unsigned FastISel::FastEmit_";
400 Operands.PrintManglingSuffix(OS);
401 OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
402 if (!Operands.empty())
404 Operands.PrintParameters(OS);
406 OS << " switch (Opcode) {\n";
407 for (OpcodeTypePredMap::const_iterator I = OTM.begin(), E = OTM.end();
409 const std::string &Opcode = I->first;
411 OS << " case " << Opcode << ": return FastEmit_"
412 << getLegalCName(Opcode) << "_";
413 Operands.PrintManglingSuffix(OS);
415 if (!Operands.empty())
417 Operands.PrintArguments(OS);
420 OS << " default: return 0;\n";
426 OS << "} // namespace X86\n";
428 OS << "} // namespace llvm\n";
431 FastISelEmitter::FastISelEmitter(RecordKeeper &R)
434 Target(CGP.getTargetInfo()),
435 InstNS(Target.getInstNamespace() + "::") {
437 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");