1 //===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a "fast" instruction selector.
12 // This instruction selection method is designed to emit very poor code
13 // quickly. Also, it is not designed to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations (e.g. calls) are not
15 // supported and cannot easily be added. Blocks containing operations
16 // that are not supported need to be handled by a more capable selector,
17 // such as the SelectionDAG selector.
19 // The intended use for "fast" instruction selection is "-O0" mode
20 // compilation, where the quality of the generated code is irrelevant when
21 // weighed against the speed at which the code can be generated.
23 // If compile time is so important, you might wonder why we don't just
24 // skip codegen all-together, emit LLVM bytecode files, and execute them
25 // with an interpreter. The answer is that it would complicate linking and
26 // debugging, and also because that isn't how a compiler is expected to
27 // work in some circles.
29 // If you need better generated code or more lowering than what this
30 // instruction selector provides, use the SelectionDAG (DAGISel) instruction
31 // selector instead. If you're looking here because SelectionDAG isn't fast
32 // enough, consider looking into improving the SelectionDAG infastructure
33 // instead. At the time of this writing there remain several major
34 // opportunities for improvement.
36 //===----------------------------------------------------------------------===//
38 #include "FastISelEmitter.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/Streams.h"
42 #include "llvm/ADT/VectorExtras.h"
47 /// OperandsSignature - This class holds a description of a list of operand
48 /// types. It has utility methods for emitting text based on the operands.
50 struct OperandsSignature {
51 std::vector<std::string> Operands;
53 bool operator<(const OperandsSignature &O) const {
54 return Operands < O.Operands;
57 bool empty() const { return Operands.empty(); }
59 /// initialize - Examine the given pattern and initialize the contents
60 /// of the Operands array accordingly. Return true if all the operands
61 /// are supported, false otherwise.
63 bool initialize(TreePatternNode *InstPatNode,
64 const CodeGenTarget &Target,
65 MVT::SimpleValueType VT,
66 const CodeGenRegisterClass *DstRC) {
67 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
68 TreePatternNode *Op = InstPatNode->getChild(i);
71 // For now, filter out any operand with a predicate.
72 if (!Op->getPredicateFn().empty())
74 DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
77 Record *OpLeafRec = OpDI->getDef();
78 // For now, only accept register operands.
79 if (!OpLeafRec->isSubClassOf("RegisterClass"))
81 // For now, require the register operands' register classes to all
83 const CodeGenRegisterClass *RC = &Target.getRegisterClass(OpLeafRec);
86 // For now, all the operands must have the same register class.
89 // For now, all the operands must have the same type.
90 if (Op->getTypeNum(0) != VT)
92 Operands.push_back("r");
97 void PrintParameters(std::ostream &OS) const {
98 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
99 if (Operands[i] == "r") {
100 OS << "unsigned Op" << i;
102 assert("Unknown operand kind!");
110 void PrintArguments(std::ostream &OS) const {
111 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
112 if (Operands[i] == "r") {
115 assert("Unknown operand kind!");
123 void PrintManglingSuffix(std::ostream &OS) const {
124 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
130 /// InstructionMemo - This class holds additional information about an
131 /// instruction needed to emit code for it.
133 struct InstructionMemo {
135 const CodeGenRegisterClass *RC;
140 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
141 return CGP.getSDNodeInfo(Op).getEnumName();
144 static std::string getLegalCName(std::string OpName) {
145 std::string::size_type pos = OpName.find("::");
146 if (pos != std::string::npos)
147 OpName.replace(pos, 2, "_");
151 void FastISelEmitter::run(std::ostream &OS) {
152 EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
153 Target.getName() + " target", OS);
155 OS << "#include \"llvm/CodeGen/FastISel.h\"\n";
157 OS << "namespace llvm {\n";
159 OS << "namespace " << InstNS.substr(0, InstNS.size() - 2) << " {\n";
162 typedef std::map<MVT::SimpleValueType, InstructionMemo> TypeMap;
163 typedef std::map<std::string, TypeMap> OpcodeTypeMap;
164 typedef std::map<OperandsSignature, OpcodeTypeMap> OperandsOpcodeTypeMap;
165 OperandsOpcodeTypeMap SimplePatterns;
167 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
168 E = CGP.ptm_end(); I != E; ++I) {
169 const PatternToMatch &Pattern = *I;
171 // For now, just look at Instructions, so that we don't have to worry
172 // about emitting multiple instructions for a pattern.
173 TreePatternNode *Dst = Pattern.getDstPattern();
174 if (Dst->isLeaf()) continue;
175 Record *Op = Dst->getOperator();
176 if (!Op->isSubClassOf("Instruction"))
178 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op->getName());
179 if (II.OperandList.empty())
182 // For now, ignore instructions where the first operand is not an
184 Record *Op0Rec = II.OperandList[0].Rec;
185 if (!Op0Rec->isSubClassOf("RegisterClass"))
187 const CodeGenRegisterClass *DstRC = &Target.getRegisterClass(Op0Rec);
191 // Inspect the pattern.
192 TreePatternNode *InstPatNode = Pattern.getSrcPattern();
193 if (!InstPatNode) continue;
194 if (InstPatNode->isLeaf()) continue;
196 Record *InstPatOp = InstPatNode->getOperator();
197 std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
198 MVT::SimpleValueType VT = InstPatNode->getTypeNum(0);
200 // For now, filter out instructions which just set a register to
201 // an Operand or an immediate, like MOV32ri.
202 if (InstPatOp->isSubClassOf("Operand"))
204 if (InstPatOp->getName() == "imm" ||
205 InstPatOp->getName() == "fpimm")
208 // For now, filter out any instructions with predicates.
209 if (!InstPatNode->getPredicateFn().empty())
212 // Check all the operands.
213 OperandsSignature Operands;
214 if (!Operands.initialize(InstPatNode, Target, VT, DstRC))
217 // Ok, we found a pattern that we can handle. Remember it.
218 InstructionMemo Memo = {
219 Pattern.getDstPattern()->getOperator()->getName(),
222 SimplePatterns[Operands][OpcodeName][VT] = Memo;
225 // Declare the target FastISel class.
226 OS << "class FastISel : public llvm::FastISel {\n";
227 for (OperandsOpcodeTypeMap::const_iterator OI = SimplePatterns.begin(),
228 OE = SimplePatterns.end(); OI != OE; ++OI) {
229 const OperandsSignature &Operands = OI->first;
230 const OpcodeTypeMap &OTM = OI->second;
232 for (OpcodeTypeMap::const_iterator I = OTM.begin(), E = OTM.end();
234 const std::string &Opcode = I->first;
235 const TypeMap &TM = I->second;
237 for (TypeMap::const_iterator TI = TM.begin(), TE = TM.end();
239 MVT::SimpleValueType VT = TI->first;
241 OS << " unsigned FastEmit_" << getLegalCName(Opcode)
242 << "_" << getLegalCName(getName(VT)) << "(";
243 Operands.PrintParameters(OS);
247 OS << " unsigned FastEmit_" << getLegalCName(Opcode)
248 << "(MVT::SimpleValueType VT";
249 if (!Operands.empty())
251 Operands.PrintParameters(OS);
255 OS << " unsigned FastEmit_";
256 Operands.PrintManglingSuffix(OS);
257 OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
258 if (!Operands.empty())
260 Operands.PrintParameters(OS);
264 OS << " explicit FastISel(MachineFunction &mf) : llvm::FastISel(mf) {}\n";
268 // Define the target FastISel creation function.
269 OS << "llvm::FastISel *createFastISel(MachineFunction &mf) {\n";
270 OS << " return new FastISel(mf);\n";
274 // Now emit code for all the patterns that we collected.
275 for (OperandsOpcodeTypeMap::const_iterator OI = SimplePatterns.begin(),
276 OE = SimplePatterns.end(); OI != OE; ++OI) {
277 const OperandsSignature &Operands = OI->first;
278 const OpcodeTypeMap &OTM = OI->second;
280 for (OpcodeTypeMap::const_iterator I = OTM.begin(), E = OTM.end();
282 const std::string &Opcode = I->first;
283 const TypeMap &TM = I->second;
285 OS << "// FastEmit functions for " << Opcode << ".\n";
288 // Emit one function for each opcode,type pair.
289 for (TypeMap::const_iterator TI = TM.begin(), TE = TM.end();
291 MVT::SimpleValueType VT = TI->first;
292 const InstructionMemo &Memo = TI->second;
294 OS << "unsigned FastISel::FastEmit_"
295 << getLegalCName(Opcode)
296 << "_" << getLegalCName(getName(VT)) << "(";
297 Operands.PrintParameters(OS);
299 OS << " return FastEmitInst_";
300 Operands.PrintManglingSuffix(OS);
301 OS << "(" << InstNS << Memo.Name << ", ";
302 OS << InstNS << Memo.RC->getName() << "RegisterClass";
303 if (!Operands.empty())
305 Operands.PrintArguments(OS);
311 // Emit one function for the opcode that demultiplexes based on the type.
312 OS << "unsigned FastISel::FastEmit_"
313 << getLegalCName(Opcode) << "(MVT::SimpleValueType VT";
314 if (!Operands.empty())
316 Operands.PrintParameters(OS);
318 OS << " switch (VT) {\n";
319 for (TypeMap::const_iterator TI = TM.begin(), TE = TM.end();
321 MVT::SimpleValueType VT = TI->first;
322 std::string TypeName = getName(VT);
323 OS << " case " << TypeName << ": return FastEmit_"
324 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "(";
325 Operands.PrintArguments(OS);
328 OS << " default: return 0;\n";
334 // Emit one function for the operand signature that demultiplexes based
335 // on opcode and type.
336 OS << "unsigned FastISel::FastEmit_";
337 Operands.PrintManglingSuffix(OS);
338 OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
339 if (!Operands.empty())
341 Operands.PrintParameters(OS);
343 OS << " switch (Opcode) {\n";
344 for (OpcodeTypeMap::const_iterator I = OTM.begin(), E = OTM.end();
346 const std::string &Opcode = I->first;
348 OS << " case " << Opcode << ": return FastEmit_"
349 << getLegalCName(Opcode) << "(VT";
350 if (!Operands.empty())
352 Operands.PrintArguments(OS);
355 OS << " default: return 0;\n";
361 OS << "} // namespace X86\n";
363 OS << "} // namespace llvm\n";
366 FastISelEmitter::FastISelEmitter(RecordKeeper &R)
369 Target(CGP.getTargetInfo()),
370 InstNS(Target.getInstNamespace() + "::") {
372 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");