1 //===- DFAPacketizerEmitter.cpp - Packetization DFA for a VLIW machine-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class parses the Schedule.td file and produces an API that can be used
11 // to reason about whether an instruction can be added to a packet on a VLIW
12 // architecture. The class internally generates a deterministic finite
13 // automaton (DFA) that models all possible mappings of machine instructions
14 // to functional units as instructions are added to a packet.
16 //===----------------------------------------------------------------------===//
18 #include "CodeGenTarget.h"
19 #include "llvm/ADT/DenseSet.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/TableGen/Record.h"
22 #include "llvm/TableGen/TableGenBackend.h"
29 // class DFAPacketizerEmitter: class that generates and prints out the DFA
30 // for resource tracking.
33 class DFAPacketizerEmitter {
35 std::string TargetName;
37 // allInsnClasses is the set of all possible resources consumed by an
40 DenseSet<unsigned> allInsnClasses;
41 RecordKeeper &Records;
44 DFAPacketizerEmitter(RecordKeeper &R);
47 // collectAllInsnClasses: Populate allInsnClasses which is a set of units
48 // used in each stage.
50 void collectAllInsnClasses(const std::string &Name,
55 void run(raw_ostream &OS);
57 } // End anonymous namespace.
61 // State represents the usage of machine resources if the packet contains
62 // a set of instruction classes.
64 // Specifically, currentState is a set of bit-masks.
65 // The nth bit in a bit-mask indicates whether the nth resource is being used
66 // by this state. The set of bit-masks in a state represent the different
67 // possible outcomes of transitioning to this state.
68 // For example: consider a two resource architecture: resource L and resource M
69 // with three instruction classes: L, M, and L_or_M.
70 // From the initial state (currentState = 0x00), if we add instruction class
71 // L_or_M we will transition to a state with currentState = [0x01, 0x10]. This
72 // represents the possible resource states that can result from adding a L_or_M
75 // Another way of thinking about this transition is we are mapping a NDFA with
76 // two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10].
78 // A State instance also contains a collection of transitions from that state:
79 // a map from inputs to new states.
84 static int currentStateNum;
87 std::set<unsigned> stateInfo;
88 typedef std::map<unsigned, State *> TransitionMap;
89 TransitionMap Transitions;
92 State(const State &S);
94 bool operator<(const State &s) const {
95 return stateNum < s.stateNum;
99 // canAddInsnClass - Returns true if an instruction of type InsnClass is a
100 // valid transition from this state, i.e., can an instruction of type InsnClass
101 // be added to the packet represented by this state.
103 // PossibleStates is the set of valid resource states that ensue from valid
106 bool canAddInsnClass(unsigned InsnClass) const;
108 // AddInsnClass - Return all combinations of resource reservation
109 // which are possible from this state (PossibleStates).
111 void AddInsnClass(unsigned InsnClass, std::set<unsigned> &PossibleStates);
113 // addTransition - Add a transition from this state given the input InsnClass
115 void addTransition(unsigned InsnClass, State *To);
117 // hasTransition - Returns true if there is a transition from this state
118 // given the input InsnClass
120 bool hasTransition(unsigned InsnClass);
122 } // End anonymous namespace.
125 // class DFA: deterministic finite automaton for processor resource tracking.
133 // Set of states. Need to keep this sorted to emit the transition table.
134 typedef std::set<State *, less_ptr<State> > StateSet;
142 void addState(State *);
145 // writeTable: Print out a table representing the DFA.
147 void writeTableAndAPI(raw_ostream &OS, const std::string &ClassName);
149 } // End anonymous namespace.
153 // Constructors and destructors for State and DFA
156 stateNum(currentStateNum++), isInitial(false) {}
159 State::State(const State &S) :
160 stateNum(currentStateNum++), isInitial(S.isInitial),
161 stateInfo(S.stateInfo) {}
163 DFA::DFA(): currentState(nullptr) {}
166 DeleteContainerPointers(states);
170 // addTransition - Add a transition from this state given the input InsnClass
172 void State::addTransition(unsigned InsnClass, State *To) {
173 assert(!Transitions.count(InsnClass) &&
174 "Cannot have multiple transitions for the same input");
175 Transitions[InsnClass] = To;
179 // hasTransition - Returns true if there is a transition from this state
180 // given the input InsnClass
182 bool State::hasTransition(unsigned InsnClass) {
183 return Transitions.count(InsnClass) > 0;
187 // AddInsnClass - Return all combinations of resource reservation
188 // which are possible from this state (PossibleStates).
190 void State::AddInsnClass(unsigned InsnClass,
191 std::set<unsigned> &PossibleStates) {
193 // Iterate over all resource states in currentState.
196 for (std::set<unsigned>::iterator SI = stateInfo.begin();
197 SI != stateInfo.end(); ++SI) {
198 unsigned thisState = *SI;
201 // Iterate over all possible resources used in InsnClass.
202 // For ex: for InsnClass = 0x11, all resources = {0x01, 0x10}.
205 DenseSet<unsigned> VisitedResourceStates;
206 for (unsigned int j = 0; j < sizeof(InsnClass) * 8; ++j) {
207 if ((0x1 << j) & InsnClass) {
209 // For each possible resource used in InsnClass, generate the
210 // resource state if that resource was used.
212 unsigned ResultingResourceState = thisState | (0x1 << j);
214 // Check if the resulting resource state can be accommodated in this
216 // We compute ResultingResourceState OR thisState.
217 // If the result of the OR is different than thisState, it implies
218 // that there is at least one resource that can be used to schedule
219 // InsnClass in the current packet.
220 // Insert ResultingResourceState into PossibleStates only if we haven't
221 // processed ResultingResourceState before.
223 if ((ResultingResourceState != thisState) &&
224 (VisitedResourceStates.count(ResultingResourceState) == 0)) {
225 VisitedResourceStates.insert(ResultingResourceState);
226 PossibleStates.insert(ResultingResourceState);
236 // canAddInsnClass - Quickly verifies if an instruction of type InsnClass is a
237 // valid transition from this state i.e., can an instruction of type InsnClass
238 // be added to the packet represented by this state.
240 bool State::canAddInsnClass(unsigned InsnClass) const {
241 for (std::set<unsigned>::const_iterator SI = stateInfo.begin();
242 SI != stateInfo.end(); ++SI) {
243 if (~*SI & InsnClass)
250 void DFA::addState(State *S) {
251 assert(!states.count(S) && "State already exists");
256 int State::currentStateNum = 0;
258 DFAPacketizerEmitter::DFAPacketizerEmitter(RecordKeeper &R):
259 TargetName(CodeGenTarget(R).getName()),
260 allInsnClasses(), Records(R) {}
264 // writeTableAndAPI - Print out a table representing the DFA and the
265 // associated API to create a DFA packetizer.
268 // DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
270 // DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable for
274 void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName) {
275 static const std::string SentinelEntry = "{-1, -1}";
276 DFA::StateSet::iterator SI = states.begin();
277 // This table provides a map to the beginning of the transitions for State s
278 // in DFAStateInputTable.
279 std::vector<int> StateEntry(states.size());
281 OS << "namespace llvm {\n\n";
282 OS << "const int " << TargetName << "DFAStateInputTable[][2] = {\n";
284 // Tracks the total valid transitions encountered so far. It is used
285 // to construct the StateEntry table.
286 int ValidTransitions = 0;
287 for (unsigned i = 0; i < states.size(); ++i, ++SI) {
288 assert (((*SI)->stateNum == (int) i) && "Mismatch in state numbers");
289 StateEntry[i] = ValidTransitions;
290 for (State::TransitionMap::iterator
291 II = (*SI)->Transitions.begin(), IE = (*SI)->Transitions.end();
293 OS << "{" << II->first << ", "
294 << II->second->stateNum
297 ValidTransitions += (*SI)->Transitions.size();
299 // If there are no valid transitions from this stage, we need a sentinel
301 if (ValidTransitions == StateEntry[i]) {
302 OS << SentinelEntry << ",";
309 // Print out a sentinel entry at the end of the StateInputTable. This is
310 // needed to iterate over StateInputTable in DFAPacketizer::ReadTable()
311 OS << SentinelEntry << "\n";
314 OS << "const unsigned int " << TargetName << "DFAStateEntryTable[] = {\n";
316 // Multiply i by 2 since each entry in DFAStateInputTable is a set of
318 for (unsigned i = 0; i < states.size(); ++i)
319 OS << StateEntry[i] << ", ";
321 // Print out the index to the sentinel entry in StateInputTable
322 OS << ValidTransitions << ", ";
325 OS << "} // namespace\n";
329 // Emit DFA Packetizer tables if the target is a VLIW machine.
331 std::string SubTargetClassName = TargetName + "GenSubtargetInfo";
332 OS << "\n" << "#include \"llvm/CodeGen/DFAPacketizer.h\"\n";
333 OS << "namespace llvm {\n";
334 OS << "DFAPacketizer *" << SubTargetClassName << "::"
335 << "createDFAPacketizer(const InstrItineraryData *IID) const {\n"
336 << " return new DFAPacketizer(IID, " << TargetName
337 << "DFAStateInputTable, " << TargetName << "DFAStateEntryTable);\n}\n\n";
338 OS << "} // End llvm namespace \n";
343 // collectAllInsnClasses - Populate allInsnClasses which is a set of units
344 // used in each stage.
346 void DFAPacketizerEmitter::collectAllInsnClasses(const std::string &Name,
350 // Collect processor itineraries.
351 std::vector<Record*> ProcItinList =
352 Records.getAllDerivedDefinitions("ProcessorItineraries");
354 // If just no itinerary then don't bother.
355 if (ProcItinList.size() < 2)
357 std::map<std::string, unsigned> NameToBitsMap;
359 // Parse functional units for all the itineraries.
360 for (unsigned i = 0, N = ProcItinList.size(); i < N; ++i) {
361 Record *Proc = ProcItinList[i];
362 std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU");
364 // Convert macros to bits for each stage.
365 for (unsigned i = 0, N = FUs.size(); i < N; ++i)
366 NameToBitsMap[FUs[i]->getName()] = (unsigned) (1U << i);
369 const std::vector<Record*> &StageList =
370 ItinData->getValueAsListOfDefs("Stages");
372 // The number of stages.
373 NStages = StageList.size();
376 unsigned UnitBitValue = 0;
378 // Compute the bitwise or of each unit used in this stage.
379 for (unsigned i = 0; i < NStages; ++i) {
380 const Record *Stage = StageList[i];
383 const std::vector<Record*> &UnitList =
384 Stage->getValueAsListOfDefs("Units");
386 for (unsigned j = 0, M = UnitList.size(); j < M; ++j) {
387 // Conduct bitwise or.
388 std::string UnitName = UnitList[j]->getName();
389 assert(NameToBitsMap.count(UnitName));
390 UnitBitValue |= NameToBitsMap[UnitName];
393 if (UnitBitValue != 0)
394 allInsnClasses.insert(UnitBitValue);
400 // Run the worklist algorithm to generate the DFA.
402 void DFAPacketizerEmitter::run(raw_ostream &OS) {
404 // Collect processor iteraries.
405 std::vector<Record*> ProcItinList =
406 Records.getAllDerivedDefinitions("ProcessorItineraries");
409 // Collect the instruction classes.
411 for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
412 Record *Proc = ProcItinList[i];
414 // Get processor itinerary name.
415 const std::string &Name = Proc->getName();
418 if (Name == "NoItineraries")
421 // Sanity check for at least one instruction itinerary class.
422 unsigned NItinClasses =
423 Records.getAllDerivedDefinitions("InstrItinClass").size();
424 if (NItinClasses == 0)
427 // Get itinerary data list.
428 std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
430 // Collect instruction classes for all itinerary data.
431 for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
432 Record *ItinData = ItinDataList[j];
434 collectAllInsnClasses(Name, ItinData, NStages, OS);
440 // Run a worklist algorithm to generate the DFA.
443 State *Initial = new State;
444 Initial->isInitial = true;
445 Initial->stateInfo.insert(0x0);
447 SmallVector<State*, 32> WorkList;
448 std::map<std::set<unsigned>, State*> Visited;
450 WorkList.push_back(Initial);
453 // Worklist algorithm to create a DFA for processor resource tracking.
454 // C = {set of InsnClasses}
455 // Begin with initial node in worklist. Initial node does not have
456 // any consumed resources,
457 // ResourceState = 0x0
459 // While worklist != empty
460 // S = first element of worklist
461 // For every instruction class C
462 // if we can accommodate C in S:
463 // S' = state with resource states = {S Union C}
464 // Add a new transition: S x C -> S'
465 // If S' is not in Visited:
466 // Add S' to worklist
469 while (!WorkList.empty()) {
470 State *current = WorkList.pop_back_val();
471 for (DenseSet<unsigned>::iterator CI = allInsnClasses.begin(),
472 CE = allInsnClasses.end(); CI != CE; ++CI) {
473 unsigned InsnClass = *CI;
475 std::set<unsigned> NewStateResources;
477 // If we haven't already created a transition for this input
478 // and the state can accommodate this InsnClass, create a transition.
480 if (!current->hasTransition(InsnClass) &&
481 current->canAddInsnClass(InsnClass)) {
482 State *NewState = nullptr;
483 current->AddInsnClass(InsnClass, NewStateResources);
484 assert(NewStateResources.size() && "New states must be generated");
487 // If we have seen this state before, then do not create a new state.
490 std::map<std::set<unsigned>, State*>::iterator VI;
491 if ((VI = Visited.find(NewStateResources)) != Visited.end())
492 NewState = VI->second;
494 NewState = new State;
495 NewState->stateInfo = NewStateResources;
496 D.addState(NewState);
497 Visited[NewStateResources] = NewState;
498 WorkList.push_back(NewState);
501 current->addTransition(InsnClass, NewState);
506 // Print out the table.
507 D.writeTableAndAPI(OS, TargetName);
512 void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS) {
513 emitSourceFileHeader("Target DFA Packetizer Tables", OS);
514 DFAPacketizerEmitter(RK).run(OS);
517 } // End llvm namespace