1 //===- DAGISelMatcherGen.cpp - Matcher generator --------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "DAGISelMatcher.h"
11 #include "CodeGenDAGPatterns.h"
13 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/ADT/StringMap.h"
19 /// getRegisterValueType - Look up and return the ValueType of the specified
20 /// register. If the register is a member of multiple register classes which
21 /// have different associated types, return MVT::Other.
22 static MVT::SimpleValueType getRegisterValueType(Record *R,
23 const CodeGenTarget &T) {
25 MVT::SimpleValueType VT = MVT::Other;
26 const std::vector<CodeGenRegisterClass> &RCs = T.getRegisterClasses();
27 std::vector<Record*>::const_iterator Element;
29 for (unsigned rc = 0, e = RCs.size(); rc != e; ++rc) {
30 const CodeGenRegisterClass &RC = RCs[rc];
31 if (!std::count(RC.Elements.begin(), RC.Elements.end(), R))
36 VT = RC.getValueTypeNum(0);
40 // If this occurs in multiple register classes, they all have to agree.
41 assert(VT == RC.getValueTypeNum(0));
49 const PatternToMatch &Pattern;
50 const CodeGenDAGPatterns &CGP;
52 /// PatWithNoTypes - This is a clone of Pattern.getSrcPattern() that starts
53 /// out with all of the types removed. This allows us to insert type checks
54 /// as we scan the tree.
55 TreePatternNode *PatWithNoTypes;
57 /// VariableMap - A map from variable names ('$dst') to the recorded operand
58 /// number that they were captured as. These are biased by 1 to make
60 StringMap<unsigned> VariableMap;
62 /// NextRecordedOperandNo - As we emit opcodes to record matched values in
63 /// the RecordedNodes array, this keeps track of which slot will be next to
65 unsigned NextRecordedOperandNo;
67 /// MatchedChainNodes - This maintains the position in the recorded nodes
68 /// array of all of the recorded input nodes that have chains.
69 SmallVector<unsigned, 2> MatchedChainNodes;
71 /// MatchedFlagResultNodes - This maintains the position in the recorded
72 /// nodes array of all of the recorded input nodes that have flag results.
73 SmallVector<unsigned, 2> MatchedFlagResultNodes;
75 /// MatchedComplexPatterns - This maintains a list of all of the
76 /// ComplexPatterns that we need to check. The patterns are known to have
77 /// names which were recorded. The second element of each pair is the first
78 /// slot number that the OPC_CheckComplexPat opcode drops the matched
80 SmallVector<std::pair<const TreePatternNode*,
81 unsigned>, 2> MatchedComplexPatterns;
83 /// PhysRegInputs - List list has an entry for each explicitly specified
84 /// physreg input to the pattern. The first elt is the Register node, the
85 /// second is the recorded slot number the input pattern match saved it in.
86 SmallVector<std::pair<Record*, unsigned>, 2> PhysRegInputs;
88 /// Matcher - This is the top level of the generated matcher, the result.
91 /// CurPredicate - As we emit matcher nodes, this points to the latest check
92 /// which should have future checks stuck into its Next position.
93 Matcher *CurPredicate;
95 MatcherGen(const PatternToMatch &pattern, const CodeGenDAGPatterns &cgp);
98 delete PatWithNoTypes;
101 bool EmitMatcherCode(unsigned Variant);
102 void EmitResultCode();
104 Matcher *GetMatcher() const { return TheMatcher; }
105 Matcher *GetCurPredicate() const { return CurPredicate; }
107 void AddMatcher(Matcher *NewNode);
108 void InferPossibleTypes();
110 // Matcher Generation.
111 void EmitMatchCode(const TreePatternNode *N, TreePatternNode *NodeNoTypes);
112 void EmitLeafMatchCode(const TreePatternNode *N);
113 void EmitOperatorMatchCode(const TreePatternNode *N,
114 TreePatternNode *NodeNoTypes);
116 // Result Code Generation.
117 unsigned getNamedArgumentSlot(StringRef Name) {
118 unsigned VarMapEntry = VariableMap[Name];
119 assert(VarMapEntry != 0 &&
120 "Variable referenced but not defined and not caught earlier!");
121 return VarMapEntry-1;
124 /// GetInstPatternNode - Get the pattern for an instruction.
125 const TreePatternNode *GetInstPatternNode(const DAGInstruction &Ins,
126 const TreePatternNode *N);
128 void EmitResultOperand(const TreePatternNode *N,
129 SmallVectorImpl<unsigned> &ResultOps);
130 void EmitResultOfNamedOperand(const TreePatternNode *N,
131 SmallVectorImpl<unsigned> &ResultOps);
132 void EmitResultLeafAsOperand(const TreePatternNode *N,
133 SmallVectorImpl<unsigned> &ResultOps);
134 void EmitResultInstructionAsOperand(const TreePatternNode *N,
135 SmallVectorImpl<unsigned> &ResultOps);
136 void EmitResultSDNodeXFormAsOperand(const TreePatternNode *N,
137 SmallVectorImpl<unsigned> &ResultOps);
140 } // end anon namespace.
142 MatcherGen::MatcherGen(const PatternToMatch &pattern,
143 const CodeGenDAGPatterns &cgp)
144 : Pattern(pattern), CGP(cgp), NextRecordedOperandNo(0),
145 TheMatcher(0), CurPredicate(0) {
146 // We need to produce the matcher tree for the patterns source pattern. To do
147 // this we need to match the structure as well as the types. To do the type
148 // matching, we want to figure out the fewest number of type checks we need to
149 // emit. For example, if there is only one integer type supported by a
150 // target, there should be no type comparisons at all for integer patterns!
152 // To figure out the fewest number of type checks needed, clone the pattern,
153 // remove the types, then perform type inference on the pattern as a whole.
154 // If there are unresolved types, emit an explicit check for those types,
155 // apply the type to the tree, then rerun type inference. Iterate until all
156 // types are resolved.
158 PatWithNoTypes = Pattern.getSrcPattern()->clone();
159 PatWithNoTypes->RemoveAllTypes();
161 // If there are types that are manifestly known, infer them.
162 InferPossibleTypes();
165 /// InferPossibleTypes - As we emit the pattern, we end up generating type
166 /// checks and applying them to the 'PatWithNoTypes' tree. As we do this, we
167 /// want to propagate implied types as far throughout the tree as possible so
168 /// that we avoid doing redundant type checks. This does the type propagation.
169 void MatcherGen::InferPossibleTypes() {
170 // TP - Get *SOME* tree pattern, we don't care which. It is only used for
171 // diagnostics, which we know are impossible at this point.
172 TreePattern &TP = *CGP.pf_begin()->second;
175 bool MadeChange = true;
177 MadeChange = PatWithNoTypes->ApplyTypeConstraints(TP,
178 true/*Ignore reg constraints*/);
180 errs() << "Type constraint application shouldn't fail!";
186 /// AddMatcher - Add a matcher node to the current graph we're building.
187 void MatcherGen::AddMatcher(Matcher *NewNode) {
188 if (CurPredicate != 0)
189 CurPredicate->setNext(NewNode);
191 TheMatcher = NewNode;
192 CurPredicate = NewNode;
196 //===----------------------------------------------------------------------===//
197 // Pattern Match Generation
198 //===----------------------------------------------------------------------===//
200 /// EmitLeafMatchCode - Generate matching code for leaf nodes.
201 void MatcherGen::EmitLeafMatchCode(const TreePatternNode *N) {
202 assert(N->isLeaf() && "Not a leaf?");
204 // Direct match against an integer constant.
205 if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
206 // If this is the root of the dag we're matching, we emit a redundant opcode
207 // check to ensure that this gets folded into the normal top-level
209 if (N == Pattern.getSrcPattern()) {
210 const SDNodeInfo &NI = CGP.getSDNodeInfo(CGP.getSDNodeNamed("imm"));
211 AddMatcher(new CheckOpcodeMatcher(NI));
214 return AddMatcher(new CheckIntegerMatcher(II->getValue()));
217 DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue());
219 errs() << "Unknown leaf kind: " << *DI << "\n";
223 Record *LeafRec = DI->getDef();
224 if (// Handle register references. Nothing to do here, they always match.
225 LeafRec->isSubClassOf("RegisterClass") ||
226 LeafRec->isSubClassOf("PointerLikeRegClass") ||
227 // Place holder for SRCVALUE nodes. Nothing to do here.
228 LeafRec->getName() == "srcvalue")
231 // If we have a physreg reference like (mul gpr:$src, EAX) then we need to
232 // record the register
233 if (LeafRec->isSubClassOf("Register")) {
234 AddMatcher(new RecordMatcher("physreg input "+LeafRec->getName(),
235 NextRecordedOperandNo));
236 PhysRegInputs.push_back(std::make_pair(LeafRec, NextRecordedOperandNo++));
240 if (LeafRec->isSubClassOf("ValueType"))
241 return AddMatcher(new CheckValueTypeMatcher(LeafRec->getName()));
243 if (LeafRec->isSubClassOf("CondCode"))
244 return AddMatcher(new CheckCondCodeMatcher(LeafRec->getName()));
246 if (LeafRec->isSubClassOf("ComplexPattern")) {
247 // We can't model ComplexPattern uses that don't have their name taken yet.
248 // The OPC_CheckComplexPattern operation implicitly records the results.
249 if (N->getName().empty()) {
250 errs() << "We expect complex pattern uses to have names: " << *N << "\n";
254 // Remember this ComplexPattern so that we can emit it after all the other
255 // structural matches are done.
256 MatchedComplexPatterns.push_back(std::make_pair(N, 0));
260 errs() << "Unknown leaf kind: " << *N << "\n";
264 void MatcherGen::EmitOperatorMatchCode(const TreePatternNode *N,
265 TreePatternNode *NodeNoTypes) {
266 assert(!N->isLeaf() && "Not an operator?");
267 const SDNodeInfo &CInfo = CGP.getSDNodeInfo(N->getOperator());
269 // If this is an 'and R, 1234' where the operation is AND/OR and the RHS is
270 // a constant without a predicate fn that has more that one bit set, handle
271 // this as a special case. This is usually for targets that have special
272 // handling of certain large constants (e.g. alpha with it's 8/16/32-bit
273 // handling stuff). Using these instructions is often far more efficient
274 // than materializing the constant. Unfortunately, both the instcombiner
275 // and the dag combiner can often infer that bits are dead, and thus drop
276 // them from the mask in the dag. For example, it might turn 'AND X, 255'
277 // into 'AND X, 254' if it knows the low bit is set. Emit code that checks
279 if ((N->getOperator()->getName() == "and" ||
280 N->getOperator()->getName() == "or") &&
281 N->getChild(1)->isLeaf() && N->getChild(1)->getPredicateFns().empty() &&
282 N->getPredicateFns().empty()) {
283 if (IntInit *II = dynamic_cast<IntInit*>(N->getChild(1)->getLeafValue())) {
284 if (!isPowerOf2_32(II->getValue())) { // Don't bother with single bits.
285 // If this is at the root of the pattern, we emit a redundant
286 // CheckOpcode so that the following checks get factored properly under
287 // a single opcode check.
288 if (N == Pattern.getSrcPattern())
289 AddMatcher(new CheckOpcodeMatcher(CInfo));
291 // Emit the CheckAndImm/CheckOrImm node.
292 if (N->getOperator()->getName() == "and")
293 AddMatcher(new CheckAndImmMatcher(II->getValue()));
295 AddMatcher(new CheckOrImmMatcher(II->getValue()));
297 // Match the LHS of the AND as appropriate.
298 AddMatcher(new MoveChildMatcher(0));
299 EmitMatchCode(N->getChild(0), NodeNoTypes->getChild(0));
300 AddMatcher(new MoveParentMatcher());
306 // Check that the current opcode lines up.
307 AddMatcher(new CheckOpcodeMatcher(CInfo));
309 // If this node has memory references (i.e. is a load or store), tell the
310 // interpreter to capture them in the memref array.
311 if (N->NodeHasProperty(SDNPMemOperand, CGP))
312 AddMatcher(new RecordMemRefMatcher());
314 // If this node has a chain, then the chain is operand #0 is the SDNode, and
315 // the child numbers of the node are all offset by one.
317 if (N->NodeHasProperty(SDNPHasChain, CGP)) {
318 // Record the node and remember it in our chained nodes list.
319 AddMatcher(new RecordMatcher("'" + N->getOperator()->getName() +
321 NextRecordedOperandNo));
322 // Remember all of the input chains our pattern will match.
323 MatchedChainNodes.push_back(NextRecordedOperandNo++);
325 // Don't look at the input chain when matching the tree pattern to the
329 // If this node is not the root and the subtree underneath it produces a
330 // chain, then the result of matching the node is also produce a chain.
331 // Beyond that, this means that we're also folding (at least) the root node
332 // into the node that produce the chain (for example, matching
333 // "(add reg, (load ptr))" as a add_with_memory on X86). This is
334 // problematic, if the 'reg' node also uses the load (say, its chain).
339 // | \ DAG's like cheese.
345 // It would be invalid to fold XX and LD. In this case, folding the two
346 // nodes together would induce a cycle in the DAG, making it a 'cyclic DAG'
347 // To prevent this, we emit a dynamic check for legality before allowing
348 // this to be folded.
350 const TreePatternNode *Root = Pattern.getSrcPattern();
351 if (N != Root) { // Not the root of the pattern.
352 // If there is a node between the root and this node, then we definitely
353 // need to emit the check.
354 bool NeedCheck = !Root->hasChild(N);
356 // If it *is* an immediate child of the root, we can still need a check if
357 // the root SDNode has multiple inputs. For us, this means that it is an
358 // intrinsic, has multiple operands, or has other inputs like chain or
361 const SDNodeInfo &PInfo = CGP.getSDNodeInfo(Root->getOperator());
363 Root->getOperator() == CGP.get_intrinsic_void_sdnode() ||
364 Root->getOperator() == CGP.get_intrinsic_w_chain_sdnode() ||
365 Root->getOperator() == CGP.get_intrinsic_wo_chain_sdnode() ||
366 PInfo.getNumOperands() > 1 ||
367 PInfo.hasProperty(SDNPHasChain) ||
368 PInfo.hasProperty(SDNPInFlag) ||
369 PInfo.hasProperty(SDNPOptInFlag);
373 AddMatcher(new CheckFoldableChainNodeMatcher());
377 // If this node has an output flag and isn't the root, remember it.
378 if (N->NodeHasProperty(SDNPOutFlag, CGP) &&
379 N != Pattern.getSrcPattern()) {
380 // TODO: This redundantly records nodes with both flags and chains.
382 // Record the node and remember it in our chained nodes list.
383 AddMatcher(new RecordMatcher("'" + N->getOperator()->getName() +
384 "' flag output node",
385 NextRecordedOperandNo));
386 // Remember all of the nodes with output flags our pattern will match.
387 MatchedFlagResultNodes.push_back(NextRecordedOperandNo++);
390 // If this node is known to have an input flag or if it *might* have an input
391 // flag, capture it as the flag input of the pattern.
392 if (N->NodeHasProperty(SDNPOptInFlag, CGP) ||
393 N->NodeHasProperty(SDNPInFlag, CGP))
394 AddMatcher(new CaptureFlagInputMatcher());
396 for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
397 // Get the code suitable for matching this child. Move to the child, check
398 // it then move back to the parent.
399 AddMatcher(new MoveChildMatcher(OpNo));
400 EmitMatchCode(N->getChild(i), NodeNoTypes->getChild(i));
401 AddMatcher(new MoveParentMatcher());
406 void MatcherGen::EmitMatchCode(const TreePatternNode *N,
407 TreePatternNode *NodeNoTypes) {
408 // If N and NodeNoTypes don't agree on a type, then this is a case where we
409 // need to do a type check. Emit the check, apply the tyep to NodeNoTypes and
410 // reinfer any correlated types.
411 unsigned NodeType = EEVT::isUnknown;
412 if (NodeNoTypes->getExtTypes() != N->getExtTypes()) {
413 NodeType = N->getTypeNum(0);
414 NodeNoTypes->setTypes(N->getExtTypes());
415 InferPossibleTypes();
418 // If this node has a name associated with it, capture it in VariableMap. If
419 // we already saw this in the pattern, emit code to verify dagness.
420 if (!N->getName().empty()) {
421 unsigned &VarMapEntry = VariableMap[N->getName()];
422 if (VarMapEntry == 0) {
423 // If it is a named node, we must emit a 'Record' opcode.
424 AddMatcher(new RecordMatcher("$" + N->getName(), NextRecordedOperandNo));
425 VarMapEntry = ++NextRecordedOperandNo;
427 // If we get here, this is a second reference to a specific name. Since
428 // we already have checked that the first reference is valid, we don't
429 // have to recursively match it, just check that it's the same as the
430 // previously named thing.
431 AddMatcher(new CheckSameMatcher(VarMapEntry-1));
437 EmitLeafMatchCode(N);
439 EmitOperatorMatchCode(N, NodeNoTypes);
441 // If there are node predicates for this node, generate their checks.
442 for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i)
443 AddMatcher(new CheckPredicateMatcher(N->getPredicateFns()[i]));
445 if (NodeType != EEVT::isUnknown)
446 AddMatcher(new CheckTypeMatcher((MVT::SimpleValueType)NodeType));
449 /// EmitMatcherCode - Generate the code that matches the predicate of this
450 /// pattern for the specified Variant. If the variant is invalid this returns
451 /// true and does not generate code, if it is valid, it returns false.
452 bool MatcherGen::EmitMatcherCode(unsigned Variant) {
453 // If the root of the pattern is a ComplexPattern and if it is specified to
454 // match some number of root opcodes, these are considered to be our variants.
455 // Depending on which variant we're generating code for, emit the root opcode
457 if (const ComplexPattern *CP =
458 Pattern.getSrcPattern()->getComplexPatternInfo(CGP)) {
459 const std::vector<Record*> &OpNodes = CP->getRootNodes();
460 assert(!OpNodes.empty() &&"Complex Pattern must specify what it can match");
461 if (Variant >= OpNodes.size()) return true;
463 AddMatcher(new CheckOpcodeMatcher(CGP.getSDNodeInfo(OpNodes[Variant])));
465 if (Variant != 0) return true;
468 // Emit the matcher for the pattern structure and types.
469 EmitMatchCode(Pattern.getSrcPattern(), PatWithNoTypes);
471 // If the pattern has a predicate on it (e.g. only enabled when a subtarget
472 // feature is around, do the check).
473 if (!Pattern.getPredicateCheck().empty())
474 AddMatcher(new CheckPatternPredicateMatcher(Pattern.getPredicateCheck()));
476 // Now that we've completed the structural type match, emit any ComplexPattern
477 // checks (e.g. addrmode matches). We emit this after the structural match
478 // because they are generally more expensive to evaluate and more difficult to
480 for (unsigned i = 0, e = MatchedComplexPatterns.size(); i != e; ++i) {
481 const TreePatternNode *N = MatchedComplexPatterns[i].first;
483 // Remember where the results of this match get stuck.
484 MatchedComplexPatterns[i].second = NextRecordedOperandNo;
486 // Get the slot we recorded the value in from the name on the node.
487 unsigned RecNodeEntry = VariableMap[N->getName()];
488 assert(!N->getName().empty() && RecNodeEntry &&
489 "Complex pattern should have a name and slot");
490 --RecNodeEntry; // Entries in VariableMap are biased.
492 const ComplexPattern &CP =
493 CGP.getComplexPattern(((DefInit*)N->getLeafValue())->getDef());
495 // Emit a CheckComplexPat operation, which does the match (aborting if it
496 // fails) and pushes the matched operands onto the recorded nodes list.
497 AddMatcher(new CheckComplexPatMatcher(CP, RecNodeEntry,
498 N->getName(), NextRecordedOperandNo));
500 // Record the right number of operands.
501 NextRecordedOperandNo += CP.getNumOperands();
502 if (CP.hasProperty(SDNPHasChain)) {
503 // If the complex pattern has a chain, then we need to keep track of the
504 // fact that we just recorded a chain input. The chain input will be
505 // matched as the last operand of the predicate if it was successful.
506 ++NextRecordedOperandNo; // Chained node operand.
508 // It is the last operand recorded.
509 assert(NextRecordedOperandNo > 1 &&
510 "Should have recorded input/result chains at least!");
511 MatchedChainNodes.push_back(NextRecordedOperandNo-1);
514 // TODO: Complex patterns can't have output flags, if they did, we'd want
522 //===----------------------------------------------------------------------===//
523 // Node Result Generation
524 //===----------------------------------------------------------------------===//
526 void MatcherGen::EmitResultOfNamedOperand(const TreePatternNode *N,
527 SmallVectorImpl<unsigned> &ResultOps){
528 assert(!N->getName().empty() && "Operand not named!");
530 // A reference to a complex pattern gets all of the results of the complex
532 if (const ComplexPattern *CP = N->getComplexPatternInfo(CGP)) {
534 for (unsigned i = 0, e = MatchedComplexPatterns.size(); i != e; ++i)
535 if (MatchedComplexPatterns[i].first->getName() == N->getName()) {
536 SlotNo = MatchedComplexPatterns[i].second;
539 assert(SlotNo != 0 && "Didn't get a slot number assigned?");
541 // The first slot entry is the node itself, the subsequent entries are the
543 for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i)
544 ResultOps.push_back(SlotNo+i);
548 unsigned SlotNo = getNamedArgumentSlot(N->getName());
550 // If this is an 'imm' or 'fpimm' node, make sure to convert it to the target
551 // version of the immediate so that it doesn't get selected due to some other
554 StringRef OperatorName = N->getOperator()->getName();
555 if (OperatorName == "imm" || OperatorName == "fpimm") {
556 AddMatcher(new EmitConvertToTargetMatcher(SlotNo));
557 ResultOps.push_back(NextRecordedOperandNo++);
562 ResultOps.push_back(SlotNo);
565 void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N,
566 SmallVectorImpl<unsigned> &ResultOps) {
567 assert(N->isLeaf() && "Must be a leaf");
569 if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
570 AddMatcher(new EmitIntegerMatcher(II->getValue(),N->getTypeNum(0)));
571 ResultOps.push_back(NextRecordedOperandNo++);
575 // If this is an explicit register reference, handle it.
576 if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) {
577 if (DI->getDef()->isSubClassOf("Register")) {
578 AddMatcher(new EmitRegisterMatcher(DI->getDef(),
580 ResultOps.push_back(NextRecordedOperandNo++);
584 if (DI->getDef()->getName() == "zero_reg") {
585 AddMatcher(new EmitRegisterMatcher(0, N->getTypeNum(0)));
586 ResultOps.push_back(NextRecordedOperandNo++);
590 // Handle a reference to a register class. This is used
591 // in COPY_TO_SUBREG instructions.
592 if (DI->getDef()->isSubClassOf("RegisterClass")) {
593 std::string Value = getQualifiedName(DI->getDef()) + "RegClassID";
594 AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
595 ResultOps.push_back(NextRecordedOperandNo++);
600 errs() << "unhandled leaf node: \n";
604 /// GetInstPatternNode - Get the pattern for an instruction.
606 const TreePatternNode *MatcherGen::
607 GetInstPatternNode(const DAGInstruction &Inst, const TreePatternNode *N) {
608 const TreePattern *InstPat = Inst.getPattern();
610 // FIXME2?: Assume actual pattern comes before "implicit".
611 TreePatternNode *InstPatNode;
613 InstPatNode = InstPat->getTree(0);
614 else if (/*isRoot*/ N == Pattern.getDstPattern())
615 InstPatNode = Pattern.getSrcPattern();
619 if (InstPatNode && !InstPatNode->isLeaf() &&
620 InstPatNode->getOperator()->getName() == "set")
621 InstPatNode = InstPatNode->getChild(InstPatNode->getNumChildren()-1);
627 EmitResultInstructionAsOperand(const TreePatternNode *N,
628 SmallVectorImpl<unsigned> &OutputOps) {
629 Record *Op = N->getOperator();
630 const CodeGenTarget &CGT = CGP.getTargetInfo();
631 CodeGenInstruction &II = CGT.getInstruction(Op->getName());
632 const DAGInstruction &Inst = CGP.getInstruction(Op);
634 // If we can, get the pattern for the instruction we're generating. We derive
635 // a variety of information from this pattern, such as whether it has a chain.
637 // FIXME2: This is extremely dubious for several reasons, not the least of
638 // which it gives special status to instructions with patterns that Pat<>
639 // nodes can't duplicate.
640 const TreePatternNode *InstPatNode = GetInstPatternNode(Inst, N);
642 // NodeHasChain - Whether the instruction node we're creating takes chains.
643 bool NodeHasChain = InstPatNode &&
644 InstPatNode->TreeHasProperty(SDNPHasChain, CGP);
646 bool isRoot = N == Pattern.getDstPattern();
648 // TreeHasOutFlag - True if this tree has a flag.
649 bool TreeHasInFlag = false, TreeHasOutFlag = false;
651 const TreePatternNode *SrcPat = Pattern.getSrcPattern();
652 TreeHasInFlag = SrcPat->TreeHasProperty(SDNPOptInFlag, CGP) ||
653 SrcPat->TreeHasProperty(SDNPInFlag, CGP);
655 // FIXME2: this is checking the entire pattern, not just the node in
656 // question, doing this just for the root seems like a total hack.
657 TreeHasOutFlag = SrcPat->TreeHasProperty(SDNPOutFlag, CGP);
660 // NumResults - This is the number of results produced by the instruction in
662 unsigned NumResults = Inst.getNumResults();
664 // Loop over all of the operands of the instruction pattern, emitting code
665 // to fill them all in. The node 'N' usually has number children equal to
666 // the number of input operands of the instruction. However, in cases
667 // where there are predicate operands for an instruction, we need to fill
668 // in the 'execute always' values. Match up the node operands to the
669 // instruction operands to do this.
670 SmallVector<unsigned, 8> InstOps;
671 for (unsigned ChildNo = 0, InstOpNo = NumResults, e = II.OperandList.size();
672 InstOpNo != e; ++InstOpNo) {
674 // Determine what to emit for this operand.
675 Record *OperandNode = II.OperandList[InstOpNo].Rec;
676 if ((OperandNode->isSubClassOf("PredicateOperand") ||
677 OperandNode->isSubClassOf("OptionalDefOperand")) &&
678 !CGP.getDefaultOperand(OperandNode).DefaultOps.empty()) {
679 // This is a predicate or optional def operand; emit the
680 // 'default ops' operands.
681 const DAGDefaultOperand &DefaultOp =
682 CGP.getDefaultOperand(II.OperandList[InstOpNo].Rec);
683 for (unsigned i = 0, e = DefaultOp.DefaultOps.size(); i != e; ++i)
684 EmitResultOperand(DefaultOp.DefaultOps[i], InstOps);
688 // Otherwise this is a normal operand or a predicate operand without
689 // 'execute always'; emit it.
690 EmitResultOperand(N->getChild(ChildNo), InstOps);
694 // If this node has an input flag or explicitly specified input physregs, we
695 // need to add chained and flagged copyfromreg nodes and materialize the flag
697 if (isRoot && !PhysRegInputs.empty()) {
698 // Emit all of the CopyToReg nodes for the input physical registers. These
699 // occur in patterns like (mul:i8 AL:i8, GR8:i8:$src).
700 for (unsigned i = 0, e = PhysRegInputs.size(); i != e; ++i)
701 AddMatcher(new EmitCopyToRegMatcher(PhysRegInputs[i].second,
702 PhysRegInputs[i].first));
703 // Even if the node has no other flag inputs, the resultant node must be
704 // flagged to the CopyFromReg nodes we just generated.
705 TreeHasInFlag = true;
708 // Result order: node results, chain, flags
710 // Determine the result types.
711 SmallVector<MVT::SimpleValueType, 4> ResultVTs;
712 if (NumResults != 0 && N->getTypeNum(0) != MVT::isVoid) {
713 // FIXME2: If the node has multiple results, we should add them. For now,
714 // preserve existing behavior?!
715 ResultVTs.push_back(N->getTypeNum(0));
719 // If this is the root instruction of a pattern that has physical registers in
720 // its result pattern, add output VTs for them. For example, X86 has:
721 // (set AL, (mul ...))
722 // This also handles implicit results like:
724 if (isRoot && Pattern.getDstRegs().size() != 0) {
725 for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i)
726 if (Pattern.getDstRegs()[i]->isSubClassOf("Register"))
727 ResultVTs.push_back(getRegisterValueType(Pattern.getDstRegs()[i], CGT));
730 // FIXME2: Instead of using the isVariadic flag on the instruction, we should
731 // have an SDNP that indicates variadicism. The TargetInstrInfo isVariadic
732 // property should be inferred from this when an instruction has a pattern.
733 int NumFixedArityOperands = -1;
734 if (isRoot && II.isVariadic)
735 NumFixedArityOperands = Pattern.getSrcPattern()->getNumChildren();
737 // If this is the root node and any of the nodes matched nodes in the input
738 // pattern have MemRefs in them, have the interpreter collect them and plop
739 // them onto this node.
741 // FIXME3: This is actively incorrect for result patterns where the root of
742 // the pattern is not the memory reference and is also incorrect when the
743 // result pattern has multiple memory-referencing instructions. For example,
744 // in the X86 backend, this pattern causes the memrefs to get attached to the
745 // CVTSS2SDrr instead of the MOVSSrm:
747 // def : Pat<(extloadf32 addr:$src),
748 // (CVTSS2SDrr (MOVSSrm addr:$src))>;
750 bool NodeHasMemRefs =
751 isRoot && Pattern.getSrcPattern()->TreeHasProperty(SDNPMemOperand, CGP);
753 AddMatcher(new EmitNodeMatcher(II.Namespace+"::"+II.TheDef->getName(),
754 ResultVTs.data(), ResultVTs.size(),
755 InstOps.data(), InstOps.size(),
756 NodeHasChain, TreeHasInFlag, TreeHasOutFlag,
757 NodeHasMemRefs, NumFixedArityOperands,
758 NextRecordedOperandNo));
760 // The non-chain and non-flag results of the newly emitted node get recorded.
761 for (unsigned i = 0, e = ResultVTs.size(); i != e; ++i) {
762 if (ResultVTs[i] == MVT::Other || ResultVTs[i] == MVT::Flag) break;
763 OutputOps.push_back(NextRecordedOperandNo++);
768 EmitResultSDNodeXFormAsOperand(const TreePatternNode *N,
769 SmallVectorImpl<unsigned> &ResultOps) {
770 assert(N->getOperator()->isSubClassOf("SDNodeXForm") && "Not SDNodeXForm?");
773 SmallVector<unsigned, 8> InputOps;
775 // FIXME2: Could easily generalize this to support multiple inputs and outputs
776 // to the SDNodeXForm. For now we just support one input and one output like
777 // the old instruction selector.
778 assert(N->getNumChildren() == 1);
779 EmitResultOperand(N->getChild(0), InputOps);
781 // The input currently must have produced exactly one result.
782 assert(InputOps.size() == 1 && "Unexpected input to SDNodeXForm");
784 AddMatcher(new EmitNodeXFormMatcher(InputOps[0], N->getOperator()));
785 ResultOps.push_back(NextRecordedOperandNo++);
788 void MatcherGen::EmitResultOperand(const TreePatternNode *N,
789 SmallVectorImpl<unsigned> &ResultOps) {
790 // This is something selected from the pattern we matched.
791 if (!N->getName().empty())
792 return EmitResultOfNamedOperand(N, ResultOps);
795 return EmitResultLeafAsOperand(N, ResultOps);
797 Record *OpRec = N->getOperator();
798 if (OpRec->isSubClassOf("Instruction"))
799 return EmitResultInstructionAsOperand(N, ResultOps);
800 if (OpRec->isSubClassOf("SDNodeXForm"))
801 return EmitResultSDNodeXFormAsOperand(N, ResultOps);
802 errs() << "Unknown result node to emit code for: " << *N << '\n';
803 throw std::string("Unknown node in result pattern!");
806 void MatcherGen::EmitResultCode() {
807 // Patterns that match nodes with (potentially multiple) chain inputs have to
808 // merge them together into a token factor. This informs the generated code
809 // what all the chained nodes are.
810 if (!MatchedChainNodes.empty())
811 AddMatcher(new EmitMergeInputChainsMatcher
812 (MatchedChainNodes.data(), MatchedChainNodes.size()));
814 // Codegen the root of the result pattern, capturing the resulting values.
815 SmallVector<unsigned, 8> Ops;
816 EmitResultOperand(Pattern.getDstPattern(), Ops);
818 // At this point, we have however many values the result pattern produces.
819 // However, the input pattern might not need all of these. If there are
820 // excess values at the end (such as condition codes etc) just lop them off.
821 // This doesn't need to worry about flags or chains, just explicit results.
823 // FIXME2: This doesn't work because there is currently no way to get an
824 // accurate count of the # results the source pattern sets. This is because
825 // of the "parallel" construct in X86 land, which looks like this:
827 //def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
828 // (implicit EFLAGS)),
829 // (AND8rr GR8:$src1, GR8:$src2)>;
831 // This idiom means to match the two-result node X86and_flag (which is
832 // declared as returning a single result, because we can't match multi-result
833 // nodes yet). In this case, we would have to know that the input has two
834 // results. However, mul8r is modelled exactly the same way, but without
835 // implicit defs included. The fix is to support multiple results directly
836 // and eliminate 'parallel'.
838 // FIXME2: When this is fixed, we should revert the terrible hack in the
839 // OPC_EmitNode code in the interpreter.
841 const TreePatternNode *Src = Pattern.getSrcPattern();
842 unsigned NumSrcResults = Src->getTypeNum(0) != MVT::isVoid ? 1 : 0;
843 NumSrcResults += Pattern.getDstRegs().size();
844 assert(Ops.size() >= NumSrcResults && "Didn't provide enough results");
845 Ops.resize(NumSrcResults);
848 // If the matched pattern covers nodes which define a flag result, emit a node
849 // that tells the matcher about them so that it can update their results.
850 if (!MatchedFlagResultNodes.empty())
851 AddMatcher(new MarkFlagResultsMatcher(MatchedFlagResultNodes.data(),
852 MatchedFlagResultNodes.size()));
854 AddMatcher(new CompleteMatchMatcher(Ops.data(), Ops.size(), Pattern));
858 /// ConvertPatternToMatcher - Create the matcher for the specified pattern with
859 /// the specified variant. If the variant number is invalid, this returns null.
860 Matcher *llvm::ConvertPatternToMatcher(const PatternToMatch &Pattern,
862 const CodeGenDAGPatterns &CGP) {
863 MatcherGen Gen(Pattern, CGP);
865 // Generate the code for the matcher.
866 if (Gen.EmitMatcherCode(Variant))
869 // FIXME2: Kill extra MoveParent commands at the end of the matcher sequence.
870 // FIXME2: Split result code out to another table, and make the matcher end
871 // with an "Emit <index>" command. This allows result generation stuff to be
872 // shared and factored?
874 // If the match succeeds, then we generate Pattern.
875 Gen.EmitResultCode();
877 // Unconditional match.
878 return Gen.GetMatcher();