1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef CODEGEN_REGISTERS_H
16 #define CODEGEN_REGISTERS_H
19 #include "llvm/CodeGen/ValueTypes.h"
20 #include "llvm/ADT/ArrayRef.h"
21 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/SetVector.h"
32 /// CodeGenRegister - Represents a register definition.
33 struct CodeGenRegister {
38 // Map SubRegIndex -> Register.
39 typedef std::map<Record*, CodeGenRegister*, LessRecord> SubRegMap;
41 CodeGenRegister(Record *R, unsigned Enum);
43 const std::string &getName() const;
45 // Get a map of sub-registers computed lazily.
46 // This includes unique entries for all sub-sub-registers.
47 const SubRegMap &getSubRegs(CodeGenRegBank&);
49 const SubRegMap &getSubRegs() const {
50 assert(SubRegsComplete && "Must precompute sub-registers");
54 // Add sub-registers to OSet following a pre-order defined by the .td file.
55 void addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const;
57 // List of super-registers in topological order, small to large.
58 typedef std::vector<CodeGenRegister*> SuperRegList;
60 // Get the list of super-registers.
61 // This is only valid after computeDerivedInfo has visited all registers.
62 const SuperRegList &getSuperRegs() const {
63 assert(SubRegsComplete && "Must precompute sub-registers");
67 // Order CodeGenRegister pointers by EnumValue.
69 bool operator()(const CodeGenRegister *A,
70 const CodeGenRegister *B) const {
71 return A->EnumValue < B->EnumValue;
75 // Canonically ordered set.
76 typedef std::set<const CodeGenRegister*, Less> Set;
81 SuperRegList SuperRegs;
85 class CodeGenRegisterClass {
86 CodeGenRegister::Set Members;
87 std::vector<Record*> Elements;
90 std::string Namespace;
91 std::vector<MVT::SimpleValueType> VTs;
93 unsigned SpillAlignment;
96 // Map SubRegIndex -> RegisterClass
97 DenseMap<Record*,Record*> SubRegClasses;
98 std::string MethodProtos, MethodBodies;
100 const std::string &getName() const;
101 const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
102 unsigned getNumValueTypes() const { return VTs.size(); }
104 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
105 if (VTNum < VTs.size())
107 assert(0 && "VTNum greater than number of ValueTypes in RegClass!");
111 // Return true if this this class contains the register.
112 bool contains(const CodeGenRegister*) const;
114 // Returns true if RC is a subclass.
115 // RC is a sub-class of this class if it is a valid replacement for any
116 // instruction operand where a register of this classis required. It must
117 // satisfy these conditions:
119 // 1. All RC registers are also in this.
120 // 2. The RC spill size must not be smaller than our spill size.
121 // 3. RC spill alignment must be compatible with ours.
123 bool hasSubClass(const CodeGenRegisterClass *RC) const;
125 // Returns an ordered list of class members.
126 // The order of registers is the same as in the .td file.
127 ArrayRef<Record*> getOrder() const {
131 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
134 // CodeGenRegBank - Represent a target's registers and the relations between
136 class CodeGenRegBank {
137 RecordKeeper &Records;
138 std::vector<Record*> SubRegIndices;
139 unsigned NumNamedIndices;
140 std::vector<CodeGenRegister> Registers;
141 DenseMap<Record*, CodeGenRegister*> Def2Reg;
143 std::vector<CodeGenRegisterClass> RegClasses;
144 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
146 // Composite SubRegIndex instances.
147 // Map (SubRegIndex, SubRegIndex) -> SubRegIndex.
148 typedef DenseMap<std::pair<Record*, Record*>, Record*> CompositeMap;
149 CompositeMap Composite;
151 // Populate the Composite map from sub-register relationships.
152 void computeComposites();
155 CodeGenRegBank(RecordKeeper&);
157 // Sub-register indices. The first NumNamedIndices are defined by the user
158 // in the .td files. The rest are synthesized such that all sub-registers
159 // have a unique name.
160 const std::vector<Record*> &getSubRegIndices() { return SubRegIndices; }
161 unsigned getNumNamedIndices() { return NumNamedIndices; }
163 // Map a SubRegIndex Record to its enum value.
164 unsigned getSubRegIndexNo(Record *idx);
166 // Find or create a sub-register index representing the A+B composition.
167 Record *getCompositeSubRegIndex(Record *A, Record *B, bool create = false);
169 const std::vector<CodeGenRegister> &getRegisters() { return Registers; }
171 // Find a register from its Record def.
172 CodeGenRegister *getReg(Record*);
174 const std::vector<CodeGenRegisterClass> &getRegClasses() {
178 // Find a register class from its def.
179 CodeGenRegisterClass *getRegClass(Record*);
181 /// getRegisterClassForRegister - Find the register class that contains the
182 /// specified physical register. If the register is not in a register
183 /// class, return null. If the register is in multiple classes, and the
184 /// classes have a superset-subset relationship and the same set of types,
185 /// return the superclass. Otherwise return null.
186 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
188 // Computed derived records such as missing sub-register indices.
189 void computeDerivedInfo();
191 // Compute full overlap sets for every register. These sets include the
192 // rarely used aliases that are neither sub nor super-registers.
194 // Map[R1].count(R2) is reflexive and symmetric, but not transitive.
196 // If R1 is a sub-register of R2, Map[R1] is a subset of Map[R2].
197 void computeOverlaps(std::map<const CodeGenRegister*,
198 CodeGenRegister::Set> &Map);