1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef CODEGEN_REGISTERS_H
16 #define CODEGEN_REGISTERS_H
19 #include "SetTheory.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/SetVector.h"
33 /// CodeGenRegister - Represents a register definition.
34 struct CodeGenRegister {
39 // Map SubRegIndex -> Register.
40 typedef std::map<Record*, CodeGenRegister*, LessRecord> SubRegMap;
42 CodeGenRegister(Record *R, unsigned Enum);
44 const std::string &getName() const;
46 // Get a map of sub-registers computed lazily.
47 // This includes unique entries for all sub-sub-registers.
48 const SubRegMap &getSubRegs(CodeGenRegBank&);
50 const SubRegMap &getSubRegs() const {
51 assert(SubRegsComplete && "Must precompute sub-registers");
55 // Add sub-registers to OSet following a pre-order defined by the .td file.
56 void addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const;
58 // List of super-registers in topological order, small to large.
59 typedef std::vector<CodeGenRegister*> SuperRegList;
61 // Get the list of super-registers.
62 // This is only valid after computeDerivedInfo has visited all registers.
63 const SuperRegList &getSuperRegs() const {
64 assert(SubRegsComplete && "Must precompute sub-registers");
68 // Order CodeGenRegister pointers by EnumValue.
70 bool operator()(const CodeGenRegister *A,
71 const CodeGenRegister *B) const {
72 return A->EnumValue < B->EnumValue;
76 // Canonically ordered set.
77 typedef std::set<const CodeGenRegister*, Less> Set;
82 SuperRegList SuperRegs;
86 class CodeGenRegisterClass {
87 CodeGenRegister::Set Members;
88 const std::vector<Record*> *Elements;
89 std::vector<SmallVector<Record*, 16> > AltOrders;
93 std::string Namespace;
94 std::vector<MVT::SimpleValueType> VTs;
96 unsigned SpillAlignment;
99 // Map SubRegIndex -> RegisterClass
100 DenseMap<Record*,Record*> SubRegClasses;
101 std::string AltOrderSelect;
103 const std::string &getName() const;
104 const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
105 unsigned getNumValueTypes() const { return VTs.size(); }
107 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
108 if (VTNum < VTs.size())
110 assert(0 && "VTNum greater than number of ValueTypes in RegClass!");
114 // Return true if this this class contains the register.
115 bool contains(const CodeGenRegister*) const;
117 // Returns true if RC is a subclass.
118 // RC is a sub-class of this class if it is a valid replacement for any
119 // instruction operand where a register of this classis required. It must
120 // satisfy these conditions:
122 // 1. All RC registers are also in this.
123 // 2. The RC spill size must not be smaller than our spill size.
124 // 3. RC spill alignment must be compatible with ours.
126 bool hasSubClass(const CodeGenRegisterClass *RC) const;
128 // Returns an ordered list of class members.
129 // The order of registers is the same as in the .td file.
130 // No = 0 is the default allocation order, No = 1 is the first alternative.
131 ArrayRef<Record*> getOrder(unsigned No = 0) const {
135 return AltOrders[No - 1];
138 // Return the total number of allocation orders available.
139 unsigned getNumOrders() const { return 1 + AltOrders.size(); }
141 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
144 // CodeGenRegBank - Represent a target's registers and the relations between
146 class CodeGenRegBank {
147 RecordKeeper &Records;
150 std::vector<Record*> SubRegIndices;
151 unsigned NumNamedIndices;
152 std::vector<CodeGenRegister*> Registers;
153 DenseMap<Record*, CodeGenRegister*> Def2Reg;
155 std::vector<CodeGenRegisterClass*> RegClasses;
156 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
158 // Composite SubRegIndex instances.
159 // Map (SubRegIndex, SubRegIndex) -> SubRegIndex.
160 typedef DenseMap<std::pair<Record*, Record*>, Record*> CompositeMap;
161 CompositeMap Composite;
163 // Populate the Composite map from sub-register relationships.
164 void computeComposites();
167 CodeGenRegBank(RecordKeeper&);
169 SetTheory &getSets() { return Sets; }
171 // Sub-register indices. The first NumNamedIndices are defined by the user
172 // in the .td files. The rest are synthesized such that all sub-registers
173 // have a unique name.
174 const std::vector<Record*> &getSubRegIndices() { return SubRegIndices; }
175 unsigned getNumNamedIndices() { return NumNamedIndices; }
177 // Map a SubRegIndex Record to its enum value.
178 unsigned getSubRegIndexNo(Record *idx);
180 // Find or create a sub-register index representing the A+B composition.
181 Record *getCompositeSubRegIndex(Record *A, Record *B, bool create = false);
183 const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
185 // Find a register from its Record def.
186 CodeGenRegister *getReg(Record*);
188 ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
192 // Find a register class from its def.
193 CodeGenRegisterClass *getRegClass(Record*);
195 /// getRegisterClassForRegister - Find the register class that contains the
196 /// specified physical register. If the register is not in a register
197 /// class, return null. If the register is in multiple classes, and the
198 /// classes have a superset-subset relationship and the same set of types,
199 /// return the superclass. Otherwise return null.
200 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
202 // Computed derived records such as missing sub-register indices.
203 void computeDerivedInfo();
205 // Compute full overlap sets for every register. These sets include the
206 // rarely used aliases that are neither sub nor super-registers.
208 // Map[R1].count(R2) is reflexive and symmetric, but not transitive.
210 // If R1 is a sub-register of R2, Map[R1] is a subset of Map[R2].
211 void computeOverlaps(std::map<const CodeGenRegister*,
212 CodeGenRegister::Set> &Map);