1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef CODEGEN_REGISTERS_H
16 #define CODEGEN_REGISTERS_H
18 #include "SetTheory.h"
19 #include "llvm/TableGen/Record.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/Support/ErrorHandling.h"
35 /// CodeGenSubRegIndex - Represents a sub-register index.
36 class CodeGenSubRegIndex {
40 const unsigned EnumValue;
42 CodeGenSubRegIndex(Record *R, unsigned Enum);
44 const std::string &getName() const;
45 std::string getNamespace() const;
46 std::string getQualifiedName() const;
48 // Order CodeGenSubRegIndex pointers by EnumValue.
50 bool operator()(const CodeGenSubRegIndex *A,
51 const CodeGenSubRegIndex *B) const {
53 return A->EnumValue < B->EnumValue;
57 // Map of composite subreg indices.
58 typedef std::map<CodeGenSubRegIndex*, CodeGenSubRegIndex*, Less> CompMap;
60 // Returns the subreg index that results from composing this with Idx.
61 // Returns NULL if this and Idx don't compose.
62 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
63 CompMap::const_iterator I = Composed.find(Idx);
64 return I == Composed.end() ? 0 : I->second;
67 // Add a composite subreg index: this+A = B.
68 // Return a conflicting composite, or NULL
69 CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
70 CodeGenSubRegIndex *B) {
72 std::pair<CompMap::iterator, bool> Ins =
73 Composed.insert(std::make_pair(A, B));
74 return (Ins.second || Ins.first->second == B) ? 0 : Ins.first->second;
77 // Update the composite maps of components specified in 'ComposedOf'.
78 void updateComponents(CodeGenRegBank&);
80 // Clean out redundant composite mappings.
81 void cleanComposites();
83 // Return the map of composites.
84 const CompMap &getComposites() const { return Composed; }
90 /// CodeGenRegister - Represents a register definition.
91 struct CodeGenRegister {
95 bool CoveredBySubRegs;
97 // Map SubRegIndex -> Register.
98 typedef std::map<CodeGenSubRegIndex*, CodeGenRegister*,
99 CodeGenSubRegIndex::Less> SubRegMap;
101 CodeGenRegister(Record *R, unsigned Enum);
103 const std::string &getName() const;
105 // Extract more information from TheDef. This is used to build an object
106 // graph after all CodeGenRegister objects have been created.
107 void buildObjectGraph(CodeGenRegBank&);
109 // Lazily compute a map of all sub-registers.
110 // This includes unique entries for all sub-sub-registers.
111 const SubRegMap &computeSubRegs(CodeGenRegBank&);
113 // Compute extra sub-registers by combining the existing sub-registers.
114 void computeSecondarySubRegs(CodeGenRegBank&);
116 // Add this as a super-register to all sub-registers after the sub-register
117 // graph has been built.
118 void computeSuperRegs(CodeGenRegBank&);
120 const SubRegMap &getSubRegs() const {
121 assert(SubRegsComplete && "Must precompute sub-registers");
125 // Add sub-registers to OSet following a pre-order defined by the .td file.
126 void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
127 CodeGenRegBank&) const;
129 // Return the sub-register index naming Reg as a sub-register of this
130 // register. Returns NULL if Reg is not a sub-register.
131 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
132 return SubReg2Idx.lookup(Reg);
135 typedef std::vector<const CodeGenRegister*> SuperRegList;
137 // Get the list of super-registers in topological order, small to large.
138 // This is valid after computeSubRegs visits all registers during RegBank
140 const SuperRegList &getSuperRegs() const {
141 assert(SubRegsComplete && "Must precompute sub-registers");
145 // Get the list of ad hoc aliases. The graph is symmetric, so the list
146 // contains all registers in 'Aliases', and all registers that mention this
147 // register in 'Aliases'.
148 ArrayRef<CodeGenRegister*> getExplicitAliases() const {
149 return ExplicitAliases;
152 // Get the topological signature of this register. This is a small integer
153 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
154 // identical sub-register structure. That is, they support the same set of
155 // sub-register indices mapping to the same kind of sub-registers
157 unsigned getTopoSig() const {
158 assert(SuperRegsComplete && "TopoSigs haven't been computed yet.");
162 // List of register units in ascending order.
163 typedef SmallVector<unsigned, 16> RegUnitList;
165 // Get the list of register units.
166 // This is only valid after getSubRegs() completes.
167 const RegUnitList &getRegUnits() const { return RegUnits; }
169 // Inherit register units from subregisters.
170 // Return true if the RegUnits changed.
171 bool inheritRegUnits(CodeGenRegBank &RegBank);
173 // Adopt a register unit for pressure tracking.
174 // A unit is adopted iff its unit number is >= NumNativeRegUnits.
175 void adoptRegUnit(unsigned RUID) { RegUnits.push_back(RUID); }
177 // Get the sum of this register's register unit weights.
178 unsigned getWeight(const CodeGenRegBank &RegBank) const;
180 // Order CodeGenRegister pointers by EnumValue.
182 bool operator()(const CodeGenRegister *A,
183 const CodeGenRegister *B) const {
185 return A->EnumValue < B->EnumValue;
189 // Canonically ordered set.
190 typedef std::set<const CodeGenRegister*, Less> Set;
193 bool SubRegsComplete;
194 bool SuperRegsComplete;
197 // The sub-registers explicit in the .td file form a tree.
198 SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices;
199 SmallVector<CodeGenRegister*, 8> ExplicitSubRegs;
201 // Explicit ad hoc aliases, symmetrized to form an undirected graph.
202 SmallVector<CodeGenRegister*, 8> ExplicitAliases;
204 // Super-registers where this is the first explicit sub-register.
205 SuperRegList LeadingSuperRegs;
208 SuperRegList SuperRegs;
209 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
210 RegUnitList RegUnits;
214 class CodeGenRegisterClass {
215 CodeGenRegister::Set Members;
216 // Allocation orders. Order[0] always contains all registers in Members.
217 std::vector<SmallVector<Record*, 16> > Orders;
218 // Bit mask of sub-classes including this, indexed by their EnumValue.
219 BitVector SubClasses;
220 // List of super-classes, topologocally ordered to have the larger classes
221 // first. This is the same as sorting by EnumValue.
222 SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
226 // For a synthesized class, inherit missing properties from the nearest
228 void inheritProperties(CodeGenRegBank&);
230 // Map SubRegIndex -> sub-class. This is the largest sub-class where all
231 // registers have a SubRegIndex sub-register.
232 DenseMap<CodeGenSubRegIndex*, CodeGenRegisterClass*> SubClassWithSubReg;
234 // Map SubRegIndex -> set of super-reg classes. This is all register
235 // classes SuperRC such that:
237 // R:SubRegIndex in this RC for all R in SuperRC.
239 DenseMap<CodeGenSubRegIndex*,
240 SmallPtrSet<CodeGenRegisterClass*, 8> > SuperRegClasses;
242 // Bit vector of TopoSigs for the registers in this class. This will be
243 // very sparse on regular architectures.
248 std::string Namespace;
249 std::vector<MVT::SimpleValueType> VTs;
251 unsigned SpillAlignment;
254 std::string AltOrderSelect;
256 // Return the Record that defined this class, or NULL if the class was
257 // created by TableGen.
258 Record *getDef() const { return TheDef; }
260 const std::string &getName() const { return Name; }
261 std::string getQualifiedName() const;
262 const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
263 unsigned getNumValueTypes() const { return VTs.size(); }
265 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
266 if (VTNum < VTs.size())
268 llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
271 // Return true if this this class contains the register.
272 bool contains(const CodeGenRegister*) const;
274 // Returns true if RC is a subclass.
275 // RC is a sub-class of this class if it is a valid replacement for any
276 // instruction operand where a register of this classis required. It must
277 // satisfy these conditions:
279 // 1. All RC registers are also in this.
280 // 2. The RC spill size must not be smaller than our spill size.
281 // 3. RC spill alignment must be compatible with ours.
283 bool hasSubClass(const CodeGenRegisterClass *RC) const {
284 return SubClasses.test(RC->EnumValue);
287 // getSubClassWithSubReg - Returns the largest sub-class where all
288 // registers have a SubIdx sub-register.
289 CodeGenRegisterClass*
290 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const {
291 return SubClassWithSubReg.lookup(SubIdx);
294 void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx,
295 CodeGenRegisterClass *SubRC) {
296 SubClassWithSubReg[SubIdx] = SubRC;
299 // getSuperRegClasses - Returns a bit vector of all register classes
300 // containing only SubIdx super-registers of this class.
301 void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
303 // addSuperRegClass - Add a class containing only SudIdx super-registers.
304 void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
305 CodeGenRegisterClass *SuperRC) {
306 SuperRegClasses[SubIdx].insert(SuperRC);
309 // getSubClasses - Returns a constant BitVector of subclasses indexed by
311 // The SubClasses vector includs an entry for this class.
312 const BitVector &getSubClasses() const { return SubClasses; }
314 // getSuperClasses - Returns a list of super classes ordered by EnumValue.
315 // The array does not include an entry for this class.
316 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
320 // Returns an ordered list of class members.
321 // The order of registers is the same as in the .td file.
322 // No = 0 is the default allocation order, No = 1 is the first alternative.
323 ArrayRef<Record*> getOrder(unsigned No = 0) const {
327 // Return the total number of allocation orders available.
328 unsigned getNumOrders() const { return Orders.size(); }
330 // Get the set of registers. This set contains the same registers as
332 const CodeGenRegister::Set &getMembers() const { return Members; }
334 // Get a bit vector of TopoSigs present in this register class.
335 const BitVector &getTopoSigs() const { return TopoSigs; }
337 // Populate a unique sorted list of units from a register set.
338 void buildRegUnitSet(std::vector<unsigned> &RegUnits) const;
340 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
342 // A key representing the parts of a register class used for forming
343 // sub-classes. Note the ordering provided by this key is not the same as
344 // the topological order used for the EnumValues.
346 const CodeGenRegister::Set *Members;
348 unsigned SpillAlignment;
351 : Members(O.Members),
352 SpillSize(O.SpillSize),
353 SpillAlignment(O.SpillAlignment) {}
355 Key(const CodeGenRegister::Set *M, unsigned S = 0, unsigned A = 0)
356 : Members(M), SpillSize(S), SpillAlignment(A) {}
358 Key(const CodeGenRegisterClass &RC)
359 : Members(&RC.getMembers()),
360 SpillSize(RC.SpillSize),
361 SpillAlignment(RC.SpillAlignment) {}
363 // Lexicographical order of (Members, SpillSize, SpillAlignment).
364 bool operator<(const Key&) const;
367 // Create a non-user defined register class.
368 CodeGenRegisterClass(StringRef Name, Key Props);
370 // Called by CodeGenRegBank::CodeGenRegBank().
371 static void computeSubClasses(CodeGenRegBank&);
374 // Each RegUnitSet is a sorted vector with a name.
376 typedef std::vector<unsigned>::const_iterator iterator;
379 std::vector<unsigned> Units;
382 // Base vector for identifying TopoSigs. The contents uniquely identify a
383 // TopoSig, only computeSuperRegs needs to know how.
384 typedef SmallVector<unsigned, 16> TopoSigId;
386 // CodeGenRegBank - Represent a target's registers and the relations between
388 class CodeGenRegBank {
389 RecordKeeper &Records;
393 std::vector<CodeGenSubRegIndex*> SubRegIndices;
394 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
395 unsigned NumNamedIndices;
397 typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>,
398 CodeGenSubRegIndex*> ConcatIdxMap;
399 ConcatIdxMap ConcatIdx;
402 std::vector<CodeGenRegister*> Registers;
403 DenseMap<Record*, CodeGenRegister*> Def2Reg;
404 unsigned NumNativeRegUnits;
405 unsigned NumRegUnits; // # native + adopted register units.
407 std::map<TopoSigId, unsigned> TopoSigs;
409 // Map each register unit to a weight (for register pressure).
410 // Includes native and adopted register units.
411 std::vector<unsigned> RegUnitWeights;
414 std::vector<CodeGenRegisterClass*> RegClasses;
415 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
416 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
419 // Remember each unique set of register units. Initially, this contains a
420 // unique set for each register class. Simliar sets are coalesced with
421 // pruneUnitSets and new supersets are inferred during computeRegUnitSets.
422 std::vector<RegUnitSet> RegUnitSets;
424 // Map RegisterClass index to the index of the RegUnitSet that contains the
425 // class's units and any inferred RegUnit supersets.
426 std::vector<std::vector<unsigned> > RegClassUnitSets;
428 // Add RC to *2RC maps.
429 void addToMaps(CodeGenRegisterClass*);
431 // Create a synthetic sub-class if it is missing.
432 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
433 const CodeGenRegister::Set *Membs,
436 // Infer missing register classes.
437 void computeInferredRegisterClasses();
438 void inferCommonSubClass(CodeGenRegisterClass *RC);
439 void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
440 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
441 unsigned FirstSubRegRC = 0);
443 // Iteratively prune unit sets.
444 void pruneUnitSets();
446 // Compute a weight for each register unit created during getSubRegs.
447 void computeRegUnitWeights();
449 // Create a RegUnitSet for each RegClass and infer superclasses.
450 void computeRegUnitSets();
452 // Populate the Composite map from sub-register relationships.
453 void computeComposites();
456 CodeGenRegBank(RecordKeeper&);
458 SetTheory &getSets() { return Sets; }
460 // Sub-register indices. The first NumNamedIndices are defined by the user
461 // in the .td files. The rest are synthesized such that all sub-registers
462 // have a unique name.
463 ArrayRef<CodeGenSubRegIndex*> getSubRegIndices() { return SubRegIndices; }
464 unsigned getNumNamedIndices() { return NumNamedIndices; }
466 // Find a SubRegIndex form its Record def.
467 CodeGenSubRegIndex *getSubRegIdx(Record*);
469 // Find or create a sub-register index representing the A+B composition.
470 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
471 CodeGenSubRegIndex *B);
473 // Find or create a sub-register index representing the concatenation of
474 // non-overlapping sibling indices.
476 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8>&);
479 addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8> &Parts,
480 CodeGenSubRegIndex *Idx) {
481 ConcatIdx.insert(std::make_pair(Parts, Idx));
484 const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
486 // Find a register from its Record def.
487 CodeGenRegister *getReg(Record*);
489 // Get a Register's index into the Registers array.
490 unsigned getRegIndex(const CodeGenRegister *Reg) const {
491 return Reg->EnumValue - 1;
494 // Return the number of allocated TopoSigs. The first TopoSig representing
495 // leaf registers is allocated number 0.
496 unsigned getNumTopoSigs() const {
497 return TopoSigs.size();
500 // Find or create a TopoSig for the given TopoSigId.
501 // This function is only for use by CodeGenRegister::computeSuperRegs().
502 // Others should simply use Reg->getTopoSig().
503 unsigned getTopoSig(const TopoSigId &Id) {
504 return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
507 // Create a new non-native register unit that can be adopted by a register
508 // to increase its pressure. Note that NumNativeRegUnits is not increased.
509 unsigned newRegUnit(unsigned Weight) {
510 if (!RegUnitWeights.empty()) {
511 assert(Weight && "should only add allocatable units");
512 RegUnitWeights.resize(NumRegUnits+1);
513 RegUnitWeights[NumRegUnits] = Weight;
515 return NumRegUnits++;
518 // Native units are the singular unit of a leaf register. Register aliasing
519 // is completely characterized by native units. Adopted units exist to give
520 // register additional weight but don't affect aliasing.
521 bool isNativeUnit(unsigned RUID) {
522 return RUID < NumNativeRegUnits;
525 ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
529 // Find a register class from its def.
530 CodeGenRegisterClass *getRegClass(Record*);
532 /// getRegisterClassForRegister - Find the register class that contains the
533 /// specified physical register. If the register is not in a register
534 /// class, return null. If the register is in multiple classes, and the
535 /// classes have a superset-subset relationship and the same set of types,
536 /// return the superclass. Otherwise return null.
537 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
539 // Get a register unit's weight. Zero for unallocatable registers.
540 unsigned getRegUnitWeight(unsigned RUID) const {
541 return RegUnitWeights[RUID];
544 // Get the sum of unit weights.
545 unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
547 for (std::vector<unsigned>::const_iterator
548 I = Units.begin(), E = Units.end(); I != E; ++I)
549 Weight += getRegUnitWeight(*I);
553 // Increase a RegUnitWeight.
554 void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
555 RegUnitWeights[RUID] += Inc;
558 // Get the number of register pressure dimensions.
559 unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
561 // Get a set of register unit IDs for a given dimension of pressure.
562 RegUnitSet getRegPressureSet(unsigned Idx) const {
563 return RegUnitSets[Idx];
566 // Get a list of pressure set IDs for a register class. Liveness of a
567 // register in this class impacts each pressure set in this list by the
568 // weight of the register. An exact solution requires all registers in a
569 // class to have the same class, but it is not strictly guaranteed.
570 ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const {
571 return RegClassUnitSets[RCIdx];
574 // Computed derived records such as missing sub-register indices.
575 void computeDerivedInfo();
577 // Compute full overlap sets for every register. These sets include the
578 // rarely used aliases that are neither sub nor super-registers.
580 // Map[R1].count(R2) is reflexive and symmetric, but not transitive.
582 // If R1 is a sub-register of R2, Map[R1] is a subset of Map[R2].
583 void computeOverlaps(std::map<const CodeGenRegister*,
584 CodeGenRegister::Set> &Map);
586 // Compute the set of registers completely covered by the registers in Regs.
587 // The returned BitVector will have a bit set for each register in Regs,
588 // all sub-registers, and all super-registers that are covered by the
589 // registers in Regs.
591 // This is used to compute the mask of call-preserved registers from a list
593 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);