1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef CODEGEN_REGISTERS_H
16 #define CODEGEN_REGISTERS_H
19 #include "llvm/CodeGen/ValueTypes.h"
20 #include "llvm/ADT/DenseMap.h"
30 /// CodeGenRegister - Represents a register definition.
31 struct CodeGenRegister {
36 // Map SubRegIndex -> Register.
37 typedef std::map<Record*, CodeGenRegister*, LessRecord> SubRegMap;
39 CodeGenRegister(Record *R, unsigned Enum);
41 const std::string &getName() const;
43 // Get a map of sub-registers computed lazily.
44 // This includes unique entries for all sub-sub-registers.
45 const SubRegMap &getSubRegs(CodeGenRegBank&);
47 const SubRegMap &getSubRegs() const {
48 assert(SubRegsComplete && "Must precompute sub-registers");
58 struct CodeGenRegisterClass {
60 std::string Namespace;
61 std::vector<Record*> Elements;
62 std::vector<MVT::SimpleValueType> VTs;
64 unsigned SpillAlignment;
67 // Map SubRegIndex -> RegisterClass
68 DenseMap<Record*,Record*> SubRegClasses;
69 std::string MethodProtos, MethodBodies;
71 const std::string &getName() const;
72 const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
73 unsigned getNumValueTypes() const { return VTs.size(); }
75 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
76 if (VTNum < VTs.size())
78 assert(0 && "VTNum greater than number of ValueTypes in RegClass!");
82 bool containsRegister(Record *R) const {
83 for (unsigned i = 0, e = Elements.size(); i != e; ++i)
84 if (Elements[i] == R) return true;
88 // Returns true if RC is a strict subclass.
89 // RC is a sub-class of this class if it is a valid replacement for any
90 // instruction operand where a register of this classis required. It must
91 // satisfy these conditions:
93 // 1. All RC registers are also in this.
94 // 2. The RC spill size must not be smaller than our spill size.
95 // 3. RC spill alignment must be compatible with ours.
97 bool hasSubClass(const CodeGenRegisterClass *RC) const {
99 if (RC->Elements.size() > Elements.size() ||
100 (SpillAlignment && RC->SpillAlignment % SpillAlignment) ||
101 SpillSize > RC->SpillSize)
104 std::set<Record*> RegSet;
105 for (unsigned i = 0, e = Elements.size(); i != e; ++i) {
106 Record *Reg = Elements[i];
110 for (unsigned i = 0, e = RC->Elements.size(); i != e; ++i) {
111 Record *Reg = RC->Elements[i];
112 if (!RegSet.count(Reg))
119 CodeGenRegisterClass(Record *R);
122 // CodeGenRegBank - Represent a target's registers and the relations between
124 class CodeGenRegBank {
125 RecordKeeper &Records;
126 std::vector<Record*> SubRegIndices;
127 unsigned NumNamedIndices;
128 std::vector<CodeGenRegister> Registers;
129 DenseMap<Record*, CodeGenRegister*> Def2Reg;
131 // Composite SubRegIndex instances.
132 // Map (SubRegIndex, SubRegIndex) -> SubRegIndex.
133 typedef DenseMap<std::pair<Record*, Record*>, Record*> CompositeMap;
134 CompositeMap Composite;
136 // Populate the Composite map from sub-register relationships.
137 void computeComposites();
140 CodeGenRegBank(RecordKeeper&);
142 // Sub-register indices. The first NumNamedIndices are defined by the user
143 // in the .td files. The rest are synthesized such that all sub-registers
144 // have a unique name.
145 const std::vector<Record*> &getSubRegIndices() { return SubRegIndices; }
146 unsigned getNumNamedIndices() { return NumNamedIndices; }
148 // Map a SubRegIndex Record to its enum value.
149 unsigned getSubRegIndexNo(Record *idx);
151 // Find or create a sub-register index representing the A+B composition.
152 Record *getCompositeSubRegIndex(Record *A, Record *B, bool create = false);
154 const std::vector<CodeGenRegister> &getRegisters() { return Registers; }
156 // Find a register from its Record def.
157 CodeGenRegister *getReg(Record*);
159 // Computed derived records such as missing sub-register indices.
160 void computeDerivedInfo();