1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #include "CodeGenRegisters.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/TableGen/Error.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/StringExtras.h"
24 //===----------------------------------------------------------------------===//
26 //===----------------------------------------------------------------------===//
28 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
31 CostPerUse(R->getValueAsInt("CostPerUse")),
32 SubRegsComplete(false)
35 const std::string &CodeGenRegister::getName() const {
36 return TheDef->getName();
41 CodeGenRegister *SubReg;
42 Record *First, *Second;
43 Orphan(CodeGenRegister *r, Record *a, Record *b)
44 : SubReg(r), First(a), Second(b) {}
48 const CodeGenRegister::SubRegMap &
49 CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
50 // Only compute this map once.
53 SubRegsComplete = true;
55 std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs");
56 std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
57 if (SubList.size() != Indices.size())
58 throw TGError(TheDef->getLoc(), "Register " + getName() +
59 " SubRegIndices doesn't match SubRegs");
61 // First insert the direct subregs and make sure they are fully indexed.
62 for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
63 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
64 if (!SubRegs.insert(std::make_pair(Indices[i], SR)).second)
65 throw TGError(TheDef->getLoc(), "SubRegIndex " + Indices[i]->getName() +
66 " appears twice in Register " + getName());
69 // Keep track of inherited subregs and how they can be reached.
70 SmallVector<Orphan, 8> Orphans;
72 // Clone inherited subregs and place duplicate entries on Orphans.
73 // Here the order is important - earlier subregs take precedence.
74 for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
75 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
76 const SubRegMap &Map = SR->getSubRegs(RegBank);
78 // Add this as a super-register of SR now all sub-registers are in the list.
79 // This creates a topological ordering, the exact order depends on the
80 // order getSubRegs is called on all registers.
81 SR->SuperRegs.push_back(this);
83 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
85 if (!SubRegs.insert(*SI).second)
86 Orphans.push_back(Orphan(SI->second, Indices[i], SI->first));
88 // Noop sub-register indexes are possible, so avoid duplicates.
90 SI->second->SuperRegs.push_back(this);
94 // Process the composites.
95 ListInit *Comps = TheDef->getValueAsListInit("CompositeIndices");
96 for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
97 DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
99 throw TGError(TheDef->getLoc(), "Invalid dag '" +
100 Comps->getElement(i)->getAsString() +
101 "' in CompositeIndices");
102 DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
103 if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
104 throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
107 // Resolve list of subreg indices into R2.
108 CodeGenRegister *R2 = this;
109 for (DagInit::const_arg_iterator di = Pat->arg_begin(),
110 de = Pat->arg_end(); di != de; ++di) {
111 DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
112 if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
113 throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
115 const SubRegMap &R2Subs = R2->getSubRegs(RegBank);
116 SubRegMap::const_iterator ni = R2Subs.find(IdxInit->getDef());
117 if (ni == R2Subs.end())
118 throw TGError(TheDef->getLoc(), "Composite " + Pat->getAsString() +
119 " refers to bad index in " + R2->getName());
123 // Insert composite index. Allow overriding inherited indices etc.
124 SubRegs[BaseIdxInit->getDef()] = R2;
126 // R2 is no longer an orphan.
127 for (unsigned j = 0, je = Orphans.size(); j != je; ++j)
128 if (Orphans[j].SubReg == R2)
129 Orphans[j].SubReg = 0;
132 // Now Orphans contains the inherited subregisters without a direct index.
133 // Create inferred indexes for all missing entries.
134 for (unsigned i = 0, e = Orphans.size(); i != e; ++i) {
135 Orphan &O = Orphans[i];
138 SubRegs[RegBank.getCompositeSubRegIndex(O.First, O.Second, true)] =
145 CodeGenRegister::addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const {
146 assert(SubRegsComplete && "Must precompute sub-registers");
147 std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
148 for (unsigned i = 0, e = Indices.size(); i != e; ++i) {
149 CodeGenRegister *SR = SubRegs.find(Indices[i])->second;
151 SR->addSubRegsPreOrder(OSet);
155 //===----------------------------------------------------------------------===//
157 //===----------------------------------------------------------------------===//
159 // A RegisterTuples def is used to generate pseudo-registers from lists of
160 // sub-registers. We provide a SetTheory expander class that returns the new
163 struct TupleExpander : SetTheory::Expander {
164 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) {
165 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
166 unsigned Dim = Indices.size();
167 ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
168 if (Dim != SubRegs->getSize())
169 throw TGError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
171 throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-registers");
173 // Evaluate the sub-register lists to be zipped.
174 unsigned Length = ~0u;
175 SmallVector<SetTheory::RecSet, 4> Lists(Dim);
176 for (unsigned i = 0; i != Dim; ++i) {
177 ST.evaluate(SubRegs->getElement(i), Lists[i]);
178 Length = std::min(Length, unsigned(Lists[i].size()));
184 // Precompute some types.
185 Record *RegisterCl = Def->getRecords().getClass("Register");
186 RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl);
187 StringInit *BlankName = StringInit::get("");
190 for (unsigned n = 0; n != Length; ++n) {
192 Record *Proto = Lists[0][n];
193 std::vector<Init*> Tuple;
194 unsigned CostPerUse = 0;
195 for (unsigned i = 0; i != Dim; ++i) {
196 Record *Reg = Lists[i][n];
198 Name += Reg->getName();
199 Tuple.push_back(DefInit::get(Reg));
200 CostPerUse = std::max(CostPerUse,
201 unsigned(Reg->getValueAsInt("CostPerUse")));
204 // Create a new Record representing the synthesized register. This record
205 // is only for consumption by CodeGenRegister, it is not added to the
207 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
210 // Copy Proto super-classes.
211 for (unsigned i = 0, e = Proto->getSuperClasses().size(); i != e; ++i)
212 NewReg->addSuperClass(Proto->getSuperClasses()[i]);
214 // Copy Proto fields.
215 for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
216 RecordVal RV = Proto->getValues()[i];
218 // Replace the sub-register list with Tuple.
219 if (RV.getName() == "SubRegs")
220 RV.setValue(ListInit::get(Tuple, RegisterRecTy));
222 // Provide a blank AsmName. MC hacks are required anyway.
223 if (RV.getName() == "AsmName")
224 RV.setValue(BlankName);
226 // CostPerUse is aggregated from all Tuple members.
227 if (RV.getName() == "CostPerUse")
228 RV.setValue(IntInit::get(CostPerUse));
230 // Copy fields from the RegisterTuples def.
231 if (RV.getName() == "SubRegIndices" ||
232 RV.getName() == "CompositeIndices") {
233 NewReg->addValue(*Def->getValue(RV.getName()));
237 // Some fields get their default uninitialized value.
238 if (RV.getName() == "DwarfNumbers" ||
239 RV.getName() == "DwarfAlias" ||
240 RV.getName() == "Aliases") {
241 if (const RecordVal *DefRV = RegisterCl->getValue(RV.getName()))
242 NewReg->addValue(*DefRV);
246 // Everything else is copied from Proto.
247 NewReg->addValue(RV);
254 //===----------------------------------------------------------------------===//
255 // CodeGenRegisterClass
256 //===----------------------------------------------------------------------===//
258 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
259 : TheDef(R), EnumValue(-1) {
260 // Rename anonymous register classes.
261 if (R->getName().size() > 9 && R->getName()[9] == '.') {
262 static unsigned AnonCounter = 0;
263 R->setName("AnonRegClass_"+utostr(AnonCounter++));
266 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
267 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
268 Record *Type = TypeList[i];
269 if (!Type->isSubClassOf("ValueType"))
270 throw "RegTypes list member '" + Type->getName() +
271 "' does not derive from the ValueType class!";
272 VTs.push_back(getValueType(Type));
274 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
276 // Default allocation order always contains all registers.
277 Elements = RegBank.getSets().expand(R);
278 for (unsigned i = 0, e = Elements->size(); i != e; ++i)
279 Members.insert(RegBank.getReg((*Elements)[i]));
281 // Alternative allocation orders may be subsets.
282 ListInit *Alts = R->getValueAsListInit("AltOrders");
283 AltOrders.resize(Alts->size());
284 SetTheory::RecSet Order;
285 for (unsigned i = 0, e = Alts->size(); i != e; ++i) {
286 RegBank.getSets().evaluate(Alts->getElement(i), Order);
287 AltOrders[i].append(Order.begin(), Order.end());
288 // Verify that all altorder members are regclass members.
289 while (!Order.empty()) {
290 CodeGenRegister *Reg = RegBank.getReg(Order.back());
293 throw TGError(R->getLoc(), " AltOrder register " + Reg->getName() +
294 " is not a class member");
298 // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
299 ListInit *SRC = R->getValueAsListInit("SubRegClasses");
300 for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
301 DagInit *DAG = dynamic_cast<DagInit*>(*i);
302 if (!DAG) throw "SubRegClasses must contain DAGs";
303 DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator());
305 if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
306 throw "Operator '" + DAG->getOperator()->getAsString() +
307 "' in SubRegClasses is not a RegisterClass";
308 // Iterate over args, all SubRegIndex instances.
309 for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
311 DefInit *Idx = dynamic_cast<DefInit*>(*ai);
313 if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
314 throw "Argument '" + (*ai)->getAsString() +
315 "' in SubRegClasses is not a SubRegIndex";
316 if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second)
317 throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice";
321 // Allow targets to override the size in bits of the RegisterClass.
322 unsigned Size = R->getValueAsInt("Size");
324 Namespace = R->getValueAsString("Namespace");
325 SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
326 SpillAlignment = R->getValueAsInt("Alignment");
327 CopyCost = R->getValueAsInt("CopyCost");
328 Allocatable = R->getValueAsBit("isAllocatable");
329 AltOrderSelect = R->getValueAsCode("AltOrderSelect");
332 bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
333 return Members.count(Reg);
336 // Returns true if RC is a strict subclass.
337 // RC is a sub-class of this class if it is a valid replacement for any
338 // instruction operand where a register of this classis required. It must
339 // satisfy these conditions:
341 // 1. All RC registers are also in this.
342 // 2. The RC spill size must not be smaller than our spill size.
343 // 3. RC spill alignment must be compatible with ours.
345 static bool testSubClass(const CodeGenRegisterClass *A,
346 const CodeGenRegisterClass *B) {
347 return A->SpillAlignment && B->SpillAlignment % A->SpillAlignment == 0 &&
348 A->SpillSize <= B->SpillSize &&
349 std::includes(A->getMembers().begin(), A->getMembers().end(),
350 B->getMembers().begin(), B->getMembers().end(),
351 CodeGenRegister::Less());
354 /// Sorting predicate for register classes. This provides a topological
355 /// ordering that arranges all register classes before their sub-classes.
357 /// Register classes with the same registers, spill size, and alignment form a
358 /// clique. They will be ordered alphabetically.
360 static int TopoOrderRC(const void *PA, const void *PB) {
361 const CodeGenRegisterClass *A = *(const CodeGenRegisterClass* const*)PA;
362 const CodeGenRegisterClass *B = *(const CodeGenRegisterClass* const*)PB;
366 // Order by descending set size.
367 if (A->getOrder().size() > B->getOrder().size())
369 if (A->getOrder().size() < B->getOrder().size())
372 // Order by ascending spill size.
373 if (A->SpillSize < B->SpillSize)
375 if (A->SpillSize > B->SpillSize)
378 // Order by ascending spill alignment.
379 if (A->SpillAlignment < B->SpillAlignment)
381 if (A->SpillAlignment > B->SpillAlignment)
384 // Finally order by name as a tie breaker.
385 return A->getName() < B->getName();
388 const std::string &CodeGenRegisterClass::getName() const {
389 return TheDef->getName();
392 // Compute sub-classes of all register classes.
393 // Assume the classes are ordered topologically.
394 void CodeGenRegisterClass::
395 computeSubClasses(ArrayRef<CodeGenRegisterClass*> RegClasses) {
396 // Visit backwards so sub-classes are seen first.
397 for (unsigned rci = RegClasses.size(); rci; --rci) {
398 CodeGenRegisterClass &RC = *RegClasses[rci - 1];
399 RC.SubClasses.resize(RegClasses.size());
400 RC.SubClasses.set(RC.EnumValue);
402 // Normally, all subclasses have IDs >= rci, unless RC is part of a clique.
403 for (unsigned s = rci; s != RegClasses.size(); ++s) {
404 if (RC.SubClasses.test(s))
406 CodeGenRegisterClass *SubRC = RegClasses[s];
407 if (!testSubClass(&RC, SubRC))
409 // SubRC is a sub-class. Grap all its sub-classes so we won't have to
411 RC.SubClasses |= SubRC->SubClasses;
414 // Sweep up missed clique members. They will be immediately preceeding RC.
415 for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s)
416 RC.SubClasses.set(s - 1);
419 // Compute the SuperClasses lists from the SubClasses vectors.
420 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {
421 const BitVector &SC = RegClasses[rci]->getSubClasses();
422 for (int s = SC.find_first(); s >= 0; s = SC.find_next(s)) {
423 if (unsigned(s) == rci)
425 RegClasses[s]->SuperClasses.push_back(RegClasses[rci]);
430 //===----------------------------------------------------------------------===//
432 //===----------------------------------------------------------------------===//
434 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
435 // Configure register Sets to understand register classes and tuples.
436 Sets.addFieldExpander("RegisterClass", "MemberList");
437 Sets.addExpander("RegisterTuples", new TupleExpander());
439 // Read in the user-defined (named) sub-register indices.
440 // More indices will be synthesized later.
441 SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex");
442 std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord());
443 NumNamedIndices = SubRegIndices.size();
445 // Read in the register definitions.
446 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
447 std::sort(Regs.begin(), Regs.end(), LessRecord());
448 Registers.reserve(Regs.size());
449 // Assign the enumeration values.
450 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
453 // Expand tuples and number the new registers.
454 std::vector<Record*> Tups =
455 Records.getAllDerivedDefinitions("RegisterTuples");
456 for (unsigned i = 0, e = Tups.size(); i != e; ++i) {
457 const std::vector<Record*> *TupRegs = Sets.expand(Tups[i]);
458 for (unsigned j = 0, je = TupRegs->size(); j != je; ++j)
459 getReg((*TupRegs)[j]);
462 // Read in register class definitions.
463 std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
465 throw std::string("No 'RegisterClass' subclasses defined!");
467 RegClasses.reserve(RCs.size());
468 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
469 CodeGenRegisterClass *RC = new CodeGenRegisterClass(*this, RCs[i]);
470 RegClasses.push_back(RC);
473 // Order register classes topologically and assign enum values.
474 array_pod_sort(RegClasses.begin(), RegClasses.end(), TopoOrderRC);
475 for (unsigned i = 0, e = RegClasses.size(); i != e; ++i)
476 RegClasses[i]->EnumValue = i;
477 CodeGenRegisterClass::computeSubClasses(RegClasses);
480 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
481 CodeGenRegister *&Reg = Def2Reg[Def];
484 Reg = new CodeGenRegister(Def, Registers.size() + 1);
485 Registers.push_back(Reg);
489 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
490 if (CodeGenRegisterClass *RC = Def2RC[Def])
493 throw TGError(Def->getLoc(), "Not a known RegisterClass!");
496 Record *CodeGenRegBank::getCompositeSubRegIndex(Record *A, Record *B,
498 // Look for an existing entry.
499 Record *&Comp = Composite[std::make_pair(A, B)];
503 // None exists, synthesize one.
504 std::string Name = A->getName() + "_then_" + B->getName();
505 Comp = new Record(Name, SMLoc(), Records);
506 SubRegIndices.push_back(Comp);
510 unsigned CodeGenRegBank::getSubRegIndexNo(Record *idx) {
511 std::vector<Record*>::const_iterator i =
512 std::find(SubRegIndices.begin(), SubRegIndices.end(), idx);
513 assert(i != SubRegIndices.end() && "Not a SubRegIndex");
514 return (i - SubRegIndices.begin()) + 1;
517 void CodeGenRegBank::computeComposites() {
518 // Precompute all sub-register maps. This will create Composite entries for
519 // all inferred sub-register indices.
520 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
521 Registers[i]->getSubRegs(*this);
523 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
524 CodeGenRegister *Reg1 = Registers[i];
525 const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs();
526 for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
527 e1 = SRM1.end(); i1 != e1; ++i1) {
528 Record *Idx1 = i1->first;
529 CodeGenRegister *Reg2 = i1->second;
530 // Ignore identity compositions.
533 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
534 // Try composing Idx1 with another SubRegIndex.
535 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
536 e2 = SRM2.end(); i2 != e2; ++i2) {
537 std::pair<Record*, Record*> IdxPair(Idx1, i2->first);
538 CodeGenRegister *Reg3 = i2->second;
539 // Ignore identity compositions.
542 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
543 for (CodeGenRegister::SubRegMap::const_iterator i1d = SRM1.begin(),
544 e1d = SRM1.end(); i1d != e1d; ++i1d) {
545 if (i1d->second == Reg3) {
546 std::pair<CompositeMap::iterator, bool> Ins =
547 Composite.insert(std::make_pair(IdxPair, i1d->first));
548 // Conflicting composition? Emit a warning but allow it.
549 if (!Ins.second && Ins.first->second != i1d->first) {
550 errs() << "Warning: SubRegIndex " << getQualifiedName(Idx1)
551 << " and " << getQualifiedName(IdxPair.second)
552 << " compose ambiguously as "
553 << getQualifiedName(Ins.first->second) << " or "
554 << getQualifiedName(i1d->first) << "\n";
562 // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
563 // compositions, so remove any mappings of that form.
564 for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
566 CompositeMap::iterator j = i;
568 if (j->first.second == j->second)
573 // Compute sets of overlapping registers.
575 // The standard set is all super-registers and all sub-registers, but the
576 // target description can add arbitrary overlapping registers via the 'Aliases'
577 // field. This complicates things, but we can compute overlapping sets using
578 // the following rules:
580 // 1. The relation overlap(A, B) is reflexive and symmetric but not transitive.
582 // 2. overlap(A, B) implies overlap(A, S) for all S in supers(B).
586 // overlap(A, B) iff there exists:
587 // A' in { A, subregs(A) } and B' in { B, subregs(B) } such that:
588 // A' = B' or A' in aliases(B') or B' in aliases(A').
590 // Here subregs(A) is the full flattened sub-register set returned by
591 // A.getSubRegs() while aliases(A) is simply the special 'Aliases' field in the
592 // description of register A.
594 // This also implies that registers with a common sub-register are considered
595 // overlapping. This can happen when forming register pairs:
601 // In this case, we will infer an overlap between P0 and P1 because of the
602 // shared sub-register R1. There is no overlap between P0 and P2.
604 void CodeGenRegBank::
605 computeOverlaps(std::map<const CodeGenRegister*, CodeGenRegister::Set> &Map) {
608 // Collect overlaps that don't follow from rule 2.
609 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
610 CodeGenRegister *Reg = Registers[i];
611 CodeGenRegister::Set &Overlaps = Map[Reg];
613 // Reg overlaps itself.
614 Overlaps.insert(Reg);
616 // All super-registers overlap.
617 const CodeGenRegister::SuperRegList &Supers = Reg->getSuperRegs();
618 Overlaps.insert(Supers.begin(), Supers.end());
620 // Form symmetrical relations from the special Aliases[] lists.
621 std::vector<Record*> RegList = Reg->TheDef->getValueAsListOfDefs("Aliases");
622 for (unsigned i2 = 0, e2 = RegList.size(); i2 != e2; ++i2) {
623 CodeGenRegister *Reg2 = getReg(RegList[i2]);
624 CodeGenRegister::Set &Overlaps2 = Map[Reg2];
625 const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs();
626 // Reg overlaps Reg2 which implies it overlaps supers(Reg2).
627 Overlaps.insert(Reg2);
628 Overlaps.insert(Supers2.begin(), Supers2.end());
629 Overlaps2.insert(Reg);
630 Overlaps2.insert(Supers.begin(), Supers.end());
634 // Apply rule 2. and inherit all sub-register overlaps.
635 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
636 CodeGenRegister *Reg = Registers[i];
637 CodeGenRegister::Set &Overlaps = Map[Reg];
638 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
639 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM.begin(),
640 e2 = SRM.end(); i2 != e2; ++i2) {
641 CodeGenRegister::Set &Overlaps2 = Map[i2->second];
642 Overlaps.insert(Overlaps2.begin(), Overlaps2.end());
647 void CodeGenRegBank::computeDerivedInfo() {
651 /// getRegisterClassForRegister - Find the register class that contains the
652 /// specified physical register. If the register is not in a register class,
653 /// return null. If the register is in multiple classes, and the classes have a
654 /// superset-subset relationship and the same set of types, return the
655 /// superclass. Otherwise return null.
656 const CodeGenRegisterClass*
657 CodeGenRegBank::getRegClassForRegister(Record *R) {
658 const CodeGenRegister *Reg = getReg(R);
659 ArrayRef<CodeGenRegisterClass*> RCs = getRegClasses();
660 const CodeGenRegisterClass *FoundRC = 0;
661 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
662 const CodeGenRegisterClass &RC = *RCs[i];
663 if (!RC.contains(Reg))
666 // If this is the first class that contains the register,
667 // make a note of it and go on to the next class.
673 // If a register's classes have different types, return null.
674 if (RC.getValueTypes() != FoundRC->getValueTypes())
677 // Check to see if the previously found class that contains
678 // the register is a subclass of the current class. If so,
679 // prefer the superclass.
680 if (RC.hasSubClass(FoundRC)) {
685 // Check to see if the previously found class that contains
686 // the register is a superclass of the current class. If so,
687 // prefer the superclass.
688 if (FoundRC->hasSubClass(&RC))
691 // Multiple classes, and neither is a superclass of the other.