1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is emits an assembly printer for the current target.
11 // Note that this is currently fairly skeletal, but will grow over time.
13 //===----------------------------------------------------------------------===//
15 #include "AsmWriterInst.h"
16 #include "CodeGenTarget.h"
17 #include "SequenceToOffsetTable.h"
18 #include "llvm/ADT/SmallString.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/Format.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
33 #define DEBUG_TYPE "asm-writer-emitter"
36 class AsmWriterEmitter {
37 RecordKeeper &Records;
39 std::map<const CodeGenInstruction*, AsmWriterInst*> CGIAWIMap;
40 const std::vector<const CodeGenInstruction*> *NumberedInstructions;
41 std::vector<AsmWriterInst> Instructions;
42 std::vector<std::string> PrintMethods;
44 AsmWriterEmitter(RecordKeeper &R);
46 void run(raw_ostream &o);
49 void EmitPrintInstruction(raw_ostream &o);
50 void EmitGetRegisterName(raw_ostream &o);
51 void EmitPrintAliasInstruction(raw_ostream &O);
53 AsmWriterInst *getAsmWriterInstByID(unsigned ID) const {
54 assert(ID < NumberedInstructions->size());
55 std::map<const CodeGenInstruction*, AsmWriterInst*>::const_iterator I =
56 CGIAWIMap.find(NumberedInstructions->at(ID));
57 assert(I != CGIAWIMap.end() && "Didn't find inst!");
60 void FindUniqueOperandCommands(std::vector<std::string> &UOC,
61 std::vector<unsigned> &InstIdxs,
62 std::vector<unsigned> &InstOpsUsed) const;
64 } // end anonymous namespace
66 static void PrintCases(std::vector<std::pair<std::string,
67 AsmWriterOperand> > &OpsToPrint, raw_ostream &O) {
68 O << " case " << OpsToPrint.back().first << ": ";
69 AsmWriterOperand TheOp = OpsToPrint.back().second;
70 OpsToPrint.pop_back();
72 // Check to see if any other operands are identical in this list, and if so,
73 // emit a case label for them.
74 for (unsigned i = OpsToPrint.size(); i != 0; --i)
75 if (OpsToPrint[i-1].second == TheOp) {
76 O << "\n case " << OpsToPrint[i-1].first << ": ";
77 OpsToPrint.erase(OpsToPrint.begin()+i-1);
80 // Finally, emit the code.
86 /// EmitInstructions - Emit the last instruction in the vector and any other
87 /// instructions that are suitably similar to it.
88 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
90 AsmWriterInst FirstInst = Insts.back();
93 std::vector<AsmWriterInst> SimilarInsts;
94 unsigned DifferingOperand = ~0;
95 for (unsigned i = Insts.size(); i != 0; --i) {
96 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
98 if (DifferingOperand == ~0U) // First match!
99 DifferingOperand = DiffOp;
101 // If this differs in the same operand as the rest of the instructions in
102 // this class, move it to the SimilarInsts list.
103 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
104 SimilarInsts.push_back(Insts[i-1]);
105 Insts.erase(Insts.begin()+i-1);
110 O << " case " << FirstInst.CGI->Namespace << "::"
111 << FirstInst.CGI->TheDef->getName() << ":\n";
112 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
113 O << " case " << SimilarInsts[i].CGI->Namespace << "::"
114 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
115 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
116 if (i != DifferingOperand) {
117 // If the operand is the same for all instructions, just print it.
118 O << " " << FirstInst.Operands[i].getCode();
120 // If this is the operand that varies between all of the instructions,
121 // emit a switch for just this operand now.
122 O << " switch (MI->getOpcode()) {\n";
123 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
124 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
125 FirstInst.CGI->TheDef->getName(),
126 FirstInst.Operands[i]));
128 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
129 AsmWriterInst &AWI = SimilarInsts[si];
130 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
131 AWI.CGI->TheDef->getName(),
134 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
135 while (!OpsToPrint.empty())
136 PrintCases(OpsToPrint, O);
144 void AsmWriterEmitter::
145 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
146 std::vector<unsigned> &InstIdxs,
147 std::vector<unsigned> &InstOpsUsed) const {
148 InstIdxs.assign(NumberedInstructions->size(), ~0U);
150 // This vector parallels UniqueOperandCommands, keeping track of which
151 // instructions each case are used for. It is a comma separated string of
153 std::vector<std::string> InstrsForCase;
154 InstrsForCase.resize(UniqueOperandCommands.size());
155 InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
157 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
158 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
160 continue; // PHI, INLINEASM, CFI_INSTRUCTION, etc.
163 if (Inst->Operands.empty())
164 continue; // Instruction already done.
166 Command = " " + Inst->Operands[0].getCode() + "\n";
168 // Check to see if we already have 'Command' in UniqueOperandCommands.
170 bool FoundIt = false;
171 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
172 if (UniqueOperandCommands[idx] == Command) {
174 InstrsForCase[idx] += ", ";
175 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
180 InstIdxs[i] = UniqueOperandCommands.size();
181 UniqueOperandCommands.push_back(Command);
182 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
184 // This command matches one operand so far.
185 InstOpsUsed.push_back(1);
189 // For each entry of UniqueOperandCommands, there is a set of instructions
190 // that uses it. If the next command of all instructions in the set are
191 // identical, fold it into the command.
192 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
193 CommandIdx != e; ++CommandIdx) {
195 for (unsigned Op = 1; ; ++Op) {
196 // Scan for the first instruction in the set.
197 std::vector<unsigned>::iterator NIT =
198 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
199 if (NIT == InstIdxs.end()) break; // No commonality.
201 // If this instruction has no more operands, we isn't anything to merge
202 // into this command.
203 const AsmWriterInst *FirstInst =
204 getAsmWriterInstByID(NIT-InstIdxs.begin());
205 if (!FirstInst || FirstInst->Operands.size() == Op)
208 // Otherwise, scan to see if all of the other instructions in this command
209 // set share the operand.
212 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
213 NIT != InstIdxs.end();
214 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
215 // Okay, found another instruction in this command set. If the operand
216 // matches, we're ok, otherwise bail out.
217 const AsmWriterInst *OtherInst =
218 getAsmWriterInstByID(NIT-InstIdxs.begin());
220 if (!OtherInst || OtherInst->Operands.size() == Op ||
221 OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
228 // Okay, everything in this command set has the same next operand. Add it
229 // to UniqueOperandCommands and remember that it was consumed.
230 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
232 UniqueOperandCommands[CommandIdx] += Command;
233 InstOpsUsed[CommandIdx]++;
237 // Prepend some of the instructions each case is used for onto the case val.
238 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
239 std::string Instrs = InstrsForCase[i];
240 if (Instrs.size() > 70) {
241 Instrs.erase(Instrs.begin()+70, Instrs.end());
246 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
247 UniqueOperandCommands[i];
252 static void UnescapeString(std::string &Str) {
253 for (unsigned i = 0; i != Str.size(); ++i) {
254 if (Str[i] == '\\' && i != Str.size()-1) {
256 default: continue; // Don't execute the code after the switch.
257 case 'a': Str[i] = '\a'; break;
258 case 'b': Str[i] = '\b'; break;
259 case 'e': Str[i] = 27; break;
260 case 'f': Str[i] = '\f'; break;
261 case 'n': Str[i] = '\n'; break;
262 case 'r': Str[i] = '\r'; break;
263 case 't': Str[i] = '\t'; break;
264 case 'v': Str[i] = '\v'; break;
265 case '"': Str[i] = '\"'; break;
266 case '\'': Str[i] = '\''; break;
267 case '\\': Str[i] = '\\'; break;
269 // Nuke the second character.
270 Str.erase(Str.begin()+i+1);
275 /// EmitPrintInstruction - Generate the code for the "printInstruction" method
276 /// implementation. Destroys all instances of AsmWriterInst information, by
277 /// clearing the Instructions vector.
278 void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
279 Record *AsmWriter = Target.getAsmWriter();
280 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
283 "/// printInstruction - This method is automatically generated by tablegen\n"
284 "/// from the instruction set description.\n"
285 "void " << Target.getName() << ClassName
286 << "::printInstruction(const MCInst *MI, raw_ostream &O) {\n";
288 // Build an aggregate string, and build a table of offsets into it.
289 SequenceToOffsetTable<std::string> StringTable;
291 /// OpcodeInfo - This encodes the index of the string to use for the first
292 /// chunk of the output as well as indices used for operand printing.
293 /// To reduce the number of unhandled cases, we expand the size from 32-bit
294 /// to 32+16 = 48-bit.
295 std::vector<uint64_t> OpcodeInfo;
297 // Add all strings to the string table upfront so it can generate an optimized
299 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
300 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)];
302 AWI->Operands[0].OperandType ==
303 AsmWriterOperand::isLiteralTextOperand &&
304 !AWI->Operands[0].Str.empty()) {
305 std::string Str = AWI->Operands[0].Str;
307 StringTable.add(Str);
311 StringTable.layout();
313 unsigned MaxStringIdx = 0;
314 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
315 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)];
318 // Something not handled by the asmwriter printer.
320 } else if (AWI->Operands[0].OperandType !=
321 AsmWriterOperand::isLiteralTextOperand ||
322 AWI->Operands[0].Str.empty()) {
323 // Something handled by the asmwriter printer, but with no leading string.
324 Idx = StringTable.get("");
326 std::string Str = AWI->Operands[0].Str;
328 Idx = StringTable.get(Str);
329 MaxStringIdx = std::max(MaxStringIdx, Idx);
331 // Nuke the string from the operand list. It is now handled!
332 AWI->Operands.erase(AWI->Operands.begin());
335 // Bias offset by one since we want 0 as a sentinel.
336 OpcodeInfo.push_back(Idx+1);
339 // Figure out how many bits we used for the string index.
340 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2);
342 // To reduce code size, we compactify common instructions into a few bits
343 // in the opcode-indexed table.
344 unsigned BitsLeft = 64-AsmStrBits;
346 std::vector<std::vector<std::string>> TableDrivenOperandPrinters;
349 std::vector<std::string> UniqueOperandCommands;
350 std::vector<unsigned> InstIdxs;
351 std::vector<unsigned> NumInstOpsHandled;
352 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
355 // If we ran out of operands to print, we're done.
356 if (UniqueOperandCommands.empty()) break;
358 // Compute the number of bits we need to represent these cases, this is
359 // ceil(log2(numentries)).
360 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
362 // If we don't have enough bits for this operand, don't include it.
363 if (NumBits > BitsLeft) {
364 DEBUG(errs() << "Not enough bits to densely encode " << NumBits
369 // Otherwise, we can include this in the initial lookup table. Add it in.
370 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
371 if (InstIdxs[i] != ~0U) {
372 OpcodeInfo[i] |= (uint64_t)InstIdxs[i] << (64-BitsLeft);
376 // Remove the info about this operand.
377 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
378 if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
379 if (!Inst->Operands.empty()) {
380 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
381 assert(NumOps <= Inst->Operands.size() &&
382 "Can't remove this many ops!");
383 Inst->Operands.erase(Inst->Operands.begin(),
384 Inst->Operands.begin()+NumOps);
388 // Remember the handlers for this set of operands.
389 TableDrivenOperandPrinters.push_back(std::move(UniqueOperandCommands));
393 // We always emit at least one 32-bit table. A second table is emitted if
394 // more bits are needed.
395 O<<" static const uint32_t OpInfo[] = {\n";
396 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
397 O << " " << (OpcodeInfo[i] & 0xffffffff) << "U,\t// "
398 << NumberedInstructions->at(i)->TheDef->getName() << "\n";
400 // Add a dummy entry so the array init doesn't end with a comma.
405 // Add a second OpInfo table only when it is necessary.
406 // Adjust the type of the second table based on the number of bits needed.
407 O << " static const uint"
408 << ((BitsLeft < 16) ? "32" : (BitsLeft < 24) ? "16" : "8")
409 << "_t OpInfo2[] = {\n";
410 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
411 O << " " << (OpcodeInfo[i] >> 32) << "U,\t// "
412 << NumberedInstructions->at(i)->TheDef->getName() << "\n";
414 // Add a dummy entry so the array init doesn't end with a comma.
419 // Emit the string itself.
420 O << " static const char AsmStrs[] = {\n";
421 StringTable.emit(O, printChar);
424 O << " O << \"\\t\";\n\n";
426 O << " // Emit the opcode for the instruction.\n";
428 // If we have two tables then we need to perform two lookups and combine
429 // the results into a single 64-bit value.
430 O << " uint64_t Bits1 = OpInfo[MI->getOpcode()];\n"
431 << " uint64_t Bits2 = OpInfo2[MI->getOpcode()];\n"
432 << " uint64_t Bits = (Bits2 << 32) | Bits1;\n";
434 // If only one table is used we just need to perform a single lookup.
435 O << " uint32_t Bits = OpInfo[MI->getOpcode()];\n";
437 O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
438 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n";
440 // Output the table driven operand information.
441 BitsLeft = 64-AsmStrBits;
442 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
443 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
445 // Compute the number of bits we need to represent these cases, this is
446 // ceil(log2(numentries)).
447 unsigned NumBits = Log2_32_Ceil(Commands.size());
448 assert(NumBits <= BitsLeft && "consistency error");
450 // Emit code to extract this field from Bits.
451 O << "\n // Fragment " << i << " encoded into " << NumBits
452 << " bits for " << Commands.size() << " unique commands.\n";
454 if (Commands.size() == 2) {
455 // Emit two possibilitys with if/else.
456 O << " if ((Bits >> "
457 << (64-BitsLeft) << ") & "
458 << ((1 << NumBits)-1) << ") {\n"
463 } else if (Commands.size() == 1) {
464 // Emit a single possibility.
465 O << Commands[0] << "\n\n";
467 O << " switch ((Bits >> "
468 << (64-BitsLeft) << ") & "
469 << ((1 << NumBits)-1) << ") {\n"
470 << " default: llvm_unreachable(\"Invalid command number.\");\n";
472 // Print out all the cases.
473 for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
474 O << " case " << i << ":\n";
483 // Okay, delete instructions with no operand info left.
484 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
485 // Entire instruction has been emitted?
486 AsmWriterInst &Inst = Instructions[i];
487 if (Inst.Operands.empty()) {
488 Instructions.erase(Instructions.begin()+i);
494 // Because this is a vector, we want to emit from the end. Reverse all of the
495 // elements in the vector.
496 std::reverse(Instructions.begin(), Instructions.end());
499 // Now that we've emitted all of the operand info that fit into 32 bits, emit
500 // information for those instructions that are left. This is a less dense
501 // encoding, but we expect the main 32-bit table to handle the majority of
503 if (!Instructions.empty()) {
504 // Find the opcode # of inline asm.
505 O << " switch (MI->getOpcode()) {\n";
506 while (!Instructions.empty())
507 EmitInstructions(Instructions, O);
516 static const char *getMinimalTypeForRange(uint64_t Range) {
517 assert(Range < 0xFFFFFFFFULL && "Enum too large");
526 emitRegisterNameString(raw_ostream &O, StringRef AltName,
527 const std::deque<CodeGenRegister> &Registers) {
528 SequenceToOffsetTable<std::string> StringTable;
529 SmallVector<std::string, 4> AsmNames(Registers.size());
531 for (const auto &Reg : Registers) {
532 std::string &AsmName = AsmNames[i++];
534 // "NoRegAltName" is special. We don't need to do a lookup for that,
535 // as it's just a reference to the default register name.
536 if (AltName == "" || AltName == "NoRegAltName") {
537 AsmName = Reg.TheDef->getValueAsString("AsmName");
539 AsmName = Reg.getName();
541 // Make sure the register has an alternate name for this index.
542 std::vector<Record*> AltNameList =
543 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
545 for (e = AltNameList.size();
546 Idx < e && (AltNameList[Idx]->getName() != AltName);
549 // If the register has an alternate name for this index, use it.
550 // Otherwise, leave it empty as an error flag.
552 std::vector<std::string> AltNames =
553 Reg.TheDef->getValueAsListOfStrings("AltNames");
554 if (AltNames.size() <= Idx)
555 PrintFatalError(Reg.TheDef->getLoc(),
556 "Register definition missing alt name for '" +
558 AsmName = AltNames[Idx];
561 StringTable.add(AsmName);
564 StringTable.layout();
565 O << " static const char AsmStrs" << AltName << "[] = {\n";
566 StringTable.emit(O, printChar);
569 O << " static const " << getMinimalTypeForRange(StringTable.size()-1)
570 << " RegAsmOffset" << AltName << "[] = {";
571 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
574 O << StringTable.get(AsmNames[i]) << ", ";
580 void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
581 Record *AsmWriter = Target.getAsmWriter();
582 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
583 const auto &Registers = Target.getRegBank().getRegisters();
584 std::vector<Record*> AltNameIndices = Target.getRegAltNameIndices();
585 bool hasAltNames = AltNameIndices.size() > 1;
588 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
589 "/// from the register set description. This returns the assembler name\n"
590 "/// for the specified register.\n"
591 "const char *" << Target.getName() << ClassName << "::";
593 O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n";
595 O << "getRegisterName(unsigned RegNo) {\n";
596 O << " assert(RegNo && RegNo < " << (Registers.size()+1)
597 << " && \"Invalid register number!\");\n"
601 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i)
602 emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers);
604 emitRegisterNameString(O, "", Registers);
607 O << " switch(AltIdx) {\n"
608 << " default: llvm_unreachable(\"Invalid register alt name index!\");\n";
609 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) {
610 std::string Namespace = AltNameIndices[1]->getValueAsString("Namespace");
611 std::string AltName(AltNameIndices[i]->getName());
612 O << " case " << Namespace << "::" << AltName << ":\n"
613 << " assert(*(AsmStrs" << AltName << "+RegAsmOffset"
614 << AltName << "[RegNo-1]) &&\n"
615 << " \"Invalid alt name index for register!\");\n"
616 << " return AsmStrs" << AltName << "+RegAsmOffset"
617 << AltName << "[RegNo-1];\n";
621 O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
622 << " \"Invalid alt name index for register!\");\n"
623 << " return AsmStrs+RegAsmOffset[RegNo-1];\n";
629 // IAPrinter - Holds information about an InstAlias. Two InstAliases match if
630 // they both have the same conditionals. In which case, we cannot print out the
631 // alias for that pattern.
633 std::vector<std::string> Conds;
634 std::map<StringRef, std::pair<int, int>> OpMap;
635 SmallVector<Record*, 4> ReqFeatures;
638 std::string AsmString;
640 IAPrinter(std::string R, std::string AS) : Result(R), AsmString(AS) {}
642 void addCond(const std::string &C) { Conds.push_back(C); }
644 void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) {
645 assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range");
646 assert(PrintMethodIdx >= -1 && PrintMethodIdx < 0xFF &&
648 OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx);
651 bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); }
652 int getOpIndex(StringRef Op) { return OpMap[Op].first; }
653 std::pair<int, int> &getOpData(StringRef Op) { return OpMap[Op]; }
655 std::pair<StringRef, StringRef::iterator> parseName(StringRef::iterator Start,
656 StringRef::iterator End) {
657 StringRef::iterator I = Start;
658 StringRef::iterator Next;
662 while (I != End && *I != '}')
669 // $name, just eat the usual suspects.
671 ((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') ||
672 (*I >= '0' && *I <= '9') || *I == '_'))
677 return std::make_pair(StringRef(Start, I - Start), Next);
680 void print(raw_ostream &O) {
681 if (Conds.empty() && ReqFeatures.empty()) {
682 O.indent(6) << "return true;\n";
688 for (std::vector<std::string>::iterator
689 I = Conds.begin(), E = Conds.end(); I != E; ++I) {
690 if (I != Conds.begin()) {
699 O.indent(6) << "// " << Result << "\n";
701 // Directly mangle mapped operands into the string. Each operand is
702 // identified by a '$' sign followed by a byte identifying the number of the
703 // operand. We add one to the index to avoid zero bytes.
704 StringRef ASM(AsmString);
705 SmallString<128> OutString;
706 raw_svector_ostream OS(OutString);
707 for (StringRef::iterator I = ASM.begin(), E = ASM.end(); I != E;) {
711 std::tie(Name, I) = parseName(++I, E);
712 assert(isOpMapped(Name) && "Unmapped operand!");
714 int OpIndex, PrintIndex;
715 std::tie(OpIndex, PrintIndex) = getOpData(Name);
716 if (PrintIndex == -1) {
717 // Can use the default printOperand route.
718 OS << format("\\x%02X", (unsigned char)OpIndex + 1);
720 // 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand
721 // number, and which of our pre-detected Methods to call.
722 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1);
730 O.indent(6) << "AsmString = \"" << OutString.str() << "\";\n";
732 O.indent(6) << "break;\n";
736 bool operator==(const IAPrinter &RHS) {
737 if (Conds.size() != RHS.Conds.size())
741 for (std::vector<std::string>::iterator
742 I = Conds.begin(), E = Conds.end(); I != E; ++I)
743 if (*I != RHS.Conds[Idx++])
750 } // end anonymous namespace
752 static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) {
753 std::string FlatAsmString =
754 CodeGenInstruction::FlattenAsmStringVariants(AsmString, Variant);
755 AsmString = FlatAsmString;
757 return AsmString.count(' ') + AsmString.count('\t');
761 struct AliasPriorityComparator {
762 typedef std::pair<CodeGenInstAlias *, int> ValueType;
763 bool operator()(const ValueType &LHS, const ValueType &RHS) {
764 if (LHS.second == RHS.second) {
765 // We don't actually care about the order, but for consistency it
766 // shouldn't depend on pointer comparisons.
767 return LHS.first->TheDef->getName() < RHS.first->TheDef->getName();
770 // Aliases with larger priorities should be considered first.
771 return LHS.second > RHS.second;
777 void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
778 Record *AsmWriter = Target.getAsmWriter();
780 O << "\n#ifdef PRINT_ALIAS_INSTR\n";
781 O << "#undef PRINT_ALIAS_INSTR\n\n";
783 //////////////////////////////
784 // Gather information about aliases we need to print
785 //////////////////////////////
787 // Emit the method that prints the alias instruction.
788 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
789 unsigned Variant = AsmWriter->getValueAsInt("Variant");
791 std::vector<Record*> AllInstAliases =
792 Records.getAllDerivedDefinitions("InstAlias");
794 // Create a map from the qualified name to a list of potential matches.
795 typedef std::set<std::pair<CodeGenInstAlias*, int>, AliasPriorityComparator>
797 std::map<std::string, AliasWithPriority> AliasMap;
798 for (std::vector<Record*>::iterator
799 I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) {
800 CodeGenInstAlias *Alias = new CodeGenInstAlias(*I, Variant, Target);
801 const Record *R = *I;
802 int Priority = R->getValueAsInt("EmitPriority");
804 continue; // Aliases with priority 0 are never emitted.
806 const DagInit *DI = R->getValueAsDag("ResultInst");
807 const DefInit *Op = cast<DefInit>(DI->getOperator());
808 AliasMap[getQualifiedName(Op->getDef())].insert(std::make_pair(Alias,
812 // A map of which conditions need to be met for each instruction operand
813 // before it can be matched to the mnemonic.
814 std::map<std::string, std::vector<IAPrinter*> > IAPrinterMap;
816 // A list of MCOperandPredicates for all operands in use, and the reverse map
817 std::vector<const Record*> MCOpPredicates;
818 DenseMap<const Record*, unsigned> MCOpPredicateMap;
820 for (auto &Aliases : AliasMap) {
821 for (auto &Alias : Aliases.second) {
822 const CodeGenInstAlias *CGA = Alias.first;
823 unsigned LastOpNo = CGA->ResultInstOperandIndex.size();
824 unsigned NumResultOps =
825 CountNumOperands(CGA->ResultInst->AsmString, Variant);
827 // Don't emit the alias if it has more operands than what it's aliasing.
828 if (NumResultOps < CountNumOperands(CGA->AsmString, Variant))
831 IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(),
834 unsigned NumMIOps = 0;
835 for (auto &Operand : CGA->ResultOperands)
836 NumMIOps += Operand.getMINumOperands();
839 Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(NumMIOps);
842 bool CantHandle = false;
844 unsigned MIOpNum = 0;
845 for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
846 std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")";
848 const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i];
851 case CodeGenInstAlias::ResultOperand::K_Record: {
852 const Record *Rec = RO.getRecord();
853 StringRef ROName = RO.getName();
854 int PrintMethodIdx = -1;
856 // These two may have a PrintMethod, which we want to record (if it's
857 // the first time we've seen it) and provide an index for the aliasing
859 if (Rec->isSubClassOf("RegisterOperand") ||
860 Rec->isSubClassOf("Operand")) {
861 std::string PrintMethod = Rec->getValueAsString("PrintMethod");
862 if (PrintMethod != "" && PrintMethod != "printOperand") {
863 PrintMethodIdx = std::find(PrintMethods.begin(),
864 PrintMethods.end(), PrintMethod) -
865 PrintMethods.begin();
866 if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size())
867 PrintMethods.push_back(PrintMethod);
871 if (Rec->isSubClassOf("RegisterOperand"))
872 Rec = Rec->getValueAsDef("RegClass");
873 if (Rec->isSubClassOf("RegisterClass")) {
874 IAP->addCond(Op + ".isReg()");
876 if (!IAP->isOpMapped(ROName)) {
877 IAP->addOperand(ROName, MIOpNum, PrintMethodIdx);
878 Record *R = CGA->ResultOperands[i].getRecord();
879 if (R->isSubClassOf("RegisterOperand"))
880 R = R->getValueAsDef("RegClass");
881 Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" +
882 R->getName() + "RegClassID)"
883 ".contains(" + Op + ".getReg())";
885 Cond = Op + ".getReg() == MI->getOperand(" +
886 llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()";
889 // Assume all printable operands are desired for now. This can be
890 // overridden in the InstAlias instantiation if necessary.
891 IAP->addOperand(ROName, MIOpNum, PrintMethodIdx);
893 // There might be an additional predicate on the MCOperand
894 unsigned Entry = MCOpPredicateMap[Rec];
896 if (!Rec->isValueUnset("MCOperandPredicate")) {
897 MCOpPredicates.push_back(Rec);
898 Entry = MCOpPredicates.size();
899 MCOpPredicateMap[Rec] = Entry;
901 break; // No conditions on this operand at all
903 Cond = Target.getName() + ClassName + "ValidateMCOperand(" +
904 Op + ", " + llvm::utostr(Entry) + ")";
906 // for all subcases of ResultOperand::K_Record:
910 case CodeGenInstAlias::ResultOperand::K_Imm: {
911 // Just because the alias has an immediate result, doesn't mean the
912 // MCInst will. An MCExpr could be present, for example.
913 IAP->addCond(Op + ".isImm()");
915 Cond = Op + ".getImm() == "
916 + llvm::utostr(CGA->ResultOperands[i].getImm());
920 case CodeGenInstAlias::ResultOperand::K_Reg:
921 // If this is zero_reg, something's playing tricks we're not
922 // equipped to handle.
923 if (!CGA->ResultOperands[i].getRegister()) {
928 Cond = Op + ".getReg() == " + Target.getName() +
929 "::" + CGA->ResultOperands[i].getRegister()->getName();
935 MIOpNum += RO.getMINumOperands();
938 if (CantHandle) continue;
939 IAPrinterMap[Aliases.first].push_back(IAP);
943 //////////////////////////////
944 // Write out the printAliasInstr function
945 //////////////////////////////
948 raw_string_ostream HeaderO(Header);
950 HeaderO << "bool " << Target.getName() << ClassName
951 << "::printAliasInstr(const MCInst"
952 << " *MI, raw_ostream &OS) {\n";
955 raw_string_ostream CasesO(Cases);
957 for (std::map<std::string, std::vector<IAPrinter*> >::iterator
958 I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) {
959 std::vector<IAPrinter*> &IAPs = I->second;
960 std::vector<IAPrinter*> UniqueIAPs;
962 for (std::vector<IAPrinter*>::iterator
963 II = IAPs.begin(), IE = IAPs.end(); II != IE; ++II) {
964 IAPrinter *LHS = *II;
966 for (std::vector<IAPrinter*>::iterator
967 III = IAPs.begin(), IIE = IAPs.end(); III != IIE; ++III) {
968 IAPrinter *RHS = *III;
969 if (LHS != RHS && *LHS == *RHS) {
975 if (!IsDup) UniqueIAPs.push_back(LHS);
978 if (UniqueIAPs.empty()) continue;
980 CasesO.indent(2) << "case " << I->first << ":\n";
982 for (std::vector<IAPrinter*>::iterator
983 II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) {
984 IAPrinter *IAP = *II;
990 CasesO.indent(4) << "return false;\n";
993 if (CasesO.str().empty()) {
995 O << " return false;\n";
997 O << "#endif // PRINT_ALIAS_INSTR\n";
1001 if (MCOpPredicates.size())
1002 O << "static bool " << Target.getName() << ClassName
1003 << "ValidateMCOperand(\n"
1004 << " const MCOperand &MCOp, unsigned PredicateIndex);\n";
1007 O.indent(2) << "const char *AsmString;\n";
1008 O.indent(2) << "switch (MI->getOpcode()) {\n";
1009 O.indent(2) << "default: return false;\n";
1011 O.indent(2) << "}\n\n";
1013 // Code that prints the alias, replacing the operands with the ones from the
1015 O << " unsigned I = 0;\n";
1016 O << " while (AsmString[I] != ' ' && AsmString[I] != '\t' &&\n";
1017 O << " AsmString[I] != '\\0')\n";
1019 O << " OS << '\\t' << StringRef(AsmString, I);\n";
1021 O << " if (AsmString[I] != '\\0') {\n";
1022 O << " OS << '\\t';\n";
1024 O << " if (AsmString[I] == '$') {\n";
1026 O << " if (AsmString[I] == (char)0xff) {\n";
1028 O << " int OpIdx = AsmString[I++] - 1;\n";
1029 O << " int PrintMethodIdx = AsmString[I++] - 1;\n";
1030 O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);\n";
1032 O << " printOperand(MI, unsigned(AsmString[I++]) - 1, OS);\n";
1034 O << " OS << AsmString[I++];\n";
1036 O << " } while (AsmString[I] != '\\0');\n";
1039 O << " return true;\n";
1042 //////////////////////////////
1043 // Write out the printCustomAliasOperand function
1044 //////////////////////////////
1046 O << "void " << Target.getName() << ClassName << "::"
1047 << "printCustomAliasOperand(\n"
1048 << " const MCInst *MI, unsigned OpIdx,\n"
1049 << " unsigned PrintMethodIdx, raw_ostream &OS) {\n";
1050 if (PrintMethods.empty())
1051 O << " llvm_unreachable(\"Unknown PrintMethod kind\");\n";
1053 O << " switch (PrintMethodIdx) {\n"
1055 << " llvm_unreachable(\"Unknown PrintMethod kind\");\n"
1058 for (unsigned i = 0; i < PrintMethods.size(); ++i) {
1059 O << " case " << i << ":\n"
1060 << " " << PrintMethods[i] << "(MI, OpIdx, OS);\n"
1067 if (MCOpPredicates.size()) {
1068 O << "static bool " << Target.getName() << ClassName
1069 << "ValidateMCOperand(\n"
1070 << " const MCOperand &MCOp, unsigned PredicateIndex) {\n"
1071 << " switch (PredicateIndex) {\n"
1073 << " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n"
1076 for (unsigned i = 0; i < MCOpPredicates.size(); ++i) {
1077 Init *MCOpPred = MCOpPredicates[i]->getValueInit("MCOperandPredicate");
1078 if (StringInit *SI = dyn_cast<StringInit>(MCOpPred)) {
1079 O << " case " << i + 1 << ": {\n"
1080 << SI->getValue() << "\n"
1083 llvm_unreachable("Unexpected MCOperandPredicate field!");
1089 O << "#endif // PRINT_ALIAS_INSTR\n";
1092 AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) {
1093 Record *AsmWriter = Target.getAsmWriter();
1094 for (const CodeGenInstruction *I : Target.instructions())
1095 if (!I->AsmString.empty() && I->TheDef->getName() != "PHI")
1096 Instructions.push_back(
1097 AsmWriterInst(*I, AsmWriter->getValueAsInt("Variant")));
1099 // Get the instruction numbering.
1100 NumberedInstructions = &Target.getInstructionsByEnumValue();
1102 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
1103 // all machine instructions are necessarily being printed, so there may be
1104 // target instructions not in this map.
1105 for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
1106 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
1109 void AsmWriterEmitter::run(raw_ostream &O) {
1110 EmitPrintInstruction(O);
1111 EmitGetRegisterName(O);
1112 EmitPrintAliasInstruction(O);
1118 void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) {
1119 emitSourceFileHeader("Assembly Writer Source Fragment", OS);
1120 AsmWriterEmitter(RK).run(OS);
1123 } // End llvm namespace