1 # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s
2 # RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s
4 #------------------------------------------------------------------------------
6 #------------------------------------------------------------------------------
7 # CHECK: add w4, w5, #0
8 # CHECK: add w2, w3, #4095
9 # CHECK: add w30, w29, #1, lsl #12
10 # CHECK: add w13, w5, #4095, lsl #12
11 # CHECK: add x5, x7, #1638
18 # CHECK: add w20, wsp, #801
19 # CHECK: add wsp, wsp, #1104
20 # CHECK: add wsp, w30, #4084
25 # CHECK: add x0, x24, #291
26 # CHECK: add x3, x24, #4095, lsl #12
27 # CHECK: add x8, sp, #1074
28 # CHECK: add sp, x29, #3816
34 # CHECK: sub w0, wsp, #4077
35 # CHECK: sub w4, w20, #546, lsl #12
36 # CHECK: sub sp, sp, #288
37 # CHECK: sub wsp, w19, #16
44 # CHECK: adds w13, w23, #291, lsl #12
45 # CHECK: cmn w2, #4095
46 # CHECK: adds w20, wsp, #0
47 # CHECK: cmn x3, #1, lsl #12
53 # CHECK: cmp sp, #20, lsl #12
54 # CHECK: cmp x30, #4095
55 # CHECK: subs x4, sp, #3822
60 # These should really be CMN
61 # CHECK: cmn w3, #291, lsl #12
62 # CHECK: cmn wsp, #1365
63 # CHECK: cmn sp, #1092, lsl #12
77 #------------------------------------------------------------------------------
78 # Add-subtract (shifted register)
79 #------------------------------------------------------------------------------
81 # CHECK: add w3, w5, w7
82 # CHECK: add wzr, w3, w5
83 # CHECK: add w20, wzr, w4
84 # CHECK: add w4, w6, wzr
85 # CHECK: add w11, w13, w15
86 # CHECK: add w9, w3, wzr, lsl #10
87 # CHECK: add w17, w29, w20, lsl #31
88 # CHECK: add w21, w22, w23, lsr #0
89 # CHECK: add w24, w25, w26, lsr #18
90 # CHECK: add w27, w28, w29, lsr #31
91 # CHECK: add w2, w3, w4, asr #0
92 # CHECK: add w5, w6, w7, asr #21
93 # CHECK: add w8, w9, w10, asr #31
108 # CHECK: add x3, x5, x7
109 # CHECK: add xzr, x3, x5
110 # CHECK: add x20, xzr, x4
111 # CHECK: add x4, x6, xzr
112 # CHECK: add x11, x13, x15
113 # CHECK: add x9, x3, xzr, lsl #10
114 # CHECK: add x17, x29, x20, lsl #63
115 # CHECK: add x21, x22, x23, lsr #0
116 # CHECK: add x24, x25, x26, lsr #18
117 # CHECK: add x27, x28, x29, lsr #63
118 # CHECK: add x2, x3, x4, asr #0
119 # CHECK: add x5, x6, x7, asr #21
120 # CHECK: add x8, x9, x10, asr #63
135 # CHECK: adds w3, w5, w7
137 # CHECK: adds w20, wzr, w4
138 # CHECK: adds w4, w6, wzr
139 # CHECK: adds w11, w13, w15
140 # CHECK: adds w9, w3, wzr, lsl #10
141 # CHECK: adds w17, w29, w20, lsl #31
142 # CHECK: adds w21, w22, w23, lsr #0
143 # CHECK: adds w24, w25, w26, lsr #18
144 # CHECK: adds w27, w28, w29, lsr #31
145 # CHECK: adds w2, w3, w4, asr #0
146 # CHECK: adds w5, w6, w7, asr #21
147 # CHECK: adds w8, w9, w10, asr #31
162 # CHECK: adds x3, x5, x7
164 # CHECK: adds x20, xzr, x4
165 # CHECK: adds x4, x6, xzr
166 # CHECK: adds x11, x13, x15
167 # CHECK: adds x9, x3, xzr, lsl #10
168 # CHECK: adds x17, x29, x20, lsl #63
169 # CHECK: adds x21, x22, x23, lsr #0
170 # CHECK: adds x24, x25, x26, lsr #18
171 # CHECK: adds x27, x28, x29, lsr #63
172 # CHECK: adds x2, x3, x4, asr #0
173 # CHECK: adds x5, x6, x7, asr #21
174 # CHECK: adds x8, x9, x10, asr #63
189 # CHECK: sub w3, w5, w7
190 # CHECK: sub wzr, w3, w5
191 # CHECK: {{sub w20, wzr, w4|neg w20, w4}}
192 # CHECK: sub w4, w6, wzr
193 # CHECK: sub w11, w13, w15
194 # CHECK: sub w9, w3, wzr, lsl #10
195 # CHECK: sub w17, w29, w20, lsl #31
196 # CHECK: sub w21, w22, w23, lsr #0
197 # CHECK: sub w24, w25, w26, lsr #18
198 # CHECK: sub w27, w28, w29, lsr #31
199 # CHECK: sub w2, w3, w4, asr #0
200 # CHECK: sub w5, w6, w7, asr #21
201 # CHECK: sub w8, w9, w10, asr #31
216 # CHECK: sub x3, x5, x7
217 # CHECK: sub xzr, x3, x5
218 # CHECK: {{sub x20, xzr, x4|neg x20, x4}}
219 # CHECK: sub x4, x6, xzr
220 # CHECK: sub x11, x13, x15
221 # CHECK: sub x9, x3, xzr, lsl #10
222 # CHECK: sub x17, x29, x20, lsl #63
223 # CHECK: sub x21, x22, x23, lsr #0
224 # CHECK: sub x24, x25, x26, lsr #18
225 # CHECK: sub x27, x28, x29, lsr #63
226 # CHECK: sub x2, x3, x4, asr #0
227 # CHECK: sub x5, x6, x7, asr #21
228 # CHECK: sub x8, x9, x10, asr #63
243 # CHECK: subs w3, w5, w7
245 # CHECK: {{subs w20, wzr, w4|negs w20, w4}}
246 # CHECK: subs w4, w6, wzr
247 # CHECK: subs w11, w13, w15
248 # CHECK: subs w9, w3, wzr, lsl #10
249 # CHECK: subs w17, w29, w20, lsl #31
250 # CHECK: subs w21, w22, w23, lsr #0
251 # CHECK: subs w24, w25, w26, lsr #18
252 # CHECK: subs w27, w28, w29, lsr #31
253 # CHECK: subs w2, w3, w4, asr #0
254 # CHECK: subs w5, w6, w7, asr #21
255 # CHECK: subs w8, w9, w10, asr #31
270 # CHECK: subs x3, x5, x7
272 # CHECK: {{subs x20, xzr, x4|negs x20, x4}}
273 # CHECK: subs x4, x6, xzr
274 # CHECK: subs x11, x13, x15
275 # CHECK: subs x9, x3, xzr, lsl #10
276 # CHECK: subs x17, x29, x20, lsl #63
277 # CHECK: subs x21, x22, x23, lsr #0
278 # CHECK: subs x24, x25, x26, lsr #18
279 # CHECK: subs x27, x28, x29, lsr #63
280 # CHECK: subs x2, x3, x4, asr #0
281 # CHECK: subs x5, x6, x7, asr #21
282 # CHECK: subs x8, x9, x10, asr #63
301 # CHECK: cmn w8, w9, lsl #15
302 # CHECK: cmn w10, w11, lsl #31
303 # CHECK: cmn w12, w13, lsr #0
304 # CHECK: cmn w14, w15, lsr #21
305 # CHECK: cmn w16, w17, lsr #31
306 # CHECK: cmn w18, w19, asr #0
307 # CHECK: cmn w20, w21, asr #22
308 # CHECK: cmn w22, w23, asr #31
326 # CHECK: cmn x8, x9, lsl #15
327 # CHECK: cmn x10, x11, lsl #63
328 # CHECK: cmn x12, x13, lsr #0
329 # CHECK: cmn x14, x15, lsr #41
330 # CHECK: cmn x16, x17, lsr #63
331 # CHECK: cmn x18, x19, asr #0
332 # CHECK: cmn x20, x21, asr #55
333 # CHECK: cmn x22, x23, asr #63
351 # CHECK: cmp w8, w9, lsl #15
352 # CHECK: cmp w10, w11, lsl #31
353 # CHECK: cmp w12, w13, lsr #0
354 # CHECK: cmp w14, w15, lsr #21
355 # CHECK: cmp w16, w17, lsr #31
356 # CHECK: cmp w18, w19, asr #0
357 # CHECK: cmp w20, w21, asr #22
358 # CHECK: cmp w22, w23, asr #31
376 # CHECK: cmp x8, x9, lsl #15
377 # CHECK: cmp x10, x11, lsl #63
378 # CHECK: cmp x12, x13, lsr #0
379 # CHECK: cmp x14, x15, lsr #41
380 # CHECK: cmp x16, x17, lsr #63
381 # CHECK: cmp x18, x19, asr #0
382 # CHECK: cmp x20, x21, asr #55
383 # CHECK: cmp x22, x23, asr #63
397 # CHECK: {{sub w29, wzr|neg w29}}, w30
398 # CHECK: {{sub w30, wzr|neg w30}}, wzr
399 # CHECK: {{sub wzr, wzr|neg wzr}}, w0
400 # CHECK: {{sub w28, wzr|neg w28}}, w27
401 # CHECK: {{sub w26, wzr|neg w26}}, w25, lsl #29
402 # CHECK: {{sub w24, wzr|neg w24}}, w23, lsl #31
403 # CHECK: {{sub w22, wzr|neg w22}}, w21, lsr #0
404 # CHECK: {{sub w20, wzr|neg w20}}, w19, lsr #1
405 # CHECK: {{sub w18, wzr|neg w18}}, w17, lsr #31
406 # CHECK: {{sub w16, wzr|neg w16}}, w15, asr #0
407 # CHECK: {{sub w14, wzr|neg w14}}, w13, asr #12
408 # CHECK: {{sub w12, wzr|neg w12}}, w11, asr #31
422 # CHECK: {{sub x29, xzr|neg x29}}, x30
423 # CHECK: {{sub x30, xzr|neg x30}}, xzr
424 # CHECK: {{sub xzr, xzr|neg xzr}}, x0
425 # CHECK: {{sub x28, xzr|neg x28}}, x27
426 # CHECK: {{sub x26, xzr|neg x26}}, x25, lsl #29
427 # CHECK: {{sub x24, xzr|neg x24}}, x23, lsl #31
428 # CHECK: {{sub x22, xzr|neg x22}}, x21, lsr #0
429 # CHECK: {{sub x20, xzr|neg x20}}, x19, lsr #1
430 # CHECK: {{sub x18, xzr|neg x18}}, x17, lsr #31
431 # CHECK: {{sub x16, xzr|neg x16}}, x15, asr #0
432 # CHECK: {{sub x14, xzr|neg x14}}, x13, asr #12
433 # CHECK: {{sub x12, xzr|neg x12}}, x11, asr #31
447 # CHECK: {{subs w29, wzr|negs w29}}, w30
448 # CHECK: {{subs w30, wzr|negs w30}}, wzr
450 # CHECK: {{subs w28, wzr|negs w28}}, w27
451 # CHECK: {{subs w26, wzr|negs w26}}, w25, lsl #29
452 # CHECK: {{subs w24, wzr|negs w24}}, w23, lsl #31
453 # CHECK: {{subs w22, wzr|negs w22}}, w21, lsr #0
454 # CHECK: {{subs w20, wzr|negs w20}}, w19, lsr #1
455 # CHECK: {{subs w18, wzr|negs w18}}, w17, lsr #31
456 # CHECK: {{subs w16, wzr|negs w16}}, w15, asr #0
457 # CHECK: {{subs w14, wzr|negs w14}}, w13, asr #12
458 # CHECK: {{subs w12, wzr|negs w12}}, w11, asr #31
472 # CHECK: {{subs x29, xzr|negs x29}}, x30
473 # CHECK: {{subs x30, xzr|negs x30}}, xzr
475 # CHECK: {{subs x28, xzr|negs x28}}, x27
476 # CHECK: {{subs x26, xzr|negs x26}}, x25, lsl #29
477 # CHECK: {{subs x24, xzr|negs x24}}, x23, lsl #31
478 # CHECK: {{subs x22, xzr|negs x22}}, x21, lsr #0
479 # CHECK: {{subs x20, xzr|negs x20}}, x19, lsr #1
480 # CHECK: {{subs x18, xzr|negs x18}}, x17, lsr #31
481 # CHECK: {{subs x16, xzr|negs x16}}, x15, asr #0
482 # CHECK: {{subs x14, xzr|negs x14}}, x13, asr #12
483 # CHECK: {{subs x12, xzr|negs x12}}, x11, asr #31
497 #------------------------------------------------------------------------------
498 # Add-subtract (shifted register)
499 #------------------------------------------------------------------------------
501 # CHECK: adc w29, w27, w25
502 # CHECK: adc wzr, w3, w4
503 # CHECK: adc w9, wzr, w10
504 # CHECK: adc w20, w0, wzr
510 # CHECK: adc x29, x27, x25
511 # CHECK: adc xzr, x3, x4
512 # CHECK: adc x9, xzr, x10
513 # CHECK: adc x20, x0, xzr
519 # CHECK: adcs w29, w27, w25
520 # CHECK: adcs wzr, w3, w4
521 # CHECK: adcs w9, wzr, w10
522 # CHECK: adcs w20, w0, wzr
528 # CHECK: adcs x29, x27, x25
529 # CHECK: adcs xzr, x3, x4
530 # CHECK: adcs x9, xzr, x10
531 # CHECK: adcs x20, x0, xzr
537 # CHECK: sbc w29, w27, w25
538 # CHECK: sbc wzr, w3, w4
540 # CHECK: sbc w20, w0, wzr
546 # CHECK: sbc x29, x27, x25
547 # CHECK: sbc xzr, x3, x4
549 # CHECK: sbc x20, x0, xzr
555 # CHECK: sbcs w29, w27, w25
556 # CHECK: sbcs wzr, w3, w4
557 # CHECK: ngcs w9, w10
558 # CHECK: sbcs w20, w0, wzr
564 # CHECK: sbcs x29, x27, x25
565 # CHECK: sbcs xzr, x3, x4
566 # CHECK: ngcs x9, x10
567 # CHECK: sbcs x20, x0, xzr
575 # CHECK: ngc w23, wzr
580 # CHECK: ngc x29, x30
587 # CHECK: ngcs w3, w12
588 # CHECK: ngcs wzr, w9
589 # CHECK: ngcs w23, wzr
594 # CHECK: ngcs x29, x30
595 # CHECK: ngcs xzr, x0
596 # CHECK: ngcs x0, xzr
601 #------------------------------------------------------------------------------
602 # Compare and branch (immediate)
603 #------------------------------------------------------------------------------
605 # CHECK: sbfx x1, x2, #3, #2
606 # CHECK: asr x3, x4, #63
607 # CHECK: asr wzr, wzr, #31
608 # CHECK: sbfx w12, w9, #0, #1
614 # CHECK: ubfiz x4, x5, #52, #11
615 # CHECK: ubfx xzr, x4, #0, #1
616 # CHECK: ubfiz x4, xzr, #1, #6
617 # CHECK: lsr x5, x6, #12
623 # CHECK: bfi x4, x5, #52, #11
624 # CHECK: bfxil xzr, x4, #0, #1
625 # CHECK: bfi x4, xzr, #1, #6
626 # CHECK: bfxil x5, x6, #12, #52
633 # CHECK: sxtb xzr, w3
634 # CHECK: sxth w9, w10
636 # CHECK: sxtw x3, w30
644 # CHECK: uxth w9, w10
645 # CHECK: ubfx x3, x30, #0, #32
650 # CHECK: asr w3, w2, #0
651 # CHECK: asr w9, w10, #31
652 # CHECK: asr x20, x21, #63
653 # CHECK: asr w1, wzr, #3
659 # CHECK: lsr w3, w2, #0
660 # CHECK: lsr w9, w10, #31
661 # CHECK: lsr x20, x21, #63
662 # CHECK: lsr wzr, wzr, #3
668 # CHECK: lsr w3, w2, #0
669 # CHECK: lsl w9, w10, #31
670 # CHECK: lsl x20, x21, #63
671 # CHECK: lsl w1, wzr, #3
677 # CHECK: sbfx w9, w10, #0, #1
678 # CHECK: sbfiz x2, x3, #63, #1
679 # CHECK: asr x19, x20, #0
680 # CHECK: sbfiz x9, x10, #5, #59
681 # CHECK: asr w9, w10, #0
682 # CHECK: sbfiz w11, w12, #31, #1
683 # CHECK: sbfiz w13, w14, #29, #3
684 # CHECK: sbfiz xzr, xzr, #10, #11
694 # CHECK: sbfx w9, w10, #0, #1
695 # CHECK: asr x2, x3, #63
696 # CHECK: asr x19, x20, #0
697 # CHECK: asr x9, x10, #5
698 # CHECK: asr w9, w10, #0
699 # CHECK: asr w11, w12, #31
700 # CHECK: asr w13, w14, #29
701 # CHECK: sbfx xzr, xzr, #10, #11
711 # CHECK: bfxil w9, w10, #0, #1
712 # CHECK: bfi x2, x3, #63, #1
713 # CHECK: bfxil x19, x20, #0, #64
714 # CHECK: bfi x9, x10, #5, #59
715 # CHECK: bfxil w9, w10, #0, #32
716 # CHECK: bfi w11, w12, #31, #1
717 # CHECK: bfi w13, w14, #29, #3
718 # CHECK: bfi xzr, xzr, #10, #11
728 # CHECK: bfxil w9, w10, #0, #1
729 # CHECK: bfxil x2, x3, #63, #1
730 # CHECK: bfxil x19, x20, #0, #64
731 # CHECK: bfxil x9, x10, #5, #59
732 # CHECK: bfxil w9, w10, #0, #32
733 # CHECK: bfxil w11, w12, #31, #1
734 # CHECK: bfxil w13, w14, #29, #3
735 # CHECK: bfxil xzr, xzr, #10, #11
745 # CHECK: ubfx w9, w10, #0, #1
746 # CHECK: lsl x2, x3, #63
747 # CHECK: lsr x19, x20, #0
748 # CHECK: lsl x9, x10, #5
749 # CHECK: lsr w9, w10, #0
750 # CHECK: lsl w11, w12, #31
751 # CHECK: lsl w13, w14, #29
752 # CHECK: ubfiz xzr, xzr, #10, #11
762 # CHECK: ubfx w9, w10, #0, #1
763 # CHECK: lsr x2, x3, #63
764 # CHECK: lsr x19, x20, #0
765 # CHECK: lsr x9, x10, #5
766 # CHECK: lsr w9, w10, #0
767 # CHECK: lsr w11, w12, #31
768 # CHECK: lsr w13, w14, #29
769 # CHECK: ubfx xzr, xzr, #10, #11
780 #------------------------------------------------------------------------------
781 # Compare and branch (immediate)
782 #------------------------------------------------------------------------------
786 # CHECK: cbnz x2, #-4
787 # CHECK: cbnz x26, #1048572
794 # CHECK: cbnz xzr, #0
798 #------------------------------------------------------------------------------
799 # Conditional branch (immediate)
800 #------------------------------------------------------------------------------
803 # CHECK: b.ge #1048572
809 #------------------------------------------------------------------------------
810 # Conditional compare (immediate)
811 #------------------------------------------------------------------------------
813 # CHECK: ccmp w1, #31, #0, eq
814 # CHECK: ccmp w3, #0, #15, hs
815 # CHECK: ccmp wzr, #15, #13, hs
820 # CHECK: ccmp x9, #31, #0, le
821 # CHECK: ccmp x3, #0, #15, gt
822 # CHECK: ccmp xzr, #5, #7, ne
827 # CHECK: ccmn w1, #31, #0, eq
828 # CHECK: ccmn w3, #0, #15, hs
829 # CHECK: ccmn wzr, #15, #13, hs
834 # CHECK: ccmn x9, #31, #0, le
835 # CHECK: ccmn x3, #0, #15, gt
836 # CHECK: ccmn xzr, #5, #7, ne
841 #------------------------------------------------------------------------------
842 # Conditional compare (register)
843 #------------------------------------------------------------------------------
845 # CHECK: ccmp w1, wzr, #0, eq
846 # CHECK: ccmp w3, w0, #15, hs
847 # CHECK: ccmp wzr, w15, #13, hs
852 # CHECK: ccmp x9, xzr, #0, le
853 # CHECK: ccmp x3, x0, #15, gt
854 # CHECK: ccmp xzr, x5, #7, ne
859 # CHECK: ccmn w1, wzr, #0, eq
860 # CHECK: ccmn w3, w0, #15, hs
861 # CHECK: ccmn wzr, w15, #13, hs
866 # CHECK: ccmn x9, xzr, #0, le
867 # CHECK: ccmn x3, x0, #15, gt
868 # CHECK: ccmn xzr, x5, #7, ne
873 #------------------------------------------------------------------------------
874 # Conditional branch (immediate)
875 #------------------------------------------------------------------------------
876 # CHECK: csel w1, w0, w19, ne
877 # CHECK: csel wzr, w5, w9, eq
878 # CHECK: csel w9, wzr, w30, gt
879 # CHECK: csel w1, w28, wzr, mi
880 # CHECK: csel x19, x23, x29, lt
881 # CHECK: csel xzr, x3, x4, ge
882 # CHECK: csel x5, xzr, x6, hs
883 # CHECK: csel x7, x8, xzr, lo
893 # CHECK: csinc w1, w0, w19, ne
894 # CHECK: csinc wzr, w5, w9, eq
895 # CHECK: csinc w9, wzr, w30, gt
896 # CHECK: csinc w1, w28, wzr, mi
897 # CHECK: csinc x19, x23, x29, lt
898 # CHECK: csinc xzr, x3, x4, ge
899 # CHECK: csinc x5, xzr, x6, hs
900 # CHECK: csinc x7, x8, xzr, lo
910 # CHECK: csinv w1, w0, w19, ne
911 # CHECK: csinv wzr, w5, w9, eq
912 # CHECK: csinv w9, wzr, w30, gt
913 # CHECK: csinv w1, w28, wzr, mi
914 # CHECK: csinv x19, x23, x29, lt
915 # CHECK: csinv xzr, x3, x4, ge
916 # CHECK: csinv x5, xzr, x6, hs
917 # CHECK: csinv x7, x8, xzr, lo
927 # CHECK: csneg w1, w0, w19, ne
928 # CHECK: csneg wzr, w5, w9, eq
929 # CHECK: csneg w9, wzr, w30, gt
930 # CHECK: csneg w1, w28, wzr, mi
931 # CHECK: csneg x19, x23, x29, lt
932 # CHECK: csneg xzr, x3, x4, ge
933 # CHECK: csneg x5, xzr, x6, hs
934 # CHECK: csneg x7, x8, xzr, lo
944 # CHECK: csinc w3, wzr, wzr, ne
945 # CHECK: csinc x9, xzr, xzr, mi
946 # CHECK: csinv w20, wzr, wzr, eq
947 # CHECK: csinv x30, xzr, xzr, lt
953 # CHECK: csinc w3, w5, w5, le
954 # CHECK: csinc wzr, w4, w4, gt
955 # CHECK: csinc w9, wzr, wzr, ge
956 # CHECK: csinc x3, x5, x5, le
957 # CHECK: csinc xzr, x4, x4, gt
958 # CHECK: csinc x9, xzr, xzr, ge
966 # CHECK: csinv w3, w5, w5, le
967 # CHECK: csinv wzr, w4, w4, gt
968 # CHECK: csinv w9, wzr, wzr, ge
969 # CHECK: csinv x3, x5, x5, le
970 # CHECK: csinv xzr, x4, x4, gt
971 # CHECK: csinv x9, xzr, xzr, ge
979 # CHECK: csneg w3, w5, w5, le
980 # CHECK: csneg wzr, w4, w4, gt
981 # CHECK: csneg w9, wzr, wzr, ge
982 # CHECK: csneg x3, x5, x5, le
983 # CHECK: csneg xzr, x4, x4, gt
984 # CHECK: csneg x9, xzr, xzr, ge
992 #------------------------------------------------------------------------------
993 # Data-processing (1 source)
994 #------------------------------------------------------------------------------
997 # CHECK: rbit x18, x3
998 # CHECK: rev16 w17, w1
999 # CHECK: rev16 x5, x2
1000 # CHECK: rev w18, w0
1001 # CHECK: rev32 x20, x1
1009 # CHECK: rev x22, x2
1010 # CHECK: clz w24, w3
1011 # CHECK: clz x26, x4
1013 # CHECK: cls x20, x5
1020 #------------------------------------------------------------------------------
1021 # Data-processing (2 source)
1022 #------------------------------------------------------------------------------
1024 # CHECK: crc32b w5, w7, w20
1025 # CHECK: crc32h w28, wzr, w30
1026 # CHECK: crc32w w0, w1, w2
1027 # CHECK: crc32x w7, w9, x20
1028 # CHECK: crc32cb w9, w5, w4
1029 # CHECK: crc32ch w13, w17, w25
1030 # CHECK: crc32cw wzr, w3, w5
1031 # CHECK: crc32cx w18, w16, xzr
1041 # CHECK: udiv w0, w7, w10
1042 # CHECK: udiv x9, x22, x4
1043 # CHECK: sdiv w12, w21, w0
1044 # CHECK: sdiv x13, x2, x1
1045 # CHECK: lsl w11, w12, w13
1046 # CHECK: lsl x14, x15, x16
1047 # CHECK: lsr w17, w18, w19
1048 # CHECK: lsr x20, x21, x22
1049 # CHECK: asr w23, w24, w25
1050 # CHECK: asr x26, x27, x28
1051 # CHECK: ror w0, w1, w2
1052 # CHECK: ror x3, x4, x5
1066 # CHECK: lsl w6, w7, w8
1067 # CHECK: lsl x9, x10, x11
1068 # CHECK: lsr w12, w13, w14
1069 # CHECK: lsr x15, x16, x17
1070 # CHECK: asr w18, w19, w20
1071 # CHECK: asr x21, x22, x23
1072 # CHECK: ror w24, w25, w26
1073 # CHECK: ror x27, x28, x29
1083 #------------------------------------------------------------------------------
1084 # Data-processing (3 sources)
1085 #------------------------------------------------------------------------------
1087 # First check some non-canonical encodings where Ra is not 0b11111 (only umulh
1088 # and smulh have them).
1090 # CHECK: smulh x30, x29, x28
1091 # CHECK: smulh xzr, x27, x26
1092 # CHECK: umulh x30, x29, x28
1093 # CHECK: umulh x23, x30, xzr
1099 # Now onto the boilerplate stuff
1101 # CHECK: madd w1, w3, w7, w4
1102 # CHECK: madd wzr, w0, w9, w11
1103 # CHECK: madd w13, wzr, w4, w4
1104 # CHECK: madd w19, w30, wzr, w29
1105 # CHECK: mul w4, w5, w6
1112 # CHECK: madd x1, x3, x7, x4
1113 # CHECK: madd xzr, x0, x9, x11
1114 # CHECK: madd x13, xzr, x4, x4
1115 # CHECK: madd x19, x30, xzr, x29
1116 # CHECK: mul x4, x5, x6
1123 # CHECK: msub w1, w3, w7, w4
1124 # CHECK: msub wzr, w0, w9, w11
1125 # CHECK: msub w13, wzr, w4, w4
1126 # CHECK: msub w19, w30, wzr, w29
1127 # CHECK: mneg w4, w5, w6
1134 # CHECK: msub x1, x3, x7, x4
1135 # CHECK: msub xzr, x0, x9, x11
1136 # CHECK: msub x13, xzr, x4, x4
1137 # CHECK: msub x19, x30, xzr, x29
1138 # CHECK: mneg x4, x5, x6
1145 # CHECK: smaddl x3, w5, w2, x9
1146 # CHECK: smaddl xzr, w10, w11, x12
1147 # CHECK: smaddl x13, wzr, w14, x15
1148 # CHECK: smaddl x16, w17, wzr, x18
1149 # CHECK: smull x19, w20, w21
1156 # CHECK: smsubl x3, w5, w2, x9
1157 # CHECK: smsubl xzr, w10, w11, x12
1158 # CHECK: smsubl x13, wzr, w14, x15
1159 # CHECK: smsubl x16, w17, wzr, x18
1160 # CHECK: smnegl x19, w20, w21
1167 # CHECK: umaddl x3, w5, w2, x9
1168 # CHECK: umaddl xzr, w10, w11, x12
1169 # CHECK: umaddl x13, wzr, w14, x15
1170 # CHECK: umaddl x16, w17, wzr, x18
1171 # CHECK: umull x19, w20, w21
1178 # CHECK: umsubl x3, w5, w2, x9
1179 # CHECK: umsubl xzr, w10, w11, x12
1180 # CHECK: umsubl x13, wzr, w14, x15
1181 # CHECK: umsubl x16, w17, wzr, x18
1182 # CHECK: umnegl x19, w20, w21
1189 # CHECK: smulh x30, x29, x28
1190 # CHECK: smulh xzr, x27, x26
1191 # CHECK: smulh x25, xzr, x24
1192 # CHECK: smulh x23, x22, xzr
1198 # CHECK: umulh x30, x29, x28
1199 # CHECK: umulh xzr, x27, x26
1200 # CHECK: umulh x25, xzr, x24
1201 # CHECK: umulh x23, x22, xzr
1207 # CHECK: mul w3, w4, w5
1208 # CHECK: mul wzr, w6, w7
1209 # CHECK: mul w8, wzr, w9
1210 # CHECK: mul w10, w11, wzr
1211 # CHECK: mul x12, x13, x14
1212 # CHECK: mul xzr, x15, x16
1213 # CHECK: mul x17, xzr, x18
1214 # CHECK: mul x19, x20, xzr
1224 # CHECK: mneg w21, w22, w23
1225 # CHECK: mneg wzr, w24, w25
1226 # CHECK: mneg w26, wzr, w27
1227 # CHECK: mneg w28, w29, wzr
1233 # CHECK: smull x11, w13, w17
1234 # CHECK: umull x11, w13, w17
1235 # CHECK: smnegl x11, w13, w17
1236 # CHECK: umnegl x11, w13, w17
1242 #------------------------------------------------------------------------------
1243 # Exception generation
1244 #------------------------------------------------------------------------------
1247 # CHECK: svc #{{65535|0xffff}}
1251 # CHECK: hvc #{{1|0x1}}
1252 # CHECK: smc #{{12000|0x2ee0}}
1253 # CHECK: brk #{{12|0xc}}
1254 # CHECK: hlt #{{123|0x7b}}
1260 # CHECK: dcps1 #{{42|0x2a}}
1261 # CHECK: dcps2 #{{9|0x9}}
1262 # CHECK: dcps3 #{{1000|0x3e8}}
1274 #------------------------------------------------------------------------------
1275 # Extract (immediate)
1276 #------------------------------------------------------------------------------
1278 # CHECK: extr w3, w5, w7, #0
1279 # CHECK: extr w11, w13, w17, #31
1283 # CHECK: extr x3, x5, x7, #15
1284 # CHECK: extr x11, x13, x17, #63
1288 # CHECK: extr x19, x23, x23, #24
1289 # CHECK: extr x29, xzr, xzr, #63
1290 # CHECK: extr w9, w13, w13, #31
1295 #------------------------------------------------------------------------------
1296 # Floating-point compare
1297 #------------------------------------------------------------------------------
1299 # CHECK: fcmp s3, s5
1300 # CHECK: fcmp s31, #0.0
1301 # CHECK: fcmp s31, #0.0
1306 # CHECK: fcmpe s29, s30
1307 # CHECK: fcmpe s15, #0.0
1308 # CHECK: fcmpe s15, #0.0
1313 # CHECK: fcmp d4, d12
1314 # CHECK: fcmp d23, #0.0
1315 # CHECK: fcmp d23, #0.0
1320 # CHECK: fcmpe d26, d22
1321 # CHECK: fcmpe d29, #0.0
1322 # CHECK: fcmpe d29, #0.0
1327 #------------------------------------------------------------------------------
1328 # Floating-point conditional compare
1329 #------------------------------------------------------------------------------
1331 # CHECK: fccmp s1, s31, #0, eq
1332 # CHECK: fccmp s3, s0, #15, hs
1333 # CHECK: fccmp s31, s15, #13, hs
1338 # CHECK: fccmp d9, d31, #0, le
1339 # CHECK: fccmp d3, d0, #15, gt
1340 # CHECK: fccmp d31, d5, #7, ne
1345 # CHECK: fccmpe s1, s31, #0, eq
1346 # CHECK: fccmpe s3, s0, #15, hs
1347 # CHECK: fccmpe s31, s15, #13, hs
1352 # CHECK: fccmpe d9, d31, #0, le
1353 # CHECK: fccmpe d3, d0, #15, gt
1354 # CHECK: fccmpe d31, d5, #7, ne
1359 #-------------------------------------------------------------------------------
1360 # Floating-point conditional compare
1361 #-------------------------------------------------------------------------------
1363 # CHECK: fcsel s3, s20, s9, pl
1364 # CHECK: fcsel d9, d10, d11, mi
1368 #------------------------------------------------------------------------------
1369 # Floating-point data-processing (1 source)
1370 #------------------------------------------------------------------------------
1372 # CHECK: fmov s0, s1
1373 # CHECK: fabs s2, s3
1374 # CHECK: fneg s4, s5
1375 # CHECK: fsqrt s6, s7
1376 # CHECK: fcvt d8, s9
1377 # CHECK: fcvt h10, s11
1378 # CHECK: frintn s12, s13
1379 # CHECK: frintp s14, s15
1380 # CHECK: frintm s16, s17
1381 # CHECK: frintz s18, s19
1382 # CHECK: frinta s20, s21
1383 # CHECK: frintx s22, s23
1384 # CHECK: frinti s24, s25
1399 # CHECK: fmov d0, d1
1400 # CHECK: fabs d2, d3
1401 # CHECK: fneg d4, d5
1402 # CHECK: fsqrt d6, d7
1403 # CHECK: fcvt s8, d9
1404 # CHECK: fcvt h10, d11
1405 # CHECK: frintn d12, d13
1406 # CHECK: frintp d14, d15
1407 # CHECK: frintm d16, d17
1408 # CHECK: frintz d18, d19
1409 # CHECK: frinta d20, d21
1410 # CHECK: frintx d22, d23
1411 # CHECK: frinti d24, d25
1426 # CHECK: fcvt s26, h27
1427 # CHECK: fcvt d28, h29
1431 #------------------------------------------------------------------------------
1432 # Floating-point data-processing (2 sources)
1433 #------------------------------------------------------------------------------
1435 # CHECK: fmul s20, s19, s17
1436 # CHECK: fdiv s1, s2, s3
1437 # CHECK: fadd s4, s5, s6
1438 # CHECK: fsub s7, s8, s9
1439 # CHECK: fmax s10, s11, s12
1440 # CHECK: fmin s13, s14, s15
1441 # CHECK: fmaxnm s16, s17, s18
1442 # CHECK: fminnm s19, s20, s21
1443 # CHECK: fnmul s22, s23, s2
1455 # CHECK: fmul d20, d19, d17
1456 # CHECK: fdiv d1, d2, d3
1457 # CHECK: fadd d4, d5, d6
1458 # CHECK: fsub d7, d8, d9
1459 # CHECK: fmax d10, d11, d12
1460 # CHECK: fmin d13, d14, d15
1461 # CHECK: fmaxnm d16, d17, d18
1462 # CHECK: fminnm d19, d20, d21
1463 # CHECK: fnmul d22, d23, d24
1474 #------------------------------------------------------------------------------
1475 # Floating-point data-processing (1 source)
1476 #------------------------------------------------------------------------------
1478 # CHECK: fmadd s3, s5, s6, s31
1479 # CHECK: fmadd d3, d13, d0, d23
1480 # CHECK: fmsub s3, s5, s6, s31
1481 # CHECK: fmsub d3, d13, d0, d23
1482 # CHECK: fnmadd s3, s5, s6, s31
1483 # CHECK: fnmadd d3, d13, d0, d23
1484 # CHECK: fnmsub s3, s5, s6, s31
1485 # CHECK: fnmsub d3, d13, d0, d23
1495 #------------------------------------------------------------------------------
1496 # Floating-point <-> fixed-point conversion
1497 #------------------------------------------------------------------------------
1499 # CHECK: fcvtzs w3, s5, #1
1500 # CHECK: fcvtzs wzr, s20, #13
1501 # CHECK: fcvtzs w19, s0, #32
1506 # CHECK: fcvtzs x3, s5, #1
1507 # CHECK: fcvtzs x12, s30, #45
1508 # CHECK: fcvtzs x19, s0, #64
1513 # CHECK: fcvtzs w3, d5, #1
1514 # CHECK: fcvtzs wzr, d20, #13
1515 # CHECK: fcvtzs w19, d0, #32
1520 # CHECK: fcvtzs x3, d5, #1
1521 # CHECK: fcvtzs x12, d30, #45
1522 # CHECK: fcvtzs x19, d0, #64
1527 # CHECK: fcvtzu w3, s5, #1
1528 # CHECK: fcvtzu wzr, s20, #13
1529 # CHECK: fcvtzu w19, s0, #32
1534 # CHECK: fcvtzu x3, s5, #1
1535 # CHECK: fcvtzu x12, s30, #45
1536 # CHECK: fcvtzu x19, s0, #64
1541 # CHECK: fcvtzu w3, d5, #1
1542 # CHECK: fcvtzu wzr, d20, #13
1543 # CHECK: fcvtzu w19, d0, #32
1548 # CHECK: fcvtzu x3, d5, #1
1549 # CHECK: fcvtzu x12, d30, #45
1550 # CHECK: fcvtzu x19, d0, #64
1555 # CHECK: scvtf s23, w19, #1
1556 # CHECK: scvtf s31, wzr, #20
1557 # CHECK: scvtf s14, w0, #32
1562 # CHECK: scvtf s23, x19, #1
1563 # CHECK: scvtf s31, xzr, #20
1564 # CHECK: scvtf s14, x0, #64
1569 # CHECK: scvtf d23, w19, #1
1570 # CHECK: scvtf d31, wzr, #20
1571 # CHECK: scvtf d14, w0, #32
1576 # CHECK: scvtf d23, x19, #1
1577 # CHECK: scvtf d31, xzr, #20
1578 # CHECK: scvtf d14, x0, #64
1583 # CHECK: ucvtf s23, w19, #1
1584 # CHECK: ucvtf s31, wzr, #20
1585 # CHECK: ucvtf s14, w0, #32
1590 # CHECK: ucvtf s23, x19, #1
1591 # CHECK: ucvtf s31, xzr, #20
1592 # CHECK: ucvtf s14, x0, #64
1597 # CHECK: ucvtf d23, w19, #1
1598 # CHECK: ucvtf d31, wzr, #20
1599 # CHECK: ucvtf d14, w0, #32
1604 # CHECK: ucvtf d23, x19, #1
1605 # CHECK: ucvtf d31, xzr, #20
1606 # CHECK: ucvtf d14, x0, #64
1611 #------------------------------------------------------------------------------
1612 # Floating-point <-> integer conversion
1613 #------------------------------------------------------------------------------
1614 # CHECK: fcvtns w3, s31
1615 # CHECK: fcvtns xzr, s12
1616 # CHECK: fcvtnu wzr, s12
1617 # CHECK: fcvtnu x0, s0
1623 # CHECK: fcvtps wzr, s9
1624 # CHECK: fcvtps x12, s20
1625 # CHECK: fcvtpu w30, s23
1626 # CHECK: fcvtpu x29, s3
1632 # CHECK: fcvtms w2, s3
1633 # CHECK: fcvtms x4, s5
1634 # CHECK: fcvtmu w6, s7
1635 # CHECK: fcvtmu x8, s9
1641 # CHECK: fcvtzs w10, s11
1642 # CHECK: fcvtzs x12, s13
1643 # CHECK: fcvtzu w14, s15
1644 # CHECK: fcvtzu x15, s16
1650 # CHECK: scvtf s17, w18
1651 # CHECK: scvtf s19, x20
1652 # CHECK: ucvtf s21, w22
1653 # CHECK: scvtf s23, x24
1659 # CHECK: fcvtas w25, s26
1660 # CHECK: fcvtas x27, s28
1661 # CHECK: fcvtau w29, s30
1662 # CHECK: fcvtau xzr, s0
1668 # CHECK: fcvtns w3, d31
1669 # CHECK: fcvtns xzr, d12
1670 # CHECK: fcvtnu wzr, d12
1671 # CHECK: fcvtnu x0, d0
1677 # CHECK: fcvtps wzr, d9
1678 # CHECK: fcvtps x12, d20
1679 # CHECK: fcvtpu w30, d23
1680 # CHECK: fcvtpu x29, d3
1686 # CHECK: fcvtms w2, d3
1687 # CHECK: fcvtms x4, d5
1688 # CHECK: fcvtmu w6, d7
1689 # CHECK: fcvtmu x8, d9
1695 # CHECK: fcvtzs w10, d11
1696 # CHECK: fcvtzs x12, d13
1697 # CHECK: fcvtzu w14, d15
1698 # CHECK: fcvtzu x15, d16
1704 # CHECK: scvtf d17, w18
1705 # CHECK: scvtf d19, x20
1706 # CHECK: ucvtf d21, w22
1707 # CHECK: ucvtf d23, x24
1713 # CHECK: fcvtas w25, d26
1714 # CHECK: fcvtas x27, d28
1715 # CHECK: fcvtau w29, d30
1716 # CHECK: fcvtau xzr, d0
1722 # CHECK: fmov w3, s9
1723 # CHECK: fmov s9, w3
1727 # CHECK: fmov x20, d31
1728 # CHECK: fmov d1, x15
1732 # CHECK: fmov x3, v12.d[1]
1733 # CHECK: fmov v1.d[1], x19
1737 #------------------------------------------------------------------------------
1738 # Floating-point immediate
1739 #------------------------------------------------------------------------------
1741 # CHECK: fmov s2, #0.12500000
1742 # CHECK: fmov s3, #1.00000000
1743 # CHECK: fmov d30, #16.00000000
1748 # CHECK: fmov s4, #1.06250000
1749 # CHECK: fmov d10, #1.93750000
1753 # CHECK: fmov s12, #-1.00000000
1756 # CHECK: fmov d16, #8.50000000
1759 #------------------------------------------------------------------------------
1760 # Load-register (literal)
1761 #------------------------------------------------------------------------------
1764 # CHECK: ldr x29, #4
1765 # CHECK: ldrsw xzr, #-4
1771 # CHECK: ldr d0, #1048572
1772 # CHECK: ldr q0, #-1048576
1777 # CHECK: prfm pldl1strm, #0
1778 # CHECK: prfm #22, #0
1782 #------------------------------------------------------------------------------
1783 # Load/store exclusive
1784 #------------------------------------------------------------------------------
1786 #CHECK: stxrb w18, w8, [sp]
1787 #CHECK: stxrh w24, w15, [x16]
1788 #CHECK: stxr w5, w6, [x17]
1789 #CHECK: stxr w1, x10, [x21]
1790 #CHECK: stxr w1, x10, [x21]
1797 #CHECK: ldxrb w30, [x0]
1798 #CHECK: ldxrh w17, [x4]
1799 #CHECK: ldxr w22, [sp]
1800 #CHECK: ldxr x11, [x29]
1801 #CHECK: ldxr x11, [x29]
1802 #CHECK: ldxr x11, [x29]
1810 #CHECK: stxp w12, w11, w10, [sp]
1811 #CHECK: stxp wzr, x27, x9, [x12]
1815 #CHECK: ldxp w0, wzr, [sp]
1816 #CHECK: ldxp x17, x0, [x18]
1817 #CHECK: ldxp x17, x0, [x18]
1822 #CHECK: stlxrb w12, w22, [x0]
1823 #CHECK: stlxrh w10, w1, [x1]
1824 #CHECK: stlxr w9, w2, [x2]
1825 #CHECK: stlxr w9, x3, [sp]
1832 #CHECK: ldaxrb w8, [x4]
1833 #CHECK: ldaxrh w7, [x5]
1834 #CHECK: ldaxr w6, [sp]
1835 #CHECK: ldaxr x5, [x6]
1836 #CHECK: ldaxr x5, [x6]
1837 #CHECK: ldaxr x5, [x6]
1845 #CHECK: stlxp w4, w5, w6, [sp]
1846 #CHECK: stlxp wzr, x6, x7, [x1]
1850 #CHECK: ldaxp w5, w18, [sp]
1851 #CHECK: ldaxp x6, x19, [x22]
1852 #CHECK: ldaxp x6, x19, [x22]
1857 #CHECK: stlrb w24, [sp]
1858 #CHECK: stlrh w25, [x30]
1859 #CHECK: stlr w26, [x29]
1860 #CHECK: stlr x27, [x28]
1861 #CHECK: stlr x27, [x28]
1862 #CHECK: stlr x27, [x28]
1870 #CHECK: ldarb w23, [sp]
1871 #CHECK: ldarh w22, [x30]
1872 #CHECK: ldar wzr, [x29]
1873 #CHECK: ldar x21, [x28]
1874 #CHECK: ldar x21, [x28]
1875 #CHECK: ldar x21, [x28]
1883 #------------------------------------------------------------------------------
1884 # Load/store (unscaled immediate)
1885 #------------------------------------------------------------------------------
1887 # CHECK: sturb w9, [sp]
1888 # CHECK: sturh wzr, [x12, #255]
1889 # CHECK: stur w16, [x0, #-256]
1890 # CHECK: stur x28, [x14, #1]
1896 # CHECK: ldurb w1, [x20, #255]
1897 # CHECK: ldurh w20, [x1, #255]
1898 # CHECK: ldur w12, [sp, #255]
1899 # CHECK: ldur xzr, [x12, #255]
1905 # CHECK: ldursb x9, [x7, #-256]
1906 # CHECK: ldursh x17, [x19, #-256]
1907 # CHECK: ldursw x20, [x15, #-256]
1908 # CHECK: prfum pldl2keep, [sp, #-256]
1909 # CHECK: ldursb w19, [x1, #-256]
1910 # CHECK: ldursh w15, [x21, #-256]
1918 # CHECK: stur b0, [sp, #1]
1919 # CHECK: stur h12, [x12, #-1]
1920 # CHECK: stur s15, [x0, #255]
1921 # CHECK: stur d31, [x5, #25]
1922 # CHECK: stur q9, [x5]
1929 # CHECK: ldur b3, [sp]
1930 # CHECK: ldur h5, [x4, #-256]
1931 # CHECK: ldur s7, [x12, #-1]
1932 # CHECK: ldur d11, [x19, #4]
1933 # CHECK: ldur q13, [x1, #2]
1940 #------------------------------------------------------------------------------
1941 # Load/store (immediate post-indexed)
1942 #------------------------------------------------------------------------------
1944 # E.g. "str xzr, [sp], #4" is *not* unpredictable
1945 # CHECK-NOT: warning: potentially undefined instruction encoding
1948 # CHECK: strb w9, [x2], #255
1949 # CHECK: strb w10, [x3], #1
1950 # CHECK: strb w10, [x3], #-256
1951 # CHECK: strh w9, [x2], #255
1952 # CHECK: strh w9, [x2], #1
1953 # CHECK: strh w10, [x3], #-256
1961 # CHECK: str w19, [sp], #255
1962 # CHECK: str w20, [x30], #1
1963 # CHECK: str w21, [x12], #-256
1964 # CHECK: str xzr, [x9], #255
1965 # CHECK: str x2, [x3], #1
1966 # CHECK: str x19, [x12], #-256
1974 # CHECK: ldrb w9, [x2], #255
1975 # CHECK: ldrb w10, [x3], #1
1976 # CHECK: ldrb w10, [x3], #-256
1977 # CHECK: ldrh w9, [x2], #255
1978 # CHECK: ldrh w9, [x2], #1
1979 # CHECK: ldrh w10, [x3], #-256
1987 # CHECK: ldr w19, [sp], #255
1988 # CHECK: ldr w20, [x30], #1
1989 # CHECK: ldr w21, [x12], #-256
1990 # CHECK: ldr xzr, [x9], #255
1991 # CHECK: ldr x2, [x3], #1
1992 # CHECK: ldr x19, [x12], #-256
2000 # CHECK: ldrsb xzr, [x9], #255
2001 # CHECK: ldrsb x2, [x3], #1
2002 # CHECK: ldrsb x19, [x12], #-256
2003 # CHECK: ldrsh xzr, [x9], #255
2004 # CHECK: ldrsh x2, [x3], #1
2005 # CHECK: ldrsh x19, [x12], #-256
2006 # CHECK: ldrsw xzr, [x9], #255
2007 # CHECK: ldrsw x2, [x3], #1
2008 # CHECK: ldrsw x19, [x12], #-256
2019 # CHECK: ldrsb wzr, [x9], #255
2020 # CHECK: ldrsb w2, [x3], #1
2021 # CHECK: ldrsb w19, [x12], #-256
2022 # CHECK: ldrsh wzr, [x9], #255
2023 # CHECK: ldrsh w2, [x3], #1
2024 # CHECK: ldrsh w19, [x12], #-256
2032 # CHECK: str b0, [x0], #255
2033 # CHECK: str b3, [x3], #1
2034 # CHECK: str b5, [sp], #-256
2035 # CHECK: str h10, [x10], #255
2036 # CHECK: str h13, [x23], #1
2037 # CHECK: str h15, [sp], #-256
2038 # CHECK: str s20, [x20], #255
2039 # CHECK: str s23, [x23], #1
2040 # CHECK: str s25, [x0], #-256
2041 # CHECK: str d20, [x20], #255
2042 # CHECK: str d23, [x23], #1
2043 # CHECK: str d25, [x0], #-256
2057 # CHECK: ldr b0, [x0], #255
2058 # CHECK: ldr b3, [x3], #1
2059 # CHECK: ldr b5, [sp], #-256
2060 # CHECK: ldr h10, [x10], #255
2061 # CHECK: ldr h13, [x23], #1
2062 # CHECK: ldr h15, [sp], #-256
2063 # CHECK: ldr s20, [x20], #255
2064 # CHECK: ldr s23, [x23], #1
2065 # CHECK: ldr s25, [x0], #-256
2066 # CHECK: ldr d20, [x20], #255
2067 # CHECK: ldr d23, [x23], #1
2068 # CHECK: ldr d25, [x0], #-256
2083 # CHECK: ldr q20, [x1], #255
2084 # CHECK: ldr q23, [x9], #1
2085 # CHECK: ldr q25, [x20], #-256
2086 # CHECK: str q10, [x1], #255
2087 # CHECK: str q22, [sp], #1
2088 # CHECK: str q21, [x20], #-256
2095 #-------------------------------------------------------------------------------
2096 # Load-store register (immediate pre-indexed)
2097 #-------------------------------------------------------------------------------
2099 # E.g. "str xzr, [sp, #4]!" is *not* unpredictable
2100 # CHECK-NOT: warning: potentially undefined instruction encoding
2103 # CHECK: ldr x3, [x4, #0]!
2106 # CHECK: strb w9, [x2, #255]!
2107 # CHECK: strb w10, [x3, #1]!
2108 # CHECK: strb w10, [x3, #-256]!
2109 # CHECK: strh w9, [x2, #255]!
2110 # CHECK: strh w9, [x2, #1]!
2111 # CHECK: strh w10, [x3, #-256]!
2119 # CHECK: str w19, [sp, #255]!
2120 # CHECK: str w20, [x30, #1]!
2121 # CHECK: str w21, [x12, #-256]!
2122 # CHECK: str xzr, [x9, #255]!
2123 # CHECK: str x2, [x3, #1]!
2124 # CHECK: str x19, [x12, #-256]!
2132 # CHECK: ldrb w9, [x2, #255]!
2133 # CHECK: ldrb w10, [x3, #1]!
2134 # CHECK: ldrb w10, [x3, #-256]!
2135 # CHECK: ldrh w9, [x2, #255]!
2136 # CHECK: ldrh w9, [x2, #1]!
2137 # CHECK: ldrh w10, [x3, #-256]!
2145 # CHECK: ldr w19, [sp, #255]!
2146 # CHECK: ldr w20, [x30, #1]!
2147 # CHECK: ldr w21, [x12, #-256]!
2148 # CHECK: ldr xzr, [x9, #255]!
2149 # CHECK: ldr x2, [x3, #1]!
2150 # CHECK: ldr x19, [x12, #-256]!
2158 # CHECK: ldrsb xzr, [x9, #255]!
2159 # CHECK: ldrsb x2, [x3, #1]!
2160 # CHECK: ldrsb x19, [x12, #-256]!
2161 # CHECK: ldrsh xzr, [x9, #255]!
2162 # CHECK: ldrsh x2, [x3, #1]!
2163 # CHECK: ldrsh x19, [x12, #-256]!
2164 # CHECK: ldrsw xzr, [x9, #255]!
2165 # CHECK: ldrsw x2, [x3, #1]!
2166 # CHECK: ldrsw x19, [x12, #-256]!
2177 # CHECK: ldrsb wzr, [x9, #255]!
2178 # CHECK: ldrsb w2, [x3, #1]!
2179 # CHECK: ldrsb w19, [x12, #-256]!
2180 # CHECK: ldrsh wzr, [x9, #255]!
2181 # CHECK: ldrsh w2, [x3, #1]!
2182 # CHECK: ldrsh w19, [x12, #-256]!
2190 # CHECK: str b0, [x0, #255]!
2191 # CHECK: str b3, [x3, #1]!
2192 # CHECK: str b5, [sp, #-256]!
2193 # CHECK: str h10, [x10, #255]!
2194 # CHECK: str h13, [x23, #1]!
2195 # CHECK: str h15, [sp, #-256]!
2196 # CHECK: str s20, [x20, #255]!
2197 # CHECK: str s23, [x23, #1]!
2198 # CHECK: str s25, [x0, #-256]!
2199 # CHECK: str d20, [x20, #255]!
2200 # CHECK: str d23, [x23, #1]!
2201 # CHECK: str d25, [x0, #-256]!
2215 # CHECK: ldr b0, [x0, #255]!
2216 # CHECK: ldr b3, [x3, #1]!
2217 # CHECK: ldr b5, [sp, #-256]!
2218 # CHECK: ldr h10, [x10, #255]!
2219 # CHECK: ldr h13, [x23, #1]!
2220 # CHECK: ldr h15, [sp, #-256]!
2221 # CHECK: ldr s20, [x20, #255]!
2222 # CHECK: ldr s23, [x23, #1]!
2223 # CHECK: ldr s25, [x0, #-256]!
2224 # CHECK: ldr d20, [x20, #255]!
2225 # CHECK: ldr d23, [x23, #1]!
2226 # CHECK: ldr d25, [x0, #-256]!
2240 # CHECK: ldr q20, [x1, #255]!
2241 # CHECK: ldr q23, [x9, #1]!
2242 # CHECK: ldr q25, [x20, #-256]!
2243 # CHECK: str q10, [x1, #255]!
2244 # CHECK: str q22, [sp, #1]!
2245 # CHECK: str q21, [x20, #-256]!
2253 #------------------------------------------------------------------------------
2254 # Load/store (unprivileged)
2255 #------------------------------------------------------------------------------
2257 # CHECK: sttrb w9, [sp]
2258 # CHECK: sttrh wzr, [x12, #255]
2259 # CHECK: sttr w16, [x0, #-256]
2260 # CHECK: sttr x28, [x14, #1]
2266 # CHECK: ldtrb w1, [x20, #255]
2267 # CHECK: ldtrh w20, [x1, #255]
2268 # CHECK: ldtr w12, [sp, #255]
2269 # CHECK: ldtr xzr, [x12, #255]
2275 # CHECK: ldtrsb x9, [x7, #-256]
2276 # CHECK: ldtrsh x17, [x19, #-256]
2277 # CHECK: ldtrsw x20, [x15, #-256]
2278 # CHECK: ldtrsb w19, [x1, #-256]
2279 # CHECK: ldtrsh w15, [x21, #-256]
2286 #------------------------------------------------------------------------------
2287 # Load/store (unsigned immediate)
2288 #------------------------------------------------------------------------------
2290 # CHECK: ldr x0, [x0]
2291 # CHECK: ldr x4, [x29]
2292 # CHECK: ldr x30, [x12, #32760]
2293 # CHECK: ldr x20, [sp, #8]
2299 # CHECK: ldr xzr, [sp]
2302 # CHECK: ldr w2, [sp]
2303 # CHECK: ldr w17, [sp, #16380]
2304 # CHECK: ldr w13, [x2, #4]
2309 # CHECK: ldrsw x2, [x5, #4]
2310 # CHECK: ldrsw x23, [sp, #16380]
2314 # CHECK: ldrh w2, [x4]
2315 # CHECK: ldrsh w23, [x6, #8190]
2316 # CHECK: ldrsh wzr, [sp, #2]
2317 # CHECK: ldrsh x29, [x2, #2]
2323 # CHECK: ldrb w26, [x3, #121]
2324 # CHECK: ldrb w12, [x2]
2325 # CHECK: ldrsb w27, [sp, #4095]
2326 # CHECK: ldrsb xzr, [x15]
2332 # CHECK: str x30, [sp]
2333 # CHECK: str w20, [x4, #16380]
2334 # CHECK: strh w20, [x10, #14]
2335 # CHECK: strh w17, [sp, #8190]
2336 # CHECK: strb w23, [x3, #4095]
2337 # CHECK: strb wzr, [x2]
2345 # CHECK: ldr b31, [sp, #4095]
2346 # CHECK: ldr h20, [x2, #8190]
2347 # CHECK: ldr s10, [x19, #16380]
2348 # CHECK: ldr d3, [x10, #32760]
2349 # CHECK: str q12, [sp, #65520]
2356 # CHECK: prfm pldl1keep, [sp, #8]
2357 # CHECK: prfm pldl1strm, [x3{{(, #0)?}}]
2358 # CHECK: prfm pldl2keep, [x5, #16]
2359 # CHECK: prfm pldl2strm, [x2{{(, #0)?}}]
2360 # CHECK: prfm pldl3keep, [x5{{(, #0)?}}]
2361 # CHECK: prfm pldl3strm, [x6{{(, #0)?}}]
2362 # CHECK: prfm plil1keep, [sp, #8]
2363 # CHECK: prfm plil1strm, [x3{{(, #0)?}}]
2364 # CHECK: prfm plil2keep, [x5, #16]
2365 # CHECK: prfm plil2strm, [x2{{(, #0)?}}]
2366 # CHECK: prfm plil3keep, [x5{{(, #0)?}}]
2367 # CHECK: prfm plil3strm, [x6{{(, #0)?}}]
2368 # CHECK: prfm pstl1keep, [sp, #8]
2369 # CHECK: prfm pstl1strm, [x3{{(, #0)?}}]
2370 # CHECK: prfm pstl2keep, [x5, #16]
2371 # CHECK: prfm pstl2strm, [x2{{(, #0)?}}]
2372 # CHECK: prfm pstl3keep, [x5{{(, #0)?}}]
2373 # CHECK: prfm pstl3strm, [x6{{(, #0)?}}]
2394 #------------------------------------------------------------------------------
2395 # Load/store (register offset)
2396 #------------------------------------------------------------------------------
2398 # CHECK: ldrb w3, [sp, x5]
2399 # CHECK: ldrb w9, [x27, x6]
2400 # CHECK: ldrsb w10, [x30, x7]
2401 # CHECK: ldrb w11, [x29, x3, sxtx]
2402 # CHECK: strb w12, [x28, xzr, sxtx]
2403 # CHECK: ldrb w14, [x26, w6, uxtw]
2404 # CHECK: ldrsb w15, [x25, w7, uxtw]
2405 # CHECK: ldrb w17, [x23, w9, sxtw]
2406 # CHECK: ldrsb x18, [x22, w10, sxtw]
2417 # CHECK: ldrsh w3, [sp, x5]
2418 # CHECK: ldrsh w9, [x27, x6]
2419 # CHECK: ldrh w10, [x30, x7, lsl #1]
2420 # CHECK: strh w11, [x29, x3, sxtx]
2421 # CHECK: ldrh w12, [x28, xzr, sxtx]
2422 # CHECK: ldrsh x13, [x27, x5, sxtx #1]
2423 # CHECK: ldrh w14, [x26, w6, uxtw]
2424 # CHECK: ldrh w15, [x25, w7, uxtw]
2425 # CHECK: ldrsh w16, [x24, w8, uxtw #1]
2426 # CHECK: ldrh w17, [x23, w9, sxtw]
2427 # CHECK: ldrh w18, [x22, w10, sxtw]
2428 # CHECK: strh w19, [x21, wzr, sxtw #1]
2442 # CHECK: ldr w3, [sp, x5]
2443 # CHECK: ldr s9, [x27, x6]
2444 # CHECK: ldr w10, [x30, x7, lsl #2]
2445 # CHECK: ldr w11, [x29, x3, sxtx]
2446 # CHECK: str s12, [x28, xzr, sxtx]
2447 # CHECK: str w13, [x27, x5, sxtx #2]
2448 # CHECK: str w14, [x26, w6, uxtw]
2449 # CHECK: ldr w15, [x25, w7, uxtw]
2450 # CHECK: ldr w16, [x24, w8, uxtw #2]
2451 # CHECK: ldrsw x17, [x23, w9, sxtw]
2452 # CHECK: ldr w18, [x22, w10, sxtw]
2453 # CHECK: ldrsw x19, [x21, wzr, sxtw #2]
2467 # CHECK: ldr x3, [sp, x5]
2468 # CHECK: str x9, [x27, x6]
2469 # CHECK: ldr d10, [x30, x7, lsl #3]
2470 # CHECK: str x11, [x29, x3, sxtx]
2471 # CHECK: ldr x12, [x28, xzr, sxtx]
2472 # CHECK: ldr x13, [x27, x5, sxtx #3]
2473 # CHECK: prfm pldl1keep, [x26, w6, uxtw]
2474 # CHECK: ldr x15, [x25, w7, uxtw]
2475 # CHECK: ldr x16, [x24, w8, uxtw #3]
2476 # CHECK: ldr x17, [x23, w9, sxtw]
2477 # CHECK: ldr x18, [x22, w10, sxtw]
2478 # CHECK: str d19, [x21, wzr, sxtw #3]
2492 # CHECK: ldr q3, [sp, x5]
2493 # CHECK: ldr q9, [x27, x6]
2494 # CHECK: ldr q10, [x30, x7, lsl #4]
2495 # CHECK: str q11, [x29, x3, sxtx]
2496 # CHECK: str q12, [x28, xzr, sxtx]
2497 # CHECK: str q13, [x27, x5, sxtx #4]
2498 # CHECK: ldr q14, [x26, w6, uxtw]
2499 # CHECK: ldr q15, [x25, w7, uxtw]
2500 # CHECK: ldr q16, [x24, w8, uxtw #4]
2501 # CHECK: ldr q17, [x23, w9, sxtw]
2502 # CHECK: str q18, [x22, w10, sxtw]
2503 # CHECK: ldr q19, [x21, wzr, sxtw #4]
2517 #------------------------------------------------------------------------------
2518 # Load/store register pair (offset)
2519 #------------------------------------------------------------------------------
2521 # CHECK: ldp w3, w5, [sp]
2522 # CHECK: stp wzr, w9, [sp, #252]
2523 # CHECK: ldp w2, wzr, [sp, #-256]
2524 # CHECK: ldp w9, w10, [sp, #4]
2530 # CHECK: ldpsw x9, x10, [sp, #4]
2531 # CHECK: ldpsw x9, x10, [x2, #-256]
2532 # CHECK: ldpsw x20, x30, [sp, #252]
2537 # CHECK: ldp x21, x29, [x2, #504]
2538 # CHECK: ldp x22, x23, [x3, #-512]
2539 # CHECK: ldp x24, x25, [x4, #8]
2544 # CHECK: ldp s29, s28, [sp, #252]
2545 # CHECK: stp s27, s26, [sp, #-256]
2546 # CHECK: ldp s1, s2, [x3, #44]
2551 # CHECK: stp d3, d5, [x9, #504]
2552 # CHECK: stp d7, d11, [x10, #-512]
2553 # CHECK: ldp d2, d3, [x30, #-8]
2558 # CHECK: stp q3, q5, [sp]
2559 # CHECK: stp q17, q19, [sp, #1008]
2560 # CHECK: ldp q23, q29, [x1, #-1024]
2565 #------------------------------------------------------------------------------
2566 # Load/store register pair (post-indexed)
2567 #------------------------------------------------------------------------------
2569 # CHECK: ldp w3, w5, [sp], #0
2570 # CHECK: stp wzr, w9, [sp], #252
2571 # CHECK: ldp w2, wzr, [sp], #-256
2572 # CHECK: ldp w9, w10, [sp], #4
2578 # CHECK: ldpsw x9, x10, [sp], #4
2579 # CHECK: ldpsw x9, x10, [x2], #-256
2580 # CHECK: ldpsw x20, x30, [sp], #252
2585 # CHECK: ldp x21, x29, [x2], #504
2586 # CHECK: ldp x22, x23, [x3], #-512
2587 # CHECK: ldp x24, x25, [x4], #8
2592 # CHECK: ldp s29, s28, [sp], #252
2593 # CHECK: stp s27, s26, [sp], #-256
2594 # CHECK: ldp s1, s2, [x3], #44
2599 # CHECK: stp d3, d5, [x9], #504
2600 # CHECK: stp d7, d11, [x10], #-512
2601 # CHECK: ldp d2, d3, [x30], #-8
2606 # CHECK: stp q3, q5, [sp], #0
2607 # CHECK: stp q17, q19, [sp], #1008
2608 # CHECK: ldp q23, q29, [x1], #-1024
2613 #------------------------------------------------------------------------------
2614 # Load/store register pair (pre-indexed)
2615 #------------------------------------------------------------------------------
2617 # CHECK: ldp w3, w5, [sp, #0]!
2618 # CHECK: stp wzr, w9, [sp, #252]!
2619 # CHECK: ldp w2, wzr, [sp, #-256]!
2620 # CHECK: ldp w9, w10, [sp, #4]!
2626 # CHECK: ldpsw x9, x10, [sp, #4]!
2627 # CHECK: ldpsw x9, x10, [x2, #-256]!
2628 # CHECK: ldpsw x20, x30, [sp, #252]!
2633 # CHECK: ldp x21, x29, [x2, #504]!
2634 # CHECK: ldp x22, x23, [x3, #-512]!
2635 # CHECK: ldp x24, x25, [x4, #8]!
2640 # CHECK: ldp s29, s28, [sp, #252]!
2641 # CHECK: stp s27, s26, [sp, #-256]!
2642 # CHECK: ldp s1, s2, [x3, #44]!
2647 # CHECK: stp d3, d5, [x9, #504]!
2648 # CHECK: stp d7, d11, [x10, #-512]!
2649 # CHECK: ldp d2, d3, [x30, #-8]!
2654 # CHECK: stp q3, q5, [sp, #0]!
2655 # CHECK: stp q17, q19, [sp, #1008]!
2656 # CHECK: ldp q23, q29, [x1, #-1024]!
2661 #------------------------------------------------------------------------------
2662 # Load/store register pair (offset)
2663 #------------------------------------------------------------------------------
2665 # CHECK: ldnp w3, w5, [sp]
2666 # CHECK: stnp wzr, w9, [sp, #252]
2667 # CHECK: ldnp w2, wzr, [sp, #-256]
2668 # CHECK: ldnp w9, w10, [sp, #4]
2674 # CHECK: ldnp x21, x29, [x2, #504]
2675 # CHECK: ldnp x22, x23, [x3, #-512]
2676 # CHECK: ldnp x24, x25, [x4, #8]
2681 # CHECK: ldnp s29, s28, [sp, #252]
2682 # CHECK: stnp s27, s26, [sp, #-256]
2683 # CHECK: ldnp s1, s2, [x3, #44]
2688 # CHECK: stnp d3, d5, [x9, #504]
2689 # CHECK: stnp d7, d11, [x10, #-512]
2690 # CHECK: ldnp d2, d3, [x30, #-8]
2695 # CHECK: stnp q3, q5, [sp]
2696 # CHECK: stnp q17, q19, [sp, #1008]
2697 # CHECK: ldnp q23, q29, [x1, #-1024]
2702 #------------------------------------------------------------------------------
2703 # Logical (immediate)
2704 #------------------------------------------------------------------------------
2705 # CHECK: orr w3, w9, #0xffff0000
2706 # CHECK: orr wsp, w10, #0xe00000ff
2707 # CHECK: orr w9, w10, #0x3ff
2712 # CHECK: and w14, w15, #0x80008000
2713 # CHECK: and w12, w13, #0xffc3ffc3
2714 # CHECK: and w11, wzr, #0x30003
2719 # CHECK: eor w3, w6, #0xe0e0e0e0
2720 # CHECK: eor wsp, wzr, #0x3030303
2721 # CHECK: eor w16, w17, #0x81818181
2726 # CHECK: {{ands wzr,|tst}} w18, #0xcccccccc
2727 # CHECK: ands w19, w20, #0x33333333
2728 # CHECK: ands w21, w22, #0x99999999
2733 # CHECK: {{ands wzr,|tst}} w3, #0xaaaaaaaa
2734 # CHECK: {{ands wzr,|tst}} wzr, #0x55555555
2738 # CHECK: eor x3, x5, #0xffffffffc000000
2739 # CHECK: and x9, x10, #0x7fffffffffff
2740 # CHECK: orr x11, x12, #0x8000000000000fff
2745 # CHECK: orr x3, x9, #0xffff0000ffff0000
2746 # CHECK: orr sp, x10, #0xe00000ffe00000ff
2747 # CHECK: orr x9, x10, #0x3ff000003ff
2752 # CHECK: and x14, x15, #0x8000800080008000
2753 # CHECK: and x12, x13, #0xffc3ffc3ffc3ffc3
2754 # CHECK: and x11, xzr, #0x3000300030003
2759 # CHECK: eor x3, x6, #0xe0e0e0e0e0e0e0e0
2760 # CHECK: eor sp, xzr, #0x303030303030303
2761 # CHECK: eor x16, x17, #0x8181818181818181
2766 # CHECK: {{ands xzr,|tst}} x18, #0xcccccccccccccccc
2767 # CHECK: ands x19, x20, #0x3333333333333333
2768 # CHECK: ands x21, x22, #0x9999999999999999
2773 # CHECK: {{ands xzr,|tst}} x3, #0xaaaaaaaaaaaaaaaa
2774 # CHECK: {{ands xzr,|tst}} xzr, #0x5555555555555555
2778 # CHECK: orr w3, wzr, #0xf000f
2779 # CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa
2783 # CHECK: orr w3, wzr, #0xffff
2784 # CHECK: orr x9, xzr, #0xffff00000000
2788 #------------------------------------------------------------------------------
2789 # Logical (shifted register)
2790 #------------------------------------------------------------------------------
2792 # CHECK: and w12, w23, w21
2793 # CHECK: and w16, w15, w1, lsl #1
2794 # CHECK: and w9, w4, w10, lsl #31
2795 # CHECK: and w3, w30, w11
2796 # CHECK: and x3, x5, x7, lsl #63
2803 # CHECK: and x5, x14, x19, asr #4
2804 # CHECK: and w3, w17, w19, ror #31
2805 # CHECK: and w0, w2, wzr, lsr #17
2806 # CHECK: and w3, w30, w11, asr
2812 # CHECK: and xzr, x4, x26
2813 # CHECK: and w3, wzr, w20, ror
2814 # CHECK: and x7, x20, xzr, asr #63
2819 # CHECK: bic x13, x20, x14, lsl #47
2820 # CHECK: bic w2, w7, w9
2821 # CHECK: orr w2, w7, w0, asr #31
2822 # CHECK: orr x8, x9, x10, lsl #12
2823 # CHECK: orn x3, x5, x7, asr
2824 # CHECK: orn w2, w5, w29
2832 # CHECK: ands w7, wzr, w9, lsl #1
2833 # CHECK: ands x3, x5, x20, ror #63
2834 # CHECK: bics w3, w5, w7
2835 # CHECK: bics x3, xzr, x3, lsl #1
2836 # CHECK: tst w3, w7, lsl #31
2837 # CHECK: tst x2, x20, asr
2846 # CHECK: mov x3, xzr
2847 # CHECK: mov wzr, w2
2854 #------------------------------------------------------------------------------
2855 # Move wide (immediate)
2856 #------------------------------------------------------------------------------
2858 # N.b. (FIXME) canonical aliases aren't produced here because of
2859 # limitation in InstAlias. Lots of the "mov[nz]" instructions should
2862 # CHECK: movz w1, #{{65535|0xffff}}
2863 # CHECK: movz w2, #0, lsl #16
2864 # CHECK: movn w2, #{{1234|0x4d2}}
2869 # CHECK: movz x2, #{{1234|0x4d2}}, lsl #32
2870 # CHECK: movk xzr, #{{4321|0x10e1}}, lsl #48
2874 # CHECK: movz x2, #0
2875 # CHECK: movk w3, #0
2876 # CHECK: movz x4, #0, lsl #16
2877 # CHECK: movk w5, #0, lsl #16
2878 # CHECK: movz x6, #0, lsl #32
2879 # CHECK: movk x7, #0, lsl #32
2880 # CHECK: movz x8, #0, lsl #48
2881 # CHECK: movk x9, #0, lsl #48
2891 #------------------------------------------------------------------------------
2892 # PC-relative addressing
2893 #------------------------------------------------------------------------------
2895 # It's slightly dodgy using immediates here, but harmless enough when
2896 # it's all that's available.
2898 # CHECK: adr x2, #1600
2899 # CHECK: adrp x21, #6553600
2900 # CHECK: adr x0, #262144
2905 #------------------------------------------------------------------------------
2907 #------------------------------------------------------------------------------
2910 # CHECK: hint #{{127|0x7f}}
3002 # CHECK: msr {{spsel|SPSEL}}, #0
3003 # CHECK: msr {{daifset|DAIFSET}}, #15
3004 # CHECK: msr {{daifclr|DAIFCLR}}, #12
3009 # CHECK: sys #7, c5, c9, #7, x5
3010 # CHECK: sys #0, c15, c15, #2
3011 # CHECK: sysl x9, #7, c5, c9, #7
3012 # CHECK: sysl x1, #0, c15, c15, #2
3018 # CHECK: {{sys #0, c7, c1, #0, xzr|ic ialluis}}
3019 # CHECK: {{sys #0, c7, c5, #0, xzr|ic iallu}}
3020 # CHECK: {{sys #3, c7, c5, #1|ic ivau}}, x9
3025 # CHECK: {{sys #3, c7, c4, #1|dc zva}}, x12
3026 # CHECK: {{sys #0, c7, c6, #1|dc ivac}}, xzr
3027 # CHECK: {{sys #0, c7, c6, #2|dc isw}}, x2
3028 # CHECK: {{sys #3, c7, c10, #1|dc cvac}}, x9
3029 # CHECK: {{sys #0, c7, c10, #2|dc csw}}, x10
3030 # CHECK: {{sys #3, c7, c11, #1|dc cvau}}, x0
3031 # CHECK: {{sys #3, c7, c14, #1|dc civac}}, x3
3032 # CHECK: {{sys #0, c7, c14, #2|dc cisw}}, x30
3043 # CHECK: msr {{teecr32_el1|TEECR32_EL1}}, x12
3044 # CHECK: msr {{osdtrrx_el1|OSDTRRX_EL1}}, x12
3045 # CHECK: msr {{mdccint_el1|MDCCINT_EL1}}, x12
3046 # CHECK: msr {{mdscr_el1|MDSCR_EL1}}, x12
3047 # CHECK: msr {{osdtrtx_el1|OSDTRTX_EL1}}, x12
3048 # CHECK: msr {{dbgdtr_el0|DBGDTR_EL0}}, x12
3049 # CHECK: msr {{dbgdtrtx_el0|DBGDTRTX_EL0}}, x12
3050 # CHECK: msr {{oseccr_el1|OSECCR_EL1}}, x12
3051 # CHECK: msr {{dbgvcr32_el2|DBGVCR32_EL2}}, x12
3052 # CHECK: msr {{dbgbvr0_el1|DBGBVR0_EL1}}, x12
3053 # CHECK: msr {{dbgbvr1_el1|DBGBVR1_EL1}}, x12
3054 # CHECK: msr {{dbgbvr2_el1|DBGBVR2_EL1}}, x12
3055 # CHECK: msr {{dbgbvr3_el1|DBGBVR3_EL1}}, x12
3056 # CHECK: msr {{dbgbvr4_el1|DBGBVR4_EL1}}, x12
3057 # CHECK: msr {{dbgbvr5_el1|DBGBVR5_EL1}}, x12
3058 # CHECK: msr {{dbgbvr6_el1|DBGBVR6_EL1}}, x12
3059 # CHECK: msr {{dbgbvr7_el1|DBGBVR7_EL1}}, x12
3060 # CHECK: msr {{dbgbvr8_el1|DBGBVR8_EL1}}, x12
3061 # CHECK: msr {{dbgbvr9_el1|DBGBVR9_EL1}}, x12
3062 # CHECK: msr {{dbgbvr10_el1|DBGBVR10_EL1}}, x12
3063 # CHECK: msr {{dbgbvr11_el1|DBGBVR11_EL1}}, x12
3064 # CHECK: msr {{dbgbvr12_el1|DBGBVR12_EL1}}, x12
3065 # CHECK: msr {{dbgbvr13_el1|DBGBVR13_EL1}}, x12
3066 # CHECK: msr {{dbgbvr14_el1|DBGBVR14_EL1}}, x12
3067 # CHECK: msr {{dbgbvr15_el1|DBGBVR15_EL1}}, x12
3068 # CHECK: msr {{dbgbcr0_el1|DBGBCR0_EL1}}, x12
3069 # CHECK: msr {{dbgbcr1_el1|DBGBCR1_EL1}}, x12
3070 # CHECK: msr {{dbgbcr2_el1|DBGBCR2_EL1}}, x12
3071 # CHECK: msr {{dbgbcr3_el1|DBGBCR3_EL1}}, x12
3072 # CHECK: msr {{dbgbcr4_el1|DBGBCR4_EL1}}, x12
3073 # CHECK: msr {{dbgbcr5_el1|DBGBCR5_EL1}}, x12
3074 # CHECK: msr {{dbgbcr6_el1|DBGBCR6_EL1}}, x12
3075 # CHECK: msr {{dbgbcr7_el1|DBGBCR7_EL1}}, x12
3076 # CHECK: msr {{dbgbcr8_el1|DBGBCR8_EL1}}, x12
3077 # CHECK: msr {{dbgbcr9_el1|DBGBCR9_EL1}}, x12
3078 # CHECK: msr {{dbgbcr10_el1|DBGBCR10_EL1}}, x12
3079 # CHECK: msr {{dbgbcr11_el1|DBGBCR11_EL1}}, x12
3080 # CHECK: msr {{dbgbcr12_el1|DBGBCR12_EL1}}, x12
3081 # CHECK: msr {{dbgbcr13_el1|DBGBCR13_EL1}}, x12
3082 # CHECK: msr {{dbgbcr14_el1|DBGBCR14_EL1}}, x12
3083 # CHECK: msr {{dbgbcr15_el1|DBGBCR15_EL1}}, x12
3084 # CHECK: msr {{dbgwvr0_el1|DBGWVR0_EL1}}, x12
3085 # CHECK: msr {{dbgwvr1_el1|DBGWVR1_EL1}}, x12
3086 # CHECK: msr {{dbgwvr2_el1|DBGWVR2_EL1}}, x12
3087 # CHECK: msr {{dbgwvr3_el1|DBGWVR3_EL1}}, x12
3088 # CHECK: msr {{dbgwvr4_el1|DBGWVR4_EL1}}, x12
3089 # CHECK: msr {{dbgwvr5_el1|DBGWVR5_EL1}}, x12
3090 # CHECK: msr {{dbgwvr6_el1|DBGWVR6_EL1}}, x12
3091 # CHECK: msr {{dbgwvr7_el1|DBGWVR7_EL1}}, x12
3092 # CHECK: msr {{dbgwvr8_el1|DBGWVR8_EL1}}, x12
3093 # CHECK: msr {{dbgwvr9_el1|DBGWVR9_EL1}}, x12
3094 # CHECK: msr {{dbgwvr10_el1|DBGWVR10_EL1}}, x12
3095 # CHECK: msr {{dbgwvr11_el1|DBGWVR11_EL1}}, x12
3096 # CHECK: msr {{dbgwvr12_el1|DBGWVR12_EL1}}, x12
3097 # CHECK: msr {{dbgwvr13_el1|DBGWVR13_EL1}}, x12
3098 # CHECK: msr {{dbgwvr14_el1|DBGWVR14_EL1}}, x12
3099 # CHECK: msr {{dbgwvr15_el1|DBGWVR15_EL1}}, x12
3100 # CHECK: msr {{dbgwcr0_el1|DBGWCR0_EL1}}, x12
3101 # CHECK: msr {{dbgwcr1_el1|DBGWCR1_EL1}}, x12
3102 # CHECK: msr {{dbgwcr2_el1|DBGWCR2_EL1}}, x12
3103 # CHECK: msr {{dbgwcr3_el1|DBGWCR3_EL1}}, x12
3104 # CHECK: msr {{dbgwcr4_el1|DBGWCR4_EL1}}, x12
3105 # CHECK: msr {{dbgwcr5_el1|DBGWCR5_EL1}}, x12
3106 # CHECK: msr {{dbgwcr6_el1|DBGWCR6_EL1}}, x12
3107 # CHECK: msr {{dbgwcr7_el1|DBGWCR7_EL1}}, x12
3108 # CHECK: msr {{dbgwcr8_el1|DBGWCR8_EL1}}, x12
3109 # CHECK: msr {{dbgwcr9_el1|DBGWCR9_EL1}}, x12
3110 # CHECK: msr {{dbgwcr10_el1|DBGWCR10_EL1}}, x12
3111 # CHECK: msr {{dbgwcr11_el1|DBGWCR11_EL1}}, x12
3112 # CHECK: msr {{dbgwcr12_el1|DBGWCR12_EL1}}, x12
3113 # CHECK: msr {{dbgwcr13_el1|DBGWCR13_EL1}}, x12
3114 # CHECK: msr {{dbgwcr14_el1|DBGWCR14_EL1}}, x12
3115 # CHECK: msr {{dbgwcr15_el1|DBGWCR15_EL1}}, x12
3116 # CHECK: msr {{teehbr32_el1|TEEHBR32_EL1}}, x12
3117 # CHECK: msr {{oslar_el1|OSLAR_EL1}}, x12
3118 # CHECK: msr {{osdlr_el1|OSDLR_EL1}}, x12
3119 # CHECK: msr {{dbgprcr_el1|DBGPRCR_EL1}}, x12
3120 # CHECK: msr {{dbgclaimset_el1|DBGCLAIMSET_EL1}}, x12
3121 # CHECK: msr {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}, x12
3122 # CHECK: msr {{csselr_el1|CSSELR_EL1}}, x12
3123 # CHECK: msr {{vpidr_el2|VPIDR_EL2}}, x12
3124 # CHECK: msr {{vmpidr_el2|VMPIDR_EL2}}, x12
3125 # CHECK: msr {{sctlr_el1|SCTLR_EL1}}, x12
3126 # CHECK: msr {{sctlr_el2|SCTLR_EL2}}, x12
3127 # CHECK: msr {{sctlr_el3|SCTLR_EL3}}, x12
3128 # CHECK: msr {{actlr_el1|ACTLR_EL1}}, x12
3129 # CHECK: msr {{actlr_el2|ACTLR_EL2}}, x12
3130 # CHECK: msr {{actlr_el3|ACTLR_EL3}}, x12
3131 # CHECK: msr {{cpacr_el1|CPACR_EL1}}, x12
3132 # CHECK: msr {{hcr_el2|HCR_EL2}}, x12
3133 # CHECK: msr {{scr_el3|SCR_EL3}}, x12
3134 # CHECK: msr {{mdcr_el2|MDCR_EL2}}, x12
3135 # CHECK: msr {{sder32_el3|SDER32_EL3}}, x12
3136 # CHECK: msr {{cptr_el2|CPTR_EL2}}, x12
3137 # CHECK: msr {{cptr_el3|CPTR_EL3}}, x12
3138 # CHECK: msr {{hstr_el2|HSTR_EL2}}, x12
3139 # CHECK: msr {{hacr_el2|HACR_EL2}}, x12
3140 # CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12
3141 # CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12
3142 # CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12
3143 # CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12
3144 # CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12
3145 # CHECK: msr {{tcr_el1|TCR_EL1}}, x12
3146 # CHECK: msr {{tcr_el2|TCR_EL2}}, x12
3147 # CHECK: msr {{tcr_el3|TCR_EL3}}, x12
3148 # CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12
3149 # CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12
3150 # CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12
3151 # CHECK: msr {{spsr_el1|SPSR_EL1}}, x12
3152 # CHECK: msr {{spsr_el2|SPSR_EL2}}, x12
3153 # CHECK: msr {{spsr_el3|SPSR_EL3}}, x12
3154 # CHECK: msr {{elr_el1|ELR_EL1}}, x12
3155 # CHECK: msr {{elr_el2|ELR_EL2}}, x12
3156 # CHECK: msr {{elr_el3|ELR_EL3}}, x12
3157 # CHECK: msr {{sp_el0|SP_EL0}}, x12
3158 # CHECK: msr {{sp_el1|SP_EL1}}, x12
3159 # CHECK: msr {{sp_el2|SP_EL2}}, x12
3160 # CHECK: msr {{spsel|SPSEL}}, x12
3161 # CHECK: msr {{nzcv|NZCV}}, x12
3162 # CHECK: msr {{daif|DAIF}}, x12
3163 # CHECK: msr {{currentel|CURRENTEL}}, x12
3164 # CHECK: msr {{spsr_irq|SPSR_IRQ}}, x12
3165 # CHECK: msr {{spsr_abt|SPSR_ABT}}, x12
3166 # CHECK: msr {{spsr_und|SPSR_UND}}, x12
3167 # CHECK: msr {{spsr_fiq|SPSR_FIQ}}, x12
3168 # CHECK: msr {{fpcr|FPCR}}, x12
3169 # CHECK: msr {{fpsr|FPSR}}, x12
3170 # CHECK: msr {{dspsr_el0|DSPSR_EL0}}, x12
3171 # CHECK: msr {{dlr_el0|DLR_EL0}}, x12
3172 # CHECK: msr {{ifsr32_el2|IFSR32_EL2}}, x12
3173 # CHECK: msr {{afsr0_el1|AFSR0_EL1}}, x12
3174 # CHECK: msr {{afsr0_el2|AFSR0_EL2}}, x12
3175 # CHECK: msr {{afsr0_el3|AFSR0_EL3}}, x12
3176 # CHECK: msr {{afsr1_el1|AFSR1_EL1}}, x12
3177 # CHECK: msr {{afsr1_el2|AFSR1_EL2}}, x12
3178 # CHECK: msr {{afsr1_el3|AFSR1_EL3}}, x12
3179 # CHECK: msr {{esr_el1|ESR_EL1}}, x12
3180 # CHECK: msr {{esr_el2|ESR_EL2}}, x12
3181 # CHECK: msr {{esr_el3|ESR_EL3}}, x12
3182 # CHECK: msr {{fpexc32_el2|FPEXC32_EL2}}, x12
3183 # CHECK: msr {{far_el1|FAR_EL1}}, x12
3184 # CHECK: msr {{far_el2|FAR_EL2}}, x12
3185 # CHECK: msr {{far_el3|FAR_EL3}}, x12
3186 # CHECK: msr {{hpfar_el2|HPFAR_EL2}}, x12
3187 # CHECK: msr {{par_el1|PAR_EL1}}, x12
3188 # CHECK: msr {{pmcr_el0|PMCR_EL0}}, x12
3189 # CHECK: msr {{pmcntenset_el0|PMCNTENSET_EL0}}, x12
3190 # CHECK: msr {{pmcntenclr_el0|PMCNTENCLR_EL0}}, x12
3191 # CHECK: msr {{pmovsclr_el0|PMOVSCLR_EL0}}, x12
3192 # CHECK: msr {{pmselr_el0|PMSELR_EL0}}, x12
3193 # CHECK: msr {{pmccntr_el0|PMCCNTR_EL0}}, x12
3194 # CHECK: msr {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12
3195 # CHECK: msr {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12
3196 # CHECK: msr {{pmuserenr_el0|PMUSERENR_EL0}}, x12
3197 # CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12
3198 # CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12
3199 # CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12
3200 # CHECK: msr {{mair_el1|MAIR_EL1}}, x12
3201 # CHECK: msr {{mair_el2|MAIR_EL2}}, x12
3202 # CHECK: msr {{mair_el3|MAIR_EL3}}, x12
3203 # CHECK: msr {{amair_el1|AMAIR_EL1}}, x12
3204 # CHECK: msr {{amair_el2|AMAIR_EL2}}, x12
3205 # CHECK: msr {{amair_el3|AMAIR_EL3}}, x12
3206 # CHECK: msr {{vbar_el1|VBAR_EL1}}, x12
3207 # CHECK: msr {{vbar_el2|VBAR_EL2}}, x12
3208 # CHECK: msr {{vbar_el3|VBAR_EL3}}, x12
3209 # CHECK: msr {{rmr_el1|RMR_EL1}}, x12
3210 # CHECK: msr {{rmr_el2|RMR_EL2}}, x12
3211 # CHECK: msr {{rmr_el3|RMR_EL3}}, x12
3212 # CHECK: msr {{tpidr_el0|TPIDR_EL0}}, x12
3213 # CHECK: msr {{tpidr_el2|TPIDR_EL2}}, x12
3214 # CHECK: msr {{tpidr_el3|TPIDR_EL3}}, x12
3215 # CHECK: msr {{tpidrro_el0|TPIDRRO_EL0}}, x12
3216 # CHECK: msr {{tpidr_el1|TPIDR_EL1}}, x12
3217 # CHECK: msr {{cntfrq_el0|CNTFRQ_EL0}}, x12
3218 # CHECK: msr {{cntvoff_el2|CNTVOFF_EL2}}, x12
3219 # CHECK: msr {{cntkctl_el1|CNTKCTL_EL1}}, x12
3220 # CHECK: msr {{cnthctl_el2|CNTHCTL_EL2}}, x12
3221 # CHECK: msr {{cntp_tval_el0|CNTP_TVAL_EL0}}, x12
3222 # CHECK: msr {{cnthp_tval_el2|CNTHP_TVAL_EL2}}, x12
3223 # CHECK: msr {{cntps_tval_el1|CNTPS_TVAL_EL1}}, x12
3224 # CHECK: msr {{cntp_ctl_el0|CNTP_CTL_EL0}}, x12
3225 # CHECK: msr {{cnthp_ctl_el2|CNTHP_CTL_EL2}}, x12
3226 # CHECK: msr {{cntps_ctl_el1|CNTPS_CTL_EL1}}, x12
3227 # CHECK: msr {{cntp_cval_el0|CNTP_CVAL_EL0}}, x12
3228 # CHECK: msr {{cnthp_cval_el2|CNTHP_CVAL_EL2}}, x12
3229 # CHECK: msr {{cntps_cval_el1|CNTPS_CVAL_EL1}}, x12
3230 # CHECK: msr {{cntv_tval_el0|CNTV_TVAL_EL0}}, x12
3231 # CHECK: msr {{cntv_ctl_el0|CNTV_CTL_EL0}}, x12
3232 # CHECK: msr {{cntv_cval_el0|CNTV_CVAL_EL0}}, x12
3233 # CHECK: msr {{pmevcntr0_el0|PMEVCNTR0_EL0}}, x12
3234 # CHECK: msr {{pmevcntr1_el0|PMEVCNTR1_EL0}}, x12
3235 # CHECK: msr {{pmevcntr2_el0|PMEVCNTR2_EL0}}, x12
3236 # CHECK: msr {{pmevcntr3_el0|PMEVCNTR3_EL0}}, x12
3237 # CHECK: msr {{pmevcntr4_el0|PMEVCNTR4_EL0}}, x12
3238 # CHECK: msr {{pmevcntr5_el0|PMEVCNTR5_EL0}}, x12
3239 # CHECK: msr {{pmevcntr6_el0|PMEVCNTR6_EL0}}, x12
3240 # CHECK: msr {{pmevcntr7_el0|PMEVCNTR7_EL0}}, x12
3241 # CHECK: msr {{pmevcntr8_el0|PMEVCNTR8_EL0}}, x12
3242 # CHECK: msr {{pmevcntr9_el0|PMEVCNTR9_EL0}}, x12
3243 # CHECK: msr {{pmevcntr10_el0|PMEVCNTR10_EL0}}, x12
3244 # CHECK: msr {{pmevcntr11_el0|PMEVCNTR11_EL0}}, x12
3245 # CHECK: msr {{pmevcntr12_el0|PMEVCNTR12_EL0}}, x12
3246 # CHECK: msr {{pmevcntr13_el0|PMEVCNTR13_EL0}}, x12
3247 # CHECK: msr {{pmevcntr14_el0|PMEVCNTR14_EL0}}, x12
3248 # CHECK: msr {{pmevcntr15_el0|PMEVCNTR15_EL0}}, x12
3249 # CHECK: msr {{pmevcntr16_el0|PMEVCNTR16_EL0}}, x12
3250 # CHECK: msr {{pmevcntr17_el0|PMEVCNTR17_EL0}}, x12
3251 # CHECK: msr {{pmevcntr18_el0|PMEVCNTR18_EL0}}, x12
3252 # CHECK: msr {{pmevcntr19_el0|PMEVCNTR19_EL0}}, x12
3253 # CHECK: msr {{pmevcntr20_el0|PMEVCNTR20_EL0}}, x12
3254 # CHECK: msr {{pmevcntr21_el0|PMEVCNTR21_EL0}}, x12
3255 # CHECK: msr {{pmevcntr22_el0|PMEVCNTR22_EL0}}, x12
3256 # CHECK: msr {{pmevcntr23_el0|PMEVCNTR23_EL0}}, x12
3257 # CHECK: msr {{pmevcntr24_el0|PMEVCNTR24_EL0}}, x12
3258 # CHECK: msr {{pmevcntr25_el0|PMEVCNTR25_EL0}}, x12
3259 # CHECK: msr {{pmevcntr26_el0|PMEVCNTR26_EL0}}, x12
3260 # CHECK: msr {{pmevcntr27_el0|PMEVCNTR27_EL0}}, x12
3261 # CHECK: msr {{pmevcntr28_el0|PMEVCNTR28_EL0}}, x12
3262 # CHECK: msr {{pmevcntr29_el0|PMEVCNTR29_EL0}}, x12
3263 # CHECK: msr {{pmevcntr30_el0|PMEVCNTR30_EL0}}, x12
3264 # CHECK: msr {{pmccfiltr_el0|PMCCFILTR_EL0}}, x12
3265 # CHECK: msr {{pmevtyper0_el0|PMEVTYPER0_EL0}}, x12
3266 # CHECK: msr {{pmevtyper1_el0|PMEVTYPER1_EL0}}, x12
3267 # CHECK: msr {{pmevtyper2_el0|PMEVTYPER2_EL0}}, x12
3268 # CHECK: msr {{pmevtyper3_el0|PMEVTYPER3_EL0}}, x12
3269 # CHECK: msr {{pmevtyper4_el0|PMEVTYPER4_EL0}}, x12
3270 # CHECK: msr {{pmevtyper5_el0|PMEVTYPER5_EL0}}, x12
3271 # CHECK: msr {{pmevtyper6_el0|PMEVTYPER6_EL0}}, x12
3272 # CHECK: msr {{pmevtyper7_el0|PMEVTYPER7_EL0}}, x12
3273 # CHECK: msr {{pmevtyper8_el0|PMEVTYPER8_EL0}}, x12
3274 # CHECK: msr {{pmevtyper9_el0|PMEVTYPER9_EL0}}, x12
3275 # CHECK: msr {{pmevtyper10_el0|PMEVTYPER10_EL0}}, x12
3276 # CHECK: msr {{pmevtyper11_el0|PMEVTYPER11_EL0}}, x12
3277 # CHECK: msr {{pmevtyper12_el0|PMEVTYPER12_EL0}}, x12
3278 # CHECK: msr {{pmevtyper13_el0|PMEVTYPER13_EL0}}, x12
3279 # CHECK: msr {{pmevtyper14_el0|PMEVTYPER14_EL0}}, x12
3280 # CHECK: msr {{pmevtyper15_el0|PMEVTYPER15_EL0}}, x12
3281 # CHECK: msr {{pmevtyper16_el0|PMEVTYPER16_EL0}}, x12
3282 # CHECK: msr {{pmevtyper17_el0|PMEVTYPER17_EL0}}, x12
3283 # CHECK: msr {{pmevtyper18_el0|PMEVTYPER18_EL0}}, x12
3284 # CHECK: msr {{pmevtyper19_el0|PMEVTYPER19_EL0}}, x12
3285 # CHECK: msr {{pmevtyper20_el0|PMEVTYPER20_EL0}}, x12
3286 # CHECK: msr {{pmevtyper21_el0|PMEVTYPER21_EL0}}, x12
3287 # CHECK: msr {{pmevtyper22_el0|PMEVTYPER22_EL0}}, x12
3288 # CHECK: msr {{pmevtyper23_el0|PMEVTYPER23_EL0}}, x12
3289 # CHECK: msr {{pmevtyper24_el0|PMEVTYPER24_EL0}}, x12
3290 # CHECK: msr {{pmevtyper25_el0|PMEVTYPER25_EL0}}, x12
3291 # CHECK: msr {{pmevtyper26_el0|PMEVTYPER26_EL0}}, x12
3292 # CHECK: msr {{pmevtyper27_el0|PMEVTYPER27_EL0}}, x12
3293 # CHECK: msr {{pmevtyper28_el0|PMEVTYPER28_EL0}}, x12
3294 # CHECK: msr {{pmevtyper29_el0|PMEVTYPER29_EL0}}, x12
3295 # CHECK: msr {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12
3296 # CHECK: mrs x9, {{teecr32_el1|TEECR32_EL1}}
3297 # CHECK: mrs x9, {{osdtrrx_el1|OSDTRRX_EL1}}
3298 # CHECK: mrs x9, {{mdccsr_el0|MDCCSR_EL0}}
3299 # CHECK: mrs x9, {{mdccint_el1|MDCCINT_EL1}}
3300 # CHECK: mrs x9, {{mdscr_el1|MDSCR_EL1}}
3301 # CHECK: mrs x9, {{osdtrtx_el1|OSDTRTX_EL1}}
3302 # CHECK: mrs x9, {{dbgdtr_el0|DBGDTR_EL0}}
3303 # CHECK: mrs x9, {{dbgdtrrx_el0|DBGDTRRX_EL0}}
3304 # CHECK: mrs x9, {{oseccr_el1|OSECCR_EL1}}
3305 # CHECK: mrs x9, {{dbgvcr32_el2|DBGVCR32_EL2}}
3306 # CHECK: mrs x9, {{dbgbvr0_el1|DBGBVR0_EL1}}
3307 # CHECK: mrs x9, {{dbgbvr1_el1|DBGBVR1_EL1}}
3308 # CHECK: mrs x9, {{dbgbvr2_el1|DBGBVR2_EL1}}
3309 # CHECK: mrs x9, {{dbgbvr3_el1|DBGBVR3_EL1}}
3310 # CHECK: mrs x9, {{dbgbvr4_el1|DBGBVR4_EL1}}
3311 # CHECK: mrs x9, {{dbgbvr5_el1|DBGBVR5_EL1}}
3312 # CHECK: mrs x9, {{dbgbvr6_el1|DBGBVR6_EL1}}
3313 # CHECK: mrs x9, {{dbgbvr7_el1|DBGBVR7_EL1}}
3314 # CHECK: mrs x9, {{dbgbvr8_el1|DBGBVR8_EL1}}
3315 # CHECK: mrs x9, {{dbgbvr9_el1|DBGBVR9_EL1}}
3316 # CHECK: mrs x9, {{dbgbvr10_el1|DBGBVR10_EL1}}
3317 # CHECK: mrs x9, {{dbgbvr11_el1|DBGBVR11_EL1}}
3318 # CHECK: mrs x9, {{dbgbvr12_el1|DBGBVR12_EL1}}
3319 # CHECK: mrs x9, {{dbgbvr13_el1|DBGBVR13_EL1}}
3320 # CHECK: mrs x9, {{dbgbvr14_el1|DBGBVR14_EL1}}
3321 # CHECK: mrs x9, {{dbgbvr15_el1|DBGBVR15_EL1}}
3322 # CHECK: mrs x9, {{dbgbcr0_el1|DBGBCR0_EL1}}
3323 # CHECK: mrs x9, {{dbgbcr1_el1|DBGBCR1_EL1}}
3324 # CHECK: mrs x9, {{dbgbcr2_el1|DBGBCR2_EL1}}
3325 # CHECK: mrs x9, {{dbgbcr3_el1|DBGBCR3_EL1}}
3326 # CHECK: mrs x9, {{dbgbcr4_el1|DBGBCR4_EL1}}
3327 # CHECK: mrs x9, {{dbgbcr5_el1|DBGBCR5_EL1}}
3328 # CHECK: mrs x9, {{dbgbcr6_el1|DBGBCR6_EL1}}
3329 # CHECK: mrs x9, {{dbgbcr7_el1|DBGBCR7_EL1}}
3330 # CHECK: mrs x9, {{dbgbcr8_el1|DBGBCR8_EL1}}
3331 # CHECK: mrs x9, {{dbgbcr9_el1|DBGBCR9_EL1}}
3332 # CHECK: mrs x9, {{dbgbcr10_el1|DBGBCR10_EL1}}
3333 # CHECK: mrs x9, {{dbgbcr11_el1|DBGBCR11_EL1}}
3334 # CHECK: mrs x9, {{dbgbcr12_el1|DBGBCR12_EL1}}
3335 # CHECK: mrs x9, {{dbgbcr13_el1|DBGBCR13_EL1}}
3336 # CHECK: mrs x9, {{dbgbcr14_el1|DBGBCR14_EL1}}
3337 # CHECK: mrs x9, {{dbgbcr15_el1|DBGBCR15_EL1}}
3338 # CHECK: mrs x9, {{dbgwvr0_el1|DBGWVR0_EL1}}
3339 # CHECK: mrs x9, {{dbgwvr1_el1|DBGWVR1_EL1}}
3340 # CHECK: mrs x9, {{dbgwvr2_el1|DBGWVR2_EL1}}
3341 # CHECK: mrs x9, {{dbgwvr3_el1|DBGWVR3_EL1}}
3342 # CHECK: mrs x9, {{dbgwvr4_el1|DBGWVR4_EL1}}
3343 # CHECK: mrs x9, {{dbgwvr5_el1|DBGWVR5_EL1}}
3344 # CHECK: mrs x9, {{dbgwvr6_el1|DBGWVR6_EL1}}
3345 # CHECK: mrs x9, {{dbgwvr7_el1|DBGWVR7_EL1}}
3346 # CHECK: mrs x9, {{dbgwvr8_el1|DBGWVR8_EL1}}
3347 # CHECK: mrs x9, {{dbgwvr9_el1|DBGWVR9_EL1}}
3348 # CHECK: mrs x9, {{dbgwvr10_el1|DBGWVR10_EL1}}
3349 # CHECK: mrs x9, {{dbgwvr11_el1|DBGWVR11_EL1}}
3350 # CHECK: mrs x9, {{dbgwvr12_el1|DBGWVR12_EL1}}
3351 # CHECK: mrs x9, {{dbgwvr13_el1|DBGWVR13_EL1}}
3352 # CHECK: mrs x9, {{dbgwvr14_el1|DBGWVR14_EL1}}
3353 # CHECK: mrs x9, {{dbgwvr15_el1|DBGWVR15_EL1}}
3354 # CHECK: mrs x9, {{dbgwcr0_el1|DBGWCR0_EL1}}
3355 # CHECK: mrs x9, {{dbgwcr1_el1|DBGWCR1_EL1}}
3356 # CHECK: mrs x9, {{dbgwcr2_el1|DBGWCR2_EL1}}
3357 # CHECK: mrs x9, {{dbgwcr3_el1|DBGWCR3_EL1}}
3358 # CHECK: mrs x9, {{dbgwcr4_el1|DBGWCR4_EL1}}
3359 # CHECK: mrs x9, {{dbgwcr5_el1|DBGWCR5_EL1}}
3360 # CHECK: mrs x9, {{dbgwcr6_el1|DBGWCR6_EL1}}
3361 # CHECK: mrs x9, {{dbgwcr7_el1|DBGWCR7_EL1}}
3362 # CHECK: mrs x9, {{dbgwcr8_el1|DBGWCR8_EL1}}
3363 # CHECK: mrs x9, {{dbgwcr9_el1|DBGWCR9_EL1}}
3364 # CHECK: mrs x9, {{dbgwcr10_el1|DBGWCR10_EL1}}
3365 # CHECK: mrs x9, {{dbgwcr11_el1|DBGWCR11_EL1}}
3366 # CHECK: mrs x9, {{dbgwcr12_el1|DBGWCR12_EL1}}
3367 # CHECK: mrs x9, {{dbgwcr13_el1|DBGWCR13_EL1}}
3368 # CHECK: mrs x9, {{dbgwcr14_el1|DBGWCR14_EL1}}
3369 # CHECK: mrs x9, {{dbgwcr15_el1|DBGWCR15_EL1}}
3370 # CHECK: mrs x9, {{mdrar_el1|MDRAR_EL1}}
3371 # CHECK: mrs x9, {{teehbr32_el1|TEEHBR32_EL1}}
3372 # CHECK: mrs x9, {{oslsr_el1|OSLSR_EL1}}
3373 # CHECK: mrs x9, {{osdlr_el1|OSDLR_EL1}}
3374 # CHECK: mrs x9, {{dbgprcr_el1|DBGPRCR_EL1}}
3375 # CHECK: mrs x9, {{dbgclaimset_el1|DBGCLAIMSET_EL1}}
3376 # CHECK: mrs x9, {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}
3377 # CHECK: mrs x9, {{dbgauthstatus_el1|DBGAUTHSTATUS_EL1}}
3378 # CHECK: mrs x9, {{midr_el1|MIDR_EL1}}
3379 # CHECK: mrs x9, {{ccsidr_el1|CCSIDR_EL1}}
3380 # CHECK: mrs x9, {{csselr_el1|CSSELR_EL1}}
3381 # CHECK: mrs x9, {{vpidr_el2|VPIDR_EL2}}
3382 # CHECK: mrs x9, {{clidr_el1|CLIDR_EL1}}
3383 # CHECK: mrs x9, {{ctr_el0|CTR_EL0}}
3384 # CHECK: mrs x9, {{mpidr_el1|MPIDR_EL1}}
3385 # CHECK: mrs x9, {{vmpidr_el2|VMPIDR_EL2}}
3386 # CHECK: mrs x9, {{revidr_el1|REVIDR_EL1}}
3387 # CHECK: mrs x9, {{aidr_el1|AIDR_EL1}}
3388 # CHECK: mrs x9, {{dczid_el0|DCZID_EL0}}
3389 # CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}}
3390 # CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}}
3391 # CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}}
3392 # CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}}
3393 # CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}}
3394 # CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}}
3395 # CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}}
3396 # CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}}
3397 # CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}}
3398 # CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}}
3399 # CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}}
3400 # CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}}
3401 # CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}}
3402 # CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}}
3403 # CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}}
3404 # CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}}
3405 # CHECK: mrs x9, {{mvfr2_el1|MVFR2_EL1}}
3406 # CHECK: mrs x9, {{id_aa64pfr0_el1|ID_AA64PFR0_EL1}}
3407 # CHECK: mrs x9, {{id_aa64pfr1_el1|ID_AA64PFR1_EL1}}
3408 # CHECK: mrs x9, {{id_aa64dfr0_el1|ID_AA64DFR0_EL1}}
3409 # CHECK: mrs x9, {{id_aa64dfr1_el1|ID_AA64DFR1_EL1}}
3410 # CHECK: mrs x9, {{id_aa64afr0_el1|ID_AA64AFR0_EL1}}
3411 # CHECK: mrs x9, {{id_aa64afr1_el1|ID_AA64AFR1_EL1}}
3412 # CHECK: mrs x9, {{id_aa64isar0_el1|ID_AA64ISAR0_EL1}}
3413 # CHECK: mrs x9, {{id_aa64isar1_el1|ID_AA64ISAR1_EL1}}
3414 # CHECK: mrs x9, {{id_aa64mmfr0_el1|ID_AA64MMFR0_EL1}}
3415 # CHECK: mrs x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}}
3416 # CHECK: mrs x9, {{sctlr_el1|SCTLR_EL1}}
3417 # CHECK: mrs x9, {{sctlr_el2|SCTLR_EL2}}
3418 # CHECK: mrs x9, {{sctlr_el3|SCTLR_EL3}}
3419 # CHECK: mrs x9, {{actlr_el1|ACTLR_EL1}}
3420 # CHECK: mrs x9, {{actlr_el2|ACTLR_EL2}}
3421 # CHECK: mrs x9, {{actlr_el3|ACTLR_EL3}}
3422 # CHECK: mrs x9, {{cpacr_el1|CPACR_EL1}}
3423 # CHECK: mrs x9, {{hcr_el2|HCR_EL2}}
3424 # CHECK: mrs x9, {{scr_el3|SCR_EL3}}
3425 # CHECK: mrs x9, {{mdcr_el2|MDCR_EL2}}
3426 # CHECK: mrs x9, {{sder32_el3|SDER32_EL3}}
3427 # CHECK: mrs x9, {{cptr_el2|CPTR_EL2}}
3428 # CHECK: mrs x9, {{cptr_el3|CPTR_EL3}}
3429 # CHECK: mrs x9, {{hstr_el2|HSTR_EL2}}
3430 # CHECK: mrs x9, {{hacr_el2|HACR_EL2}}
3431 # CHECK: mrs x9, {{mdcr_el3|MDCR_EL3}}
3432 # CHECK: mrs x9, {{ttbr0_el1|TTBR0_EL1}}
3433 # CHECK: mrs x9, {{ttbr0_el2|TTBR0_EL2}}
3434 # CHECK: mrs x9, {{ttbr0_el3|TTBR0_EL3}}
3435 # CHECK: mrs x9, {{ttbr1_el1|TTBR1_EL1}}
3436 # CHECK: mrs x9, {{tcr_el1|TCR_EL1}}
3437 # CHECK: mrs x9, {{tcr_el2|TCR_EL2}}
3438 # CHECK: mrs x9, {{tcr_el3|TCR_EL3}}
3439 # CHECK: mrs x9, {{vttbr_el2|VTTBR_EL2}}
3440 # CHECK: mrs x9, {{vtcr_el2|VTCR_EL2}}
3441 # CHECK: mrs x9, {{dacr32_el2|DACR32_EL2}}
3442 # CHECK: mrs x9, {{spsr_el1|SPSR_EL1}}
3443 # CHECK: mrs x9, {{spsr_el2|SPSR_EL2}}
3444 # CHECK: mrs x9, {{spsr_el3|SPSR_EL3}}
3445 # CHECK: mrs x9, {{elr_el1|ELR_EL1}}
3446 # CHECK: mrs x9, {{elr_el2|ELR_EL2}}
3447 # CHECK: mrs x9, {{elr_el3|ELR_EL3}}
3448 # CHECK: mrs x9, {{sp_el0|SP_EL0}}
3449 # CHECK: mrs x9, {{sp_el1|SP_EL1}}
3450 # CHECK: mrs x9, {{sp_el2|SP_EL2}}
3451 # CHECK: mrs x9, {{spsel|SPSEL}}
3452 # CHECK: mrs x9, {{nzcv|NZCV}}
3453 # CHECK: mrs x9, {{daif|DAIF}}
3454 # CHECK: mrs x9, {{currentel|CURRENTEL}}
3455 # CHECK: mrs x9, {{spsr_irq|SPSR_IRQ}}
3456 # CHECK: mrs x9, {{spsr_abt|SPSR_ABT}}
3457 # CHECK: mrs x9, {{spsr_und|SPSR_UND}}
3458 # CHECK: mrs x9, {{spsr_fiq|SPSR_FIQ}}
3459 # CHECK: mrs x9, {{fpcr|FPCR}}
3460 # CHECK: mrs x9, {{fpsr|FPSR}}
3461 # CHECK: mrs x9, {{dspsr_el0|DSPSR_EL0}}
3462 # CHECK: mrs x9, {{dlr_el0|DLR_EL0}}
3463 # CHECK: mrs x9, {{ifsr32_el2|IFSR32_EL2}}
3464 # CHECK: mrs x9, {{afsr0_el1|AFSR0_EL1}}
3465 # CHECK: mrs x9, {{afsr0_el2|AFSR0_EL2}}
3466 # CHECK: mrs x9, {{afsr0_el3|AFSR0_EL3}}
3467 # CHECK: mrs x9, {{afsr1_el1|AFSR1_EL1}}
3468 # CHECK: mrs x9, {{afsr1_el2|AFSR1_EL2}}
3469 # CHECK: mrs x9, {{afsr1_el3|AFSR1_EL3}}
3470 # CHECK: mrs x9, {{esr_el1|ESR_EL1}}
3471 # CHECK: mrs x9, {{esr_el2|ESR_EL2}}
3472 # CHECK: mrs x9, {{esr_el3|ESR_EL3}}
3473 # CHECK: mrs x9, {{fpexc32_el2|FPEXC32_EL2}}
3474 # CHECK: mrs x9, {{far_el1|FAR_EL1}}
3475 # CHECK: mrs x9, {{far_el2|FAR_EL2}}
3476 # CHECK: mrs x9, {{far_el3|FAR_EL3}}
3477 # CHECK: mrs x9, {{hpfar_el2|HPFAR_EL2}}
3478 # CHECK: mrs x9, {{par_el1|PAR_EL1}}
3479 # CHECK: mrs x9, {{pmcr_el0|PMCR_EL0}}
3480 # CHECK: mrs x9, {{pmcntenset_el0|PMCNTENSET_EL0}}
3481 # CHECK: mrs x9, {{pmcntenclr_el0|PMCNTENCLR_EL0}}
3482 # CHECK: mrs x9, {{pmovsclr_el0|PMOVSCLR_EL0}}
3483 # CHECK: mrs x9, {{pmselr_el0|PMSELR_EL0}}
3484 # CHECK: mrs x9, {{pmceid0_el0|PMCEID0_EL0}}
3485 # CHECK: mrs x9, {{pmceid1_el0|PMCEID1_EL0}}
3486 # CHECK: mrs x9, {{pmccntr_el0|PMCCNTR_EL0}}
3487 # CHECK: mrs x9, {{pmxevtyper_el0|PMXEVTYPER_EL0}}
3488 # CHECK: mrs x9, {{pmxevcntr_el0|PMXEVCNTR_EL0}}
3489 # CHECK: mrs x9, {{pmuserenr_el0|PMUSERENR_EL0}}
3490 # CHECK: mrs x9, {{pmintenset_el1|PMINTENSET_EL1}}
3491 # CHECK: mrs x9, {{pmintenclr_el1|PMINTENCLR_EL1}}
3492 # CHECK: mrs x9, {{pmovsset_el0|PMOVSSET_EL0}}
3493 # CHECK: mrs x9, {{mair_el1|MAIR_EL1}}
3494 # CHECK: mrs x9, {{mair_el2|MAIR_EL2}}
3495 # CHECK: mrs x9, {{mair_el3|MAIR_EL3}}
3496 # CHECK: mrs x9, {{amair_el1|AMAIR_EL1}}
3497 # CHECK: mrs x9, {{amair_el2|AMAIR_EL2}}
3498 # CHECK: mrs x9, {{amair_el3|AMAIR_EL3}}
3499 # CHECK: mrs x9, {{vbar_el1|VBAR_EL1}}
3500 # CHECK: mrs x9, {{vbar_el2|VBAR_EL2}}
3501 # CHECK: mrs x9, {{vbar_el3|VBAR_EL3}}
3502 # CHECK: mrs x9, {{rvbar_el1|RVBAR_EL1}}
3503 # CHECK: mrs x9, {{rvbar_el2|RVBAR_EL2}}
3504 # CHECK: mrs x9, {{rvbar_el3|RVBAR_EL3}}
3505 # CHECK: mrs x9, {{rmr_el1|RMR_EL1}}
3506 # CHECK: mrs x9, {{rmr_el2|RMR_EL2}}
3507 # CHECK: mrs x9, {{rmr_el3|RMR_EL3}}
3508 # CHECK: mrs x9, {{isr_el1|ISR_EL1}}
3509 # CHECK: mrs x9, {{contextidr_el1|CONTEXTIDR_EL1}}
3510 # CHECK: mrs x9, {{tpidr_el0|TPIDR_EL0}}
3511 # CHECK: mrs x9, {{tpidr_el2|TPIDR_EL2}}
3512 # CHECK: mrs x9, {{tpidr_el3|TPIDR_EL3}}
3513 # CHECK: mrs x9, {{tpidrro_el0|TPIDRRO_EL0}}
3514 # CHECK: mrs x9, {{tpidr_el1|TPIDR_EL1}}
3515 # CHECK: mrs x9, {{cntfrq_el0|CNTFRQ_EL0}}
3516 # CHECK: mrs x9, {{cntpct_el0|CNTPCT_EL0}}
3517 # CHECK: mrs x9, {{cntvct_el0|CNTVCT_EL0}}
3518 # CHECK: mrs x9, {{cntvoff_el2|CNTVOFF_EL2}}
3519 # CHECK: mrs x9, {{cntkctl_el1|CNTKCTL_EL1}}
3520 # CHECK: mrs x9, {{cnthctl_el2|CNTHCTL_EL2}}
3521 # CHECK: mrs x9, {{cntp_tval_el0|CNTP_TVAL_EL0}}
3522 # CHECK: mrs x9, {{cnthp_tval_el2|CNTHP_TVAL_EL2}}
3523 # CHECK: mrs x9, {{cntps_tval_el1|CNTPS_TVAL_EL1}}
3524 # CHECK: mrs x9, {{cntp_ctl_el0|CNTP_CTL_EL0}}
3525 # CHECK: mrs x9, {{cnthp_ctl_el2|CNTHP_CTL_EL2}}
3526 # CHECK: mrs x9, {{cntps_ctl_el1|CNTPS_CTL_EL1}}
3527 # CHECK: mrs x9, {{cntp_cval_el0|CNTP_CVAL_EL0}}
3528 # CHECK: mrs x9, {{cnthp_cval_el2|CNTHP_CVAL_EL2}}
3529 # CHECK: mrs x9, {{cntps_cval_el1|CNTPS_CVAL_EL1}}
3530 # CHECK: mrs x9, {{cntv_tval_el0|CNTV_TVAL_EL0}}
3531 # CHECK: mrs x9, {{cntv_ctl_el0|CNTV_CTL_EL0}}
3532 # CHECK: mrs x9, {{cntv_cval_el0|CNTV_CVAL_EL0}}
3533 # CHECK: mrs x9, {{pmevcntr0_el0|PMEVCNTR0_EL0}}
3534 # CHECK: mrs x9, {{pmevcntr1_el0|PMEVCNTR1_EL0}}
3535 # CHECK: mrs x9, {{pmevcntr2_el0|PMEVCNTR2_EL0}}
3536 # CHECK: mrs x9, {{pmevcntr3_el0|PMEVCNTR3_EL0}}
3537 # CHECK: mrs x9, {{pmevcntr4_el0|PMEVCNTR4_EL0}}
3538 # CHECK: mrs x9, {{pmevcntr5_el0|PMEVCNTR5_EL0}}
3539 # CHECK: mrs x9, {{pmevcntr6_el0|PMEVCNTR6_EL0}}
3540 # CHECK: mrs x9, {{pmevcntr7_el0|PMEVCNTR7_EL0}}
3541 # CHECK: mrs x9, {{pmevcntr8_el0|PMEVCNTR8_EL0}}
3542 # CHECK: mrs x9, {{pmevcntr9_el0|PMEVCNTR9_EL0}}
3543 # CHECK: mrs x9, {{pmevcntr10_el0|PMEVCNTR10_EL0}}
3544 # CHECK: mrs x9, {{pmevcntr11_el0|PMEVCNTR11_EL0}}
3545 # CHECK: mrs x9, {{pmevcntr12_el0|PMEVCNTR12_EL0}}
3546 # CHECK: mrs x9, {{pmevcntr13_el0|PMEVCNTR13_EL0}}
3547 # CHECK: mrs x9, {{pmevcntr14_el0|PMEVCNTR14_EL0}}
3548 # CHECK: mrs x9, {{pmevcntr15_el0|PMEVCNTR15_EL0}}
3549 # CHECK: mrs x9, {{pmevcntr16_el0|PMEVCNTR16_EL0}}
3550 # CHECK: mrs x9, {{pmevcntr17_el0|PMEVCNTR17_EL0}}
3551 # CHECK: mrs x9, {{pmevcntr18_el0|PMEVCNTR18_EL0}}
3552 # CHECK: mrs x9, {{pmevcntr19_el0|PMEVCNTR19_EL0}}
3553 # CHECK: mrs x9, {{pmevcntr20_el0|PMEVCNTR20_EL0}}
3554 # CHECK: mrs x9, {{pmevcntr21_el0|PMEVCNTR21_EL0}}
3555 # CHECK: mrs x9, {{pmevcntr22_el0|PMEVCNTR22_EL0}}
3556 # CHECK: mrs x9, {{pmevcntr23_el0|PMEVCNTR23_EL0}}
3557 # CHECK: mrs x9, {{pmevcntr24_el0|PMEVCNTR24_EL0}}
3558 # CHECK: mrs x9, {{pmevcntr25_el0|PMEVCNTR25_EL0}}
3559 # CHECK: mrs x9, {{pmevcntr26_el0|PMEVCNTR26_EL0}}
3560 # CHECK: mrs x9, {{pmevcntr27_el0|PMEVCNTR27_EL0}}
3561 # CHECK: mrs x9, {{pmevcntr28_el0|PMEVCNTR28_EL0}}
3562 # CHECK: mrs x9, {{pmevcntr29_el0|PMEVCNTR29_EL0}}
3563 # CHECK: mrs x9, {{pmevcntr30_el0|PMEVCNTR30_EL0}}
3564 # CHECK: mrs x9, {{pmccfiltr_el0|PMCCFILTR_EL0}}
3565 # CHECK: mrs x9, {{pmevtyper0_el0|PMEVTYPER0_EL0}}
3566 # CHECK: mrs x9, {{pmevtyper1_el0|PMEVTYPER1_EL0}}
3567 # CHECK: mrs x9, {{pmevtyper2_el0|PMEVTYPER2_EL0}}
3568 # CHECK: mrs x9, {{pmevtyper3_el0|PMEVTYPER3_EL0}}
3569 # CHECK: mrs x9, {{pmevtyper4_el0|PMEVTYPER4_EL0}}
3570 # CHECK: mrs x9, {{pmevtyper5_el0|PMEVTYPER5_EL0}}
3571 # CHECK: mrs x9, {{pmevtyper6_el0|PMEVTYPER6_EL0}}
3572 # CHECK: mrs x9, {{pmevtyper7_el0|PMEVTYPER7_EL0}}
3573 # CHECK: mrs x9, {{pmevtyper8_el0|PMEVTYPER8_EL0}}
3574 # CHECK: mrs x9, {{pmevtyper9_el0|PMEVTYPER9_EL0}}
3575 # CHECK: mrs x9, {{pmevtyper10_el0|PMEVTYPER10_EL0}}
3576 # CHECK: mrs x9, {{pmevtyper11_el0|PMEVTYPER11_EL0}}
3577 # CHECK: mrs x9, {{pmevtyper12_el0|PMEVTYPER12_EL0}}
3578 # CHECK: mrs x9, {{pmevtyper13_el0|PMEVTYPER13_EL0}}
3579 # CHECK: mrs x9, {{pmevtyper14_el0|PMEVTYPER14_EL0}}
3580 # CHECK: mrs x9, {{pmevtyper15_el0|PMEVTYPER15_EL0}}
3581 # CHECK: mrs x9, {{pmevtyper16_el0|PMEVTYPER16_EL0}}
3582 # CHECK: mrs x9, {{pmevtyper17_el0|PMEVTYPER17_EL0}}
3583 # CHECK: mrs x9, {{pmevtyper18_el0|PMEVTYPER18_EL0}}
3584 # CHECK: mrs x9, {{pmevtyper19_el0|PMEVTYPER19_EL0}}
3585 # CHECK: mrs x9, {{pmevtyper20_el0|PMEVTYPER20_EL0}}
3586 # CHECK: mrs x9, {{pmevtyper21_el0|PMEVTYPER21_EL0}}
3587 # CHECK: mrs x9, {{pmevtyper22_el0|PMEVTYPER22_EL0}}
3588 # CHECK: mrs x9, {{pmevtyper23_el0|PMEVTYPER23_EL0}}
3589 # CHECK: mrs x9, {{pmevtyper24_el0|PMEVTYPER24_EL0}}
3590 # CHECK: mrs x9, {{pmevtyper25_el0|PMEVTYPER25_EL0}}
3591 # CHECK: mrs x9, {{pmevtyper26_el0|PMEVTYPER26_EL0}}
3592 # CHECK: mrs x9, {{pmevtyper27_el0|PMEVTYPER27_EL0}}
3593 # CHECK: mrs x9, {{pmevtyper28_el0|PMEVTYPER28_EL0}}
3594 # CHECK: mrs x9, {{pmevtyper29_el0|PMEVTYPER29_EL0}}
3595 # CHECK: mrs x9, {{pmevtyper30_el0|PMEVTYPER30_EL0}}
4151 # CHECK: mrs x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}}
4152 # CHECK: mrs x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}}
4153 # CHECK: msr {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12
4154 # CHECK: msr {{s3_7_c11_c13_7|S3_7_C11_C13_7}}, x5
4160 #------------------------------------------------------------------------------
4161 # Test and branch (immediate)
4162 #------------------------------------------------------------------------------
4164 # CHECK: tbz x12, #62, #0
4165 # CHECK: tbz x12, #62, #4
4166 # CHECK: tbz x12, #62, #-32768
4167 # CHECK: tbnz x12, #60, #32764
4173 #------------------------------------------------------------------------------
4174 # Unconditional branch (immediate)
4175 #------------------------------------------------------------------------------
4179 # CHECK: b #134217724
4184 #------------------------------------------------------------------------------
4185 # Unconditional branch (register)
4186 #------------------------------------------------------------------------------
projects / oota-llvm.git / blob