1 ;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding < %s | FileCheck %s
4 ;FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
5 ; should run on .s source files rather than using llc to generate the
6 ; assembly. There's also a large number of instruction encodings the
7 ; compiler never generates, so we need the integrated assembler to be
8 ; able to test those at all.
10 define i32 @foo(i32 %a, i32 %b) {
13 ; CHECK: trap @ encoding: [0xf0,0x00,0xf0,0x07]
14 ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
16 tail call void @llvm.trap()
20 define i32 @f2(i32 %a, i32 %b) {
23 ; CHECK: add r0, r1, r0 @ encoding: [0x00,0x00,0x81,0xe0]
24 ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
25 %add = add nsw i32 %b, %a
30 define i32 @f3(i32 %a, i32 %b) {
33 ; CHECK: add r0, r0, r1, lsl #3 @ encoding: [0x81,0x01,0x80,0xe0]
34 ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
36 %add = add nsw i32 %mul, %a
40 define i32 @f4(i32 %a, i32 %b) {
43 ; CHECK: add r0, r0, #254, 28 @ encoding: [0xfe,0x0e,0x80,0xe2]
45 ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
46 %add = add nsw i32 %a, 4064
50 define i32 @f5(i32 %a, i32 %b, i32 %c) {
53 ; CHECK: cmp r0, r1 @ encoding: [0x01,0x00,0x50,0xe1]
54 ; CHECK: mov r0, r2 @ encoding: [0x02,0x00,0xa0,0xe1]
55 ; CHECK: movgt r0, r1 @ encoding: [0x01,0x00,0xa0,0xc1]
56 %cmp = icmp sgt i32 %a, %b
57 %retval.0 = select i1 %cmp, i32 %b, i32 %c
61 define i64 @f6(i64 %a, i64 %b, i64 %c) {
64 ; CHECK: adds r0, r2, r0 @ encoding: [0x00,0x00,0x92,0xe0]
65 ; CHECK: adc r1, r3, r1 @ encoding: [0x01,0x10,0xa3,0xe0]
66 %add = add nsw i64 %b, %a
70 define i32 @f7(i32 %a, i32 %b) {
73 ; CHECK: uxtab r0, r0, r1 @ encoding: [0x71,0x00,0xe0,0xe6]
74 %and = and i32 %b, 255
75 %add = add i32 %and, %a
79 define i32 @f8(i32 %a) {
82 ; CHECK: movt r0, #42405 @ encoding: [0xa5,0x05,0x4a,0xe3]
83 %and = and i32 %a, 65535
84 %or = or i32 %and, -1515913216
91 ; CHECK: movw r0, #42405 @ encoding: [0xa5,0x05,0x0a,0xe3]
95 define i64 @f10(i64 %a) {
98 ; CHECK: asrs r1, r1, #1 @ encoding: [0xc1,0x10,0xb0,0xe1]
99 ; CHECK: rrx r0, r0 @ encoding: [0x60,0x00,0xa0,0xe1]
100 %shr = ashr i64 %a, 1
104 define i32 @f11([1 x i32] %A.coerce0, [1 x i32] %B.coerce0) {
107 ; CHECK: ubfx r1, r1, #8, #5 @ encoding: [0x51,0x14,0xe4,0xe7]
108 ; CHECK: sbfx r0, r0, #13, #7 @ encoding: [0xd0,0x06,0xa6,0xe7]
109 %tmp11 = extractvalue [1 x i32] %A.coerce0, 0
110 %tmp4 = extractvalue [1 x i32] %B.coerce0, 0
111 %0 = shl i32 %tmp11, 12
112 %bf.val.sext = ashr i32 %0, 25
113 %1 = lshr i32 %tmp4, 8
114 %bf.clear2 = and i32 %1, 31
115 %mul = mul nsw i32 %bf.val.sext, %bf.clear2
119 define i32 @f12(i32 %a) {
121 ; CHECK: bfc r0, #4, #20 @ encoding: [0x1f,0x02,0xd7,0xe7]
122 %tmp = and i32 %a, 4278190095
128 ; CHECK: mvn r0, #0 @ encoding: [0x00,0x00,0xe0,0xe3]
129 ; CHECK: mvn r1, #2, 2 @ encoding: [0x02,0x11,0xe0,0xe3]
131 ret i64 9223372036854775807
134 define i32 @f14(i32 %x, i32 %y) {
136 ; CHECK: smmul r0, r1, r0 @ encoding: [0x11,0xf0,0x50,0xe7]
137 %tmp = sext i32 %x to i64
138 %tmp1 = sext i32 %y to i64
139 %tmp2 = mul i64 %tmp1, %tmp
140 %tmp3 = lshr i64 %tmp2, 32
141 %tmp3.upgrd.1 = trunc i64 %tmp3 to i32
142 ret i32 %tmp3.upgrd.1
145 define i32 @f15(i32 %x, i32 %y) {
147 ; CHECK: umull r1, r0, r1, r0 @ encoding: [0x91,0x10,0x80,0xe0]
148 %tmp = zext i32 %x to i64
149 %tmp1 = zext i32 %y to i64
150 %tmp2 = mul i64 %tmp1, %tmp
151 %tmp3 = lshr i64 %tmp2, 32
152 %tmp3.upgrd.2 = trunc i64 %tmp3 to i32
153 ret i32 %tmp3.upgrd.2
156 define i32 @f16(i16 %x, i32 %y) {
158 ; CHECK: smulbt r0, r0, r1 @ encoding: [0xc0,0x01,0x60,0xe1]
159 %tmp1 = add i16 %x, 2
160 %tmp2 = sext i16 %tmp1 to i32
161 %tmp3 = ashr i32 %y, 16
162 %tmp4 = mul i32 %tmp2, %tmp3
166 define i32 @f17(i32 %x, i32 %y) {
168 ; CHECK: smultt r0, r1, r0 @ encoding: [0xe1,0x00,0x60,0xe1]
169 %tmp1 = ashr i32 %x, 16
170 %tmp3 = ashr i32 %y, 16
171 %tmp4 = mul i32 %tmp3, %tmp1
175 define i32 @f18(i32 %a, i16 %x, i32 %y) {
177 ; CHECK: smlabt r0, r1, r2, r0 @ encoding: [0xc1,0x02,0x00,0xe1]
178 %tmp = sext i16 %x to i32
179 %tmp2 = ashr i32 %y, 16
180 %tmp3 = mul i32 %tmp2, %tmp
181 %tmp5 = add i32 %tmp3, %a
185 declare void @llvm.trap() nounwind