test/MC/ARM/basic-arm-instructions.s

   1 @ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s
   2   .syntax unified
   3   .globl _func
   4
   5 @ Check that the assembler can handle the documented syntax from the ARM ARM.
   6 @ For complex constructs like shifter operands, check more thoroughly for them
   7 @ once then spot check that following instructions accept the form generally.
   8 @ This gives us good coverage while keeping the overall size of the test
   9 @ more reasonable.
  10
  11 _func:
  12 @ CHECK: _func
  13
  14 @------------------------------------------------------------------------------
  15 @ ADC (immediate)
  16 @------------------------------------------------------------------------------
  17   adc r1, r2, #0xf
  18   adc r1, r2, #0xf0
  19   adc r1, r2, #0xf00
  20   adc r1, r2, #0xf000
  21   adc r1, r2, #0xf0000
  22   adc r1, r2, #0xf00000
  23   adc r1, r2, #0xf000000
  24   adc r1, r2, #0xf0000000
  25   adc r1, r2, #0xf000000f
  26   adcs r1, r2, #0xf00
  27   adcseq r1, r2, #0xf00
  28   adceq r1, r2, #0xf00
  29
  30 @ CHECK: adc    r1, r2, #15             @ encoding: [0x0f,0x10,0xa2,0xe2]
  31 @ CHECK: adc    r1, r2, #240            @ encoding: [0xf0,0x10,0xa2,0xe2]
  32 @ CHECK: adc    r1, r2, #3840           @ encoding: [0x0f,0x1c,0xa2,0xe2]
  33 @ CHECK: adc    r1, r2, #61440          @ encoding: [0x0f,0x1a,0xa2,0xe2]
  34 @ CHECK: adc    r1, r2, #983040         @ encoding: [0x0f,0x18,0xa2,0xe2]
  35 @ CHECK: adc    r1, r2, #15728640       @ encoding: [0x0f,0x16,0xa2,0xe2]
  36 @ CHECK: adc    r1, r2, #251658240      @ encoding: [0x0f,0x14,0xa2,0xe2]
  37 @ CHECK: adc    r1, r2, #4026531840     @ encoding: [0x0f,0x12,0xa2,0xe2]
  38 @ CHECK: adc    r1, r2, #4026531855     @ encoding: [0xff,0x12,0xa2,0xe2]
  39
  40 @ CHECK: adcs   r1, r2, #3840           @ encoding: [0x0f,0x1c,0xb2,0xe2]
  41 @ CHECK: adcseq r1, r2, #3840           @ encoding: [0x0f,0x1c,0xb2,0x02]
  42 @ CHECK: adceq  r1, r2, #3840           @ encoding: [0x0f,0x1c,0xa2,0x02]
  43
  44 @------------------------------------------------------------------------------
  45 @ ADC (register)
  46 @ ADC (shifted register)
  47 @------------------------------------------------------------------------------
  48   adc r4, r5, r6
  49   @ Constant shifts
  50   adc r4, r5, r6, lsl #1
  51   adc r4, r5, r6, lsl #31
  52   adc r4, r5, r6, lsr #1
  53   adc r4, r5, r6, lsr #31
  54   adc r4, r5, r6, lsr #32
  55   adc r4, r5, r6, asr #1
  56   adc r4, r5, r6, asr #31
  57   adc r4, r5, r6, asr #32
  58   adc r4, r5, r6, ror #1
  59   adc r4, r5, r6, ror #31
  60
  61   @ Register shifts
  62   adc r6, r7, r8, lsl r9
  63   adc r6, r7, r8, lsr r9
  64   adc r6, r7, r8, asr r9
  65   adc r6, r7, r8, ror r9
  66   adc r4, r5, r6, rrx
  67
  68   @ Destination register is optional
  69   adc r5, r6
  70   adc r4, r5, lsl #1
  71   adc r4, r5, lsl #31
  72   adc r4, r5, lsr #1
  73   adc r4, r5, lsr #31
  74   adc r4, r5, lsr #32
  75   adc r4, r5, asr #1
  76   adc r4, r5, asr #31
  77   adc r4, r5, asr #32
  78   adc r4, r5, ror #1
  79   adc r4, r5, ror #31
  80   adc r4, r5, rrx
  81   adc r6, r7, lsl r9
  82   adc r6, r7, lsr r9
  83   adc r6, r7, asr r9
  84   adc r6, r7, ror r9
  85   adc r4, r5, rrx
  86
  87 @ CHECK: adc    r4, r5, r6              @ encoding: [0x06,0x40,0xa5,0xe0]
  88
  89 @ CHECK: adc    r4, r5, r6, lsl #1      @ encoding: [0x86,0x40,0xa5,0xe0]
  90 @ CHECK: adc    r4, r5, r6, lsl #31     @ encoding: [0x86,0x4f,0xa5,0xe0]
  91 @ CHECK: adc    r4, r5, r6, lsr #1      @ encoding: [0xa6,0x40,0xa5,0xe0]
  92 @ CHECK: adc    r4, r5, r6, lsr #31     @ encoding: [0xa6,0x4f,0xa5,0xe0]
  93 @ CHECK: adc    r4, r5, r6, lsr #32     @ encoding: [0x26,0x40,0xa5,0xe0]
  94 @ CHECK: adc    r4, r5, r6, asr #1      @ encoding: [0xc6,0x40,0xa5,0xe0]
  95 @ CHECK: adc    r4, r5, r6, asr #31     @ encoding: [0xc6,0x4f,0xa5,0xe0]
  96 @ CHECK: adc    r4, r5, r6, asr #32     @ encoding: [0x46,0x40,0xa5,0xe0]
  97 @ CHECK: adc    r4, r5, r6, ror #1      @ encoding: [0xe6,0x40,0xa5,0xe0]
  98 @ CHECK: adc    r4, r5, r6, ror #31     @ encoding: [0xe6,0x4f,0xa5,0xe0]
  99
 100 @ CHECK: adc    r6, r7, r8, lsl r9      @ encoding: [0x18,0x69,0xa7,0xe0]
 101 @ CHECK: adc    r6, r7, r8, lsr r9      @ encoding: [0x38,0x69,0xa7,0xe0]
 102 @ CHECK: adc    r6, r7, r8, asr r9      @ encoding: [0x58,0x69,0xa7,0xe0]
 103 @ CHECK: adc    r6, r7, r8, ror r9      @ encoding: [0x78,0x69,0xa7,0xe0]
 104 @ CHECK: adc    r4, r5, r6, rrx         @ encoding: [0x66,0x40,0xa5,0xe0]
 105
 106 @ CHECK: adc    r5, r5, r6              @ encoding: [0x06,0x50,0xa5,0xe0]
 107 @ CHECK: adc    r4, r4, r5, lsl #1      @ encoding: [0x85,0x40,0xa4,0xe0]
 108 @ CHECK: adc    r4, r4, r5, lsl #31     @ encoding: [0x85,0x4f,0xa4,0xe0]
 109 @ CHECK: adc    r4, r4, r5, lsr #1      @ encoding: [0xa5,0x40,0xa4,0xe0]
 110 @ CHECK: adc    r4, r4, r5, lsr #31     @ encoding: [0xa5,0x4f,0xa4,0xe0]
 111 @ CHECK: adc    r4, r4, r5, lsr #32     @ encoding: [0x25,0x40,0xa4,0xe0]
 112 @ CHECK: adc    r4, r4, r5, asr #1      @ encoding: [0xc5,0x40,0xa4,0xe0]
 113 @ CHECK: adc    r4, r4, r5, asr #31     @ encoding: [0xc5,0x4f,0xa4,0xe0]
 114 @ CHECK: adc    r4, r4, r5, asr #32     @ encoding: [0x45,0x40,0xa4,0xe0]
 115 @ CHECK: adc    r4, r4, r5, ror #1      @ encoding: [0xe5,0x40,0xa4,0xe0]
 116 @ CHECK: adc    r4, r4, r5, ror #31     @ encoding: [0xe5,0x4f,0xa4,0xe0]
 117 @ CHECK: adc    r4, r4, r5, rrx         @ encoding: [0x65,0x40,0xa4,0xe0]
 118 @ CHECK: adc    r6, r6, r7, lsl r9      @ encoding: [0x17,0x69,0xa6,0xe0]
 119 @ CHECK: adc    r6, r6, r7, lsr r9      @ encoding: [0x37,0x69,0xa6,0xe0]
 120 @ CHECK: adc    r6, r6, r7, asr r9      @ encoding: [0x57,0x69,0xa6,0xe0]
 121 @ CHECK: adc    r6, r6, r7, ror r9      @ encoding: [0x77,0x69,0xa6,0xe0]
 122 @ CHECK: adc    r4, r4, r5, rrx         @ encoding: [0x65,0x40,0xa4,0xe0]
 123
 124
 125 @------------------------------------------------------------------------------
 126 @ ADD
 127 @------------------------------------------------------------------------------
 128   add r4, r5, #0xf000
 129   add r4, r5, r6
 130   add r4, r5, r6, lsl #5
 131   add r4, r5, r6, lsr #5
 132   add r4, r5, r6, lsr #5
 133   add r4, r5, r6, asr #5
 134   add r4, r5, r6, ror #5
 135   add r6, r7, r8, lsl r9
 136   add r6, r7, r8, lsr r9
 137   add r6, r7, r8, asr r9
 138   add r6, r7, r8, ror r9
 139   add r4, r5, r6, rrx
 140
 141   @ destination register is optional
 142   add r5, #0xf000
 143   add r4, r5
 144   add r4, r5, lsl #5
 145   add r4, r5, lsr #5
 146   add r4, r5, lsr #5
 147   add r4, r5, asr #5
 148   add r4, r5, ror #5
 149   add r6, r7, lsl r9
 150   add r6, r7, lsr r9
 151   add r6, r7, asr r9
 152   add r6, r7, ror r9
 153   add r4, r5, rrx
 154
 155 @ CHECK: add    r4, r5, #61440          @ encoding: [0x0f,0x4a,0x85,0xe2]
 156 @ CHECK: add    r4, r5, r6              @ encoding: [0x06,0x40,0x85,0xe0]
 157 @ CHECK: add    r4, r5, r6, lsl #5      @ encoding: [0x86,0x42,0x85,0xe0]
 158 @ CHECK: add    r4, r5, r6, lsr #5      @ encoding: [0xa6,0x42,0x85,0xe0]
 159 @ CHECK: add    r4, r5, r6, lsr #5      @ encoding: [0xa6,0x42,0x85,0xe0]
 160 @ CHECK: add    r4, r5, r6, asr #5      @ encoding: [0xc6,0x42,0x85,0xe0]
 161 @ CHECK: add    r4, r5, r6, ror #5      @ encoding: [0xe6,0x42,0x85,0xe0]
 162 @ CHECK: add    r6, r7, r8, lsl r9      @ encoding: [0x18,0x69,0x87,0xe0]
 163 @ CHECK: add    r6, r7, r8, lsr r9      @ encoding: [0x38,0x69,0x87,0xe0]
 164 @ CHECK: add    r6, r7, r8, asr r9      @ encoding: [0x58,0x69,0x87,0xe0]
 165 @ CHECK: add    r6, r7, r8, ror r9      @ encoding: [0x78,0x69,0x87,0xe0]
 166 @ CHECK: add    r4, r5, r6, rrx         @ encoding: [0x66,0x40,0x85,0xe0]
 167
 168
 169 @ CHECK: add    r5, r5, #61440          @ encoding: [0x0f,0x5a,0x85,0xe2]
 170 @ CHECK: add    r4, r4, r5              @ encoding: [0x05,0x40,0x84,0xe0]
 171 @ CHECK: add    r4, r4, r5, lsl #5      @ encoding: [0x85,0x42,0x84,0xe0]
 172 @ CHECK: add    r4, r4, r5, lsr #5      @ encoding: [0xa5,0x42,0x84,0xe0]
 173 @ CHECK: add    r4, r4, r5, lsr #5      @ encoding: [0xa5,0x42,0x84,0xe0]
 174 @ CHECK: add    r4, r4, r5, asr #5      @ encoding: [0xc5,0x42,0x84,0xe0]
 175 @ CHECK: add    r4, r4, r5, ror #5      @ encoding: [0xe5,0x42,0x84,0xe0]
 176 @ CHECK: add    r6, r6, r7, lsl r9      @ encoding: [0x17,0x69,0x86,0xe0]
 177 @ CHECK: add    r6, r6, r7, lsr r9      @ encoding: [0x37,0x69,0x86,0xe0]
 178 @ CHECK: add    r6, r6, r7, asr r9      @ encoding: [0x57,0x69,0x86,0xe0]
 179 @ CHECK: add    r6, r6, r7, ror r9      @ encoding: [0x77,0x69,0x86,0xe0]
 180 @ CHECK: add    r4, r4, r5, rrx         @ encoding: [0x65,0x40,0x84,0xe0]