1 @ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s
5 @ Check that the assembler can handle the documented syntax from the ARM ARM.
6 @ For complex constructs like shifter operands, check more thoroughly for them
7 @ once then spot check that following instructions accept the form generally.
8 @ This gives us good coverage while keeping the overall size of the test
14 @------------------------------------------------------------------------------
16 @------------------------------------------------------------------------------
23 adc r1, r2, #0xf000000
24 adc r1, r2, #0xf0000000
25 adc r1, r2, #0xf000000f
30 @ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2]
31 @ CHECK: adc r1, r2, #240 @ encoding: [0xf0,0x10,0xa2,0xe2]
32 @ CHECK: adc r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0xe2]
33 @ CHECK: adc r1, r2, #61440 @ encoding: [0x0f,0x1a,0xa2,0xe2]
34 @ CHECK: adc r1, r2, #983040 @ encoding: [0x0f,0x18,0xa2,0xe2]
35 @ CHECK: adc r1, r2, #15728640 @ encoding: [0x0f,0x16,0xa2,0xe2]
36 @ CHECK: adc r1, r2, #251658240 @ encoding: [0x0f,0x14,0xa2,0xe2]
37 @ CHECK: adc r1, r2, #4026531840 @ encoding: [0x0f,0x12,0xa2,0xe2]
38 @ CHECK: adc r1, r2, #4026531855 @ encoding: [0xff,0x12,0xa2,0xe2]
40 @ CHECK: adcs r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0xe2]
41 @ CHECK: adcseq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0x02]
42 @ CHECK: adceq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0x02]
44 @------------------------------------------------------------------------------
46 @ ADC (shifted register)
47 @------------------------------------------------------------------------------
50 adc r4, r5, r6, lsl #1
51 adc r4, r5, r6, lsl #31
52 adc r4, r5, r6, lsr #1
53 adc r4, r5, r6, lsr #31
54 adc r4, r5, r6, lsr #32
55 adc r4, r5, r6, asr #1
56 adc r4, r5, r6, asr #31
57 adc r4, r5, r6, asr #32
58 adc r4, r5, r6, ror #1
59 adc r4, r5, r6, ror #31
62 adc r6, r7, r8, lsl r9
63 adc r6, r7, r8, lsr r9
64 adc r6, r7, r8, asr r9
65 adc r6, r7, r8, ror r9
68 @ Destination register is optional
87 @ CHECK: adc r4, r5, r6 @ encoding: [0x06,0x40,0xa5,0xe0]
89 @ CHECK: adc r4, r5, r6, lsl #1 @ encoding: [0x86,0x40,0xa5,0xe0]
90 @ CHECK: adc r4, r5, r6, lsl #31 @ encoding: [0x86,0x4f,0xa5,0xe0]
91 @ CHECK: adc r4, r5, r6, lsr #1 @ encoding: [0xa6,0x40,0xa5,0xe0]
92 @ CHECK: adc r4, r5, r6, lsr #31 @ encoding: [0xa6,0x4f,0xa5,0xe0]
93 @ CHECK: adc r4, r5, r6, lsr #32 @ encoding: [0x26,0x40,0xa5,0xe0]
94 @ CHECK: adc r4, r5, r6, asr #1 @ encoding: [0xc6,0x40,0xa5,0xe0]
95 @ CHECK: adc r4, r5, r6, asr #31 @ encoding: [0xc6,0x4f,0xa5,0xe0]
96 @ CHECK: adc r4, r5, r6, asr #32 @ encoding: [0x46,0x40,0xa5,0xe0]
97 @ CHECK: adc r4, r5, r6, ror #1 @ encoding: [0xe6,0x40,0xa5,0xe0]
98 @ CHECK: adc r4, r5, r6, ror #31 @ encoding: [0xe6,0x4f,0xa5,0xe0]
100 @ CHECK: adc r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0xa7,0xe0]
101 @ CHECK: adc r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0xa7,0xe0]
102 @ CHECK: adc r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0xa7,0xe0]
103 @ CHECK: adc r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0xa7,0xe0]
104 @ CHECK: adc r4, r5, r6, rrx @ encoding: [0x66,0x40,0xa5,0xe0]
106 @ CHECK: adc r5, r5, r6 @ encoding: [0x06,0x50,0xa5,0xe0]
107 @ CHECK: adc r4, r4, r5, lsl #1 @ encoding: [0x85,0x40,0xa4,0xe0]
108 @ CHECK: adc r4, r4, r5, lsl #31 @ encoding: [0x85,0x4f,0xa4,0xe0]
109 @ CHECK: adc r4, r4, r5, lsr #1 @ encoding: [0xa5,0x40,0xa4,0xe0]
110 @ CHECK: adc r4, r4, r5, lsr #31 @ encoding: [0xa5,0x4f,0xa4,0xe0]
111 @ CHECK: adc r4, r4, r5, lsr #32 @ encoding: [0x25,0x40,0xa4,0xe0]
112 @ CHECK: adc r4, r4, r5, asr #1 @ encoding: [0xc5,0x40,0xa4,0xe0]
113 @ CHECK: adc r4, r4, r5, asr #31 @ encoding: [0xc5,0x4f,0xa4,0xe0]
114 @ CHECK: adc r4, r4, r5, asr #32 @ encoding: [0x45,0x40,0xa4,0xe0]
115 @ CHECK: adc r4, r4, r5, ror #1 @ encoding: [0xe5,0x40,0xa4,0xe0]
116 @ CHECK: adc r4, r4, r5, ror #31 @ encoding: [0xe5,0x4f,0xa4,0xe0]
117 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
118 @ CHECK: adc r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0xa6,0xe0]
119 @ CHECK: adc r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0xa6,0xe0]
120 @ CHECK: adc r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0xa6,0xe0]
121 @ CHECK: adc r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0xa6,0xe0]
122 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
125 @------------------------------------------------------------------------------
127 @------------------------------------------------------------------------------
130 add r4, r5, r6, lsl #5
131 add r4, r5, r6, lsr #5
132 add r4, r5, r6, lsr #5
133 add r4, r5, r6, asr #5
134 add r4, r5, r6, ror #5
135 add r6, r7, r8, lsl r9
136 add r6, r7, r8, lsr r9
137 add r6, r7, r8, asr r9
138 add r6, r7, r8, ror r9
141 @ destination register is optional
155 @ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2]
156 @ CHECK: add r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe0]
157 @ CHECK: add r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe0]
158 @ CHECK: add r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe0]
159 @ CHECK: add r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe0]
160 @ CHECK: add r4, r5, r6, asr #5 @ encoding: [0xc6,0x42,0x85,0xe0]
161 @ CHECK: add r4, r5, r6, ror #5 @ encoding: [0xe6,0x42,0x85,0xe0]
162 @ CHECK: add r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0x87,0xe0]
163 @ CHECK: add r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0x87,0xe0]
164 @ CHECK: add r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0x87,0xe0]
165 @ CHECK: add r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0x87,0xe0]
166 @ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0]
169 @ CHECK: add r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe2]
170 @ CHECK: add r4, r4, r5 @ encoding: [0x05,0x40,0x84,0xe0]
171 @ CHECK: add r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x84,0xe0]
172 @ CHECK: add r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe0]
173 @ CHECK: add r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe0]
174 @ CHECK: add r4, r4, r5, asr #5 @ encoding: [0xc5,0x42,0x84,0xe0]
175 @ CHECK: add r4, r4, r5, ror #5 @ encoding: [0xe5,0x42,0x84,0xe0]
176 @ CHECK: add r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0x86,0xe0]
177 @ CHECK: add r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0x86,0xe0]
178 @ CHECK: add r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x86,0xe0]
179 @ CHECK: add r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x86,0xe0]
180 @ CHECK: add r4, r4, r5, rrx @ encoding: [0x65,0x40,0x84,0xe0]
183 @------------------------------------------------------------------------------
185 @------------------------------------------------------------------------------
188 and r10, r1, r6, lsl #10
189 and r10, r1, r6, lsr #10
190 and r10, r1, r6, lsr #10
191 and r10, r1, r6, asr #10
192 and r10, r1, r6, ror #10
193 and r6, r7, r8, lsl r2
194 and r6, r7, r8, lsr r2
195 and r6, r7, r8, asr r2
196 and r6, r7, r8, ror r2
199 @ destination register is optional
213 @ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2]
214 @ CHECK: and r10, r1, r6 @ encoding: [0x06,0xa0,0x01,0xe0]
215 @ CHECK: and r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0x01,0xe0]
216 @ CHECK: and r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0x01,0xe0]
217 @ CHECK: and r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0x01,0xe0]
218 @ CHECK: and r10, r1, r6, asr #10 @ encoding: [0x46,0xa5,0x01,0xe0]
219 @ CHECK: and r10, r1, r6, ror #10 @ encoding: [0x66,0xa5,0x01,0xe0]
220 @ CHECK: and r6, r7, r8, lsl r2 @ encoding: [0x18,0x62,0x07,0xe0]
221 @ CHECK: and r6, r7, r8, lsr r2 @ encoding: [0x38,0x62,0x07,0xe0]
222 @ CHECK: and r6, r7, r8, asr r2 @ encoding: [0x58,0x62,0x07,0xe0]
223 @ CHECK: and r6, r7, r8, ror r2 @ encoding: [0x78,0x62,0x07,0xe0]
224 @ CHECK: and r10, r1, r6, rrx @ encoding: [0x66,0xa0,0x01,0xe0]
226 @ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2]
227 @ CHECK: and r10, r10, r1 @ encoding: [0x01,0xa0,0x0a,0xe0]
228 @ CHECK: and r10, r10, r1, lsl #10 @ encoding: [0x01,0xa5,0x0a,0xe0]
229 @ CHECK: and r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0x0a,0xe0]
230 @ CHECK: and r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0x0a,0xe0]
231 @ CHECK: and r10, r10, r1, asr #10 @ encoding: [0x41,0xa5,0x0a,0xe0]
232 @ CHECK: and r10, r10, r1, ror #10 @ encoding: [0x61,0xa5,0x0a,0xe0]
233 @ CHECK: and r6, r6, r7, lsl r2 @ encoding: [0x17,0x62,0x06,0xe0]
234 @ CHECK: and r6, r6, r7, lsr r2 @ encoding: [0x37,0x62,0x06,0xe0]
235 @ CHECK: and r6, r6, r7, asr r2 @ encoding: [0x57,0x62,0x06,0xe0]
236 @ CHECK: and r6, r6, r7, ror r2 @ encoding: [0x77,0x62,0x06,0xe0]
237 @ CHECK: and r10, r10, r1, rrx @ encoding: [0x61,0xa0,0x0a,0xe0]