2 ; RUN: llc %s -march=x86 -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched 2>&1 | FileCheck %s
4 ; Test scheduling of copy instructions.
6 ; Argument copies should be hoisted to the top of the block.
7 ; Return copies should be sunk to the end.
8 ; MUL_HiLo PhysReg use copies should be just above the mul.
9 ; MUL_HiLo PhysReg def copies should be just below the mul.
11 ; CHECK: *** Final schedule for BB#1 ***
12 ; CHECK-NEXT: %EAX<def> = COPY
13 ; CHECK: MUL32r %vreg{{[0-6]+}}, %EAX<imp-def>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use>;
14 ; CHECK-NEXT: COPY %EAX;
15 ; CHECK-NEXT: COPY %EDX;
17 define i64 @mulhoist(i32 %a, i32 %b) #0 {
22 %convb = sitofp i32 %b to float
23 ; Generates an iMUL64r to legalize types.
24 %aa = zext i32 %a to i64
25 %mul = mul i64 %aa, 74383
26 ; Do some dependent long latency stuff.
27 %trunc = trunc i64 %mul to i32
28 %convm = sitofp i32 %trunc to float
29 %divm = fdiv float %convm, 0.75
30 ;%addmb = fadd float %divm, %convb
31 ;%divmb = fdiv float %addmb, 0.125
32 ; Do some independent long latency stuff.
33 %conva = sitofp i32 %a to float
34 %diva = fdiv float %conva, 0.75
35 %addab = fadd float %diva, %convb
36 %divab = fdiv float %addab, 0.125
40 %val = fptosi float %divab to i64
41 %add = add i64 %mul, %val
45 attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
47 !0 = metadata !{metadata !"float", metadata !1}
48 !1 = metadata !{metadata !"omnipotent char", metadata !2}
49 !2 = metadata !{metadata !"Simple C/C++ TBAA"}