1 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
2 ; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
4 ; Full strength reduction wouldn't reduce register pressure, so LSR should
5 ; stick with indexing here.
7 ; FIXME: This is worse off from disabling of scheduler 2-address hack.
8 ; CHECK: movaps (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]]
9 ; CHECK: leaq 4(%rax), %{{rcx|r9}}
11 ; CHECK: orps {{%xmm[0-9]+}}, [[X4:%xmm[0-9]+]]
12 ; CHECK: movaps [[X4]], (%{{rdi|rcx}},%rax,4)
13 ; CHECK: cmpl %{{ecx|r9d}}, (%{{rdx|r8}})
16 define void @vvfloorf(float* nocapture %y, float* nocapture %x, i32* nocapture %n) nounwind {
18 %0 = load i32* %n, align 4
19 %1 = icmp sgt i32 %0, 0
20 br i1 %1, label %bb, label %return
23 %indvar = phi i64 [ %indvar.next, %bb ], [ 0, %entry ]
24 %tmp = shl i64 %indvar, 2
25 %scevgep = getelementptr float* %y, i64 %tmp
26 %scevgep9 = bitcast float* %scevgep to <4 x float>*
27 %scevgep10 = getelementptr float* %x, i64 %tmp
28 %scevgep1011 = bitcast float* %scevgep10 to <4 x float>*
29 %2 = load <4 x float>* %scevgep1011, align 16
30 %3 = bitcast <4 x float> %2 to <4 x i32>
31 %4 = and <4 x i32> %3, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
32 %5 = bitcast <4 x i32> %4 to <4 x float>
33 %6 = and <4 x i32> %3, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
34 %7 = tail call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %5, <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>, i8 5) nounwind
35 %tmp.i4 = bitcast <4 x float> %7 to <4 x i32>
36 %8 = xor <4 x i32> %tmp.i4, <i32 -1, i32 -1, i32 -1, i32 -1>
37 %9 = and <4 x i32> %8, <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200>
38 %10 = or <4 x i32> %9, %6
39 %11 = bitcast <4 x i32> %10 to <4 x float>
40 %12 = fadd <4 x float> %2, %11
41 %13 = fsub <4 x float> %12, %11
42 %14 = tail call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %2, <4 x float> %13, i8 1) nounwind
43 %15 = bitcast <4 x float> %14 to <4 x i32>
44 %16 = tail call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %15) nounwind readnone
45 %17 = fadd <4 x float> %13, %16
46 %tmp.i = bitcast <4 x float> %17 to <4 x i32>
47 %18 = or <4 x i32> %tmp.i, %6
48 %19 = bitcast <4 x i32> %18 to <4 x float>
49 store <4 x float> %19, <4 x float>* %scevgep9, align 16
50 %tmp12 = add i64 %tmp, 4
51 %tmp13 = trunc i64 %tmp12 to i32
52 %20 = load i32* %n, align 4
53 %21 = icmp sgt i32 %20, %tmp13
54 %indvar.next = add i64 %indvar, 1
55 br i1 %21, label %bb, label %return
61 declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone
63 declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone