1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s
3 declare i32 @llvm.x86.avx512.kortestz.w(i16, i16) nounwind readnone
4 ; CHECK-LABEL: test_kortestz
7 define i32 @test_kortestz(i16 %a0, i16 %a1) {
8 %res = call i32 @llvm.x86.avx512.kortestz.w(i16 %a0, i16 %a1)
12 declare i32 @llvm.x86.avx512.kortestc.w(i16, i16) nounwind readnone
13 ; CHECK-LABEL: test_kortestc
16 define i32 @test_kortestc(i16 %a0, i16 %a1) {
17 %res = call i32 @llvm.x86.avx512.kortestc.w(i16 %a0, i16 %a1)
21 declare i16 @llvm.x86.avx512.kand.w(i16, i16) nounwind readnone
22 ; CHECK-LABEL: test_kand
25 define i16 @test_kand(i16 %a0, i16 %a1) {
26 %t1 = call i16 @llvm.x86.avx512.kand.w(i16 %a0, i16 8)
27 %t2 = call i16 @llvm.x86.avx512.kand.w(i16 %t1, i16 %a1)
31 declare i16 @llvm.x86.avx512.knot.w(i16) nounwind readnone
32 ; CHECK-LABEL: test_knot
34 define i16 @test_knot(i16 %a0) {
35 %res = call i16 @llvm.x86.avx512.knot.w(i16 %a0)
39 declare i16 @llvm.x86.avx512.kunpck.bw(i16, i16) nounwind readnone
41 ; CHECK-LABEL: unpckbw_test
44 define i16 @unpckbw_test(i16 %a0, i16 %a1) {
45 %res = call i16 @llvm.x86.avx512.kunpck.bw(i16 %a0, i16 %a1)
49 define <16 x float> @test_rcp_ps_512(<16 x float> %a0) {
50 ; CHECK: vrcp14ps {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x4c,0xc0]
51 %res = call <16 x float> @llvm.x86.avx512.rcp14.ps.512(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1) ; <<16 x float>> [#uses=1]
54 declare <16 x float> @llvm.x86.avx512.rcp14.ps.512(<16 x float>, <16 x float>, i16) nounwind readnone
56 define <8 x double> @test_rcp_pd_512(<8 x double> %a0) {
57 ; CHECK: vrcp14pd {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x4c,0xc0]
58 %res = call <8 x double> @llvm.x86.avx512.rcp14.pd.512(<8 x double> %a0, <8 x double> zeroinitializer, i8 -1) ; <<8 x double>> [#uses=1]
61 declare <8 x double> @llvm.x86.avx512.rcp14.pd.512(<8 x double>, <8 x double>, i8) nounwind readnone
63 define <16 x float> @test_rcp28_ps_512(<16 x float> %a0) {
64 ; CHECK: vrcp28ps {sae}, {{.*}}encoding: [0x62,0xf2,0x7d,0x18,0xca,0xc0]
65 %res = call <16 x float> @llvm.x86.avx512.rcp28.ps(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1, i32 8) ; <<16 x float>> [#uses=1]
68 declare <16 x float> @llvm.x86.avx512.rcp28.ps(<16 x float>, <16 x float>, i16, i32) nounwind readnone
70 define <8 x double> @test_rcp28_pd_512(<8 x double> %a0) {
71 ; CHECK: vrcp28pd {sae}, {{.*}}encoding: [0x62,0xf2,0xfd,0x18,0xca,0xc0]
72 %res = call <8 x double> @llvm.x86.avx512.rcp28.pd(<8 x double> %a0, <8 x double> zeroinitializer, i8 -1, i32 8) ; <<8 x double>> [#uses=1]
75 declare <8 x double> @llvm.x86.avx512.rcp28.pd(<8 x double>, <8 x double>, i8, i32) nounwind readnone
77 declare <8 x double> @llvm.x86.avx512.mask.rndscale.pd.512(<8 x double>, i32, <8 x double>, i8, i32)
79 define <8 x double> @test7(<8 x double> %a) {
80 ; CHECK: vrndscalepd {{.*}}encoding: [0x62,0xf3,0xfd,0x48,0x09,0xc0,0x0b]
81 %res = call <8 x double> @llvm.x86.avx512.mask.rndscale.pd.512(<8 x double> %a, i32 11, <8 x double> %a, i8 -1, i32 4)
85 declare <16 x float> @llvm.x86.avx512.mask.rndscale.ps.512(<16 x float>, i32, <16 x float>, i16, i32)
87 define <16 x float> @test8(<16 x float> %a) {
88 ; CHECK: vrndscaleps {{.*}}encoding: [0x62,0xf3,0x7d,0x48,0x08,0xc0,0x0b]
89 %res = call <16 x float> @llvm.x86.avx512.mask.rndscale.ps.512(<16 x float> %a, i32 11, <16 x float> %a, i16 -1, i32 4)
93 define <16 x float> @test_rsqrt_ps_512(<16 x float> %a0) {
94 ; CHECK: vrsqrt14ps {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x4e,0xc0]
95 %res = call <16 x float> @llvm.x86.avx512.rsqrt14.ps.512(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1) ; <<16 x float>> [#uses=1]
98 declare <16 x float> @llvm.x86.avx512.rsqrt14.ps.512(<16 x float>, <16 x float>, i16) nounwind readnone
100 define <16 x float> @test_rsqrt28_ps_512(<16 x float> %a0) {
101 ; CHECK: vrsqrt28ps {sae}, {{.*}}encoding: [0x62,0xf2,0x7d,0x18,0xcc,0xc0]
102 %res = call <16 x float> @llvm.x86.avx512.rsqrt28.ps(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1, i32 8) ; <<16 x float>> [#uses=1]
103 ret <16 x float> %res
105 declare <16 x float> @llvm.x86.avx512.rsqrt28.ps(<16 x float>, <16 x float>, i16, i32) nounwind readnone
107 define <4 x float> @test_rsqrt14_ss(<4 x float> %a0) {
108 ; CHECK: vrsqrt14ss {{.*}}encoding: [0x62,0xf2,0x7d,0x08,0x4f,0xc0]
109 %res = call <4 x float> @llvm.x86.avx512.rsqrt14.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 -1) ; <<4 x float>> [#uses=1]
112 declare <4 x float> @llvm.x86.avx512.rsqrt14.ss(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone
114 define <4 x float> @test_rsqrt28_ss(<4 x float> %a0) {
115 ; CHECK: vrsqrt28ss {sae}, {{.*}}encoding: [0x62,0xf2,0x7d,0x18,0xcd,0xc0]
116 %res = call <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 -1, i32 8) ; <<4 x float>> [#uses=1]
119 declare <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone
121 define <4 x float> @test_rcp14_ss(<4 x float> %a0) {
122 ; CHECK: vrcp14ss {{.*}}encoding: [0x62,0xf2,0x7d,0x08,0x4d,0xc0]
123 %res = call <4 x float> @llvm.x86.avx512.rcp14.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 -1) ; <<4 x float>> [#uses=1]
126 declare <4 x float> @llvm.x86.avx512.rcp14.ss(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone
128 define <4 x float> @test_rcp28_ss(<4 x float> %a0) {
129 ; CHECK: vrcp28ss {sae}, {{.*}}encoding: [0x62,0xf2,0x7d,0x18,0xcb,0xc0]
130 %res = call <4 x float> @llvm.x86.avx512.rcp28.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 -1, i32 8) ; <<4 x float>> [#uses=1]
133 declare <4 x float> @llvm.x86.avx512.rcp28.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone
135 define <8 x double> @test_sqrt_pd_512(<8 x double> %a0) {
137 %res = call <8 x double> @llvm.x86.avx512.sqrt.pd.512(<8 x double> %a0, <8 x double> zeroinitializer, i8 -1, i32 4) ; <<8 x double>> [#uses=1]
138 ret <8 x double> %res
140 declare <8 x double> @llvm.x86.avx512.sqrt.pd.512(<8 x double>, <8 x double>, i8, i32) nounwind readnone
142 define <16 x float> @test_sqrt_ps_512(<16 x float> %a0) {
144 %res = call <16 x float> @llvm.x86.avx512.sqrt.ps.512(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1, i32 4) ; <<16 x float>> [#uses=1]
145 ret <16 x float> %res
147 declare <16 x float> @llvm.x86.avx512.sqrt.ps.512(<16 x float>, <16 x float>, i16, i32) nounwind readnone
149 define <4 x float> @test_sqrt_ss(<4 x float> %a0, <4 x float> %a1) {
150 ; CHECK: vsqrtss {{.*}}encoding: [0x62
151 %res = call <4 x float> @llvm.x86.avx512.sqrt.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
154 declare <4 x float> @llvm.x86.avx512.sqrt.ss(<4 x float>, <4 x float>) nounwind readnone
156 define <2 x double> @test_sqrt_sd(<2 x double> %a0, <2 x double> %a1) {
157 ; CHECK: vsqrtsd {{.*}}encoding: [0x62
158 %res = call <2 x double> @llvm.x86.avx512.sqrt.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
159 ret <2 x double> %res
161 declare <2 x double> @llvm.x86.avx512.sqrt.sd(<2 x double>, <2 x double>) nounwind readnone
163 define i64 @test_x86_sse2_cvtsd2si64(<2 x double> %a0) {
164 ; CHECK: vcvtsd2si {{.*}}encoding: [0x62
165 %res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
168 declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
170 define <2 x double> @test_x86_sse2_cvtsi642sd(<2 x double> %a0, i64 %a1) {
171 ; CHECK: vcvtsi2sdq {{.*}}encoding: [0x62
172 %res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1]
173 ret <2 x double> %res
175 declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone
177 define <2 x double> @test_x86_avx512_cvtusi642sd(<2 x double> %a0, i64 %a1) {
178 ; CHECK: vcvtusi2sdq {{.*}}encoding: [0x62
179 %res = call <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1]
180 ret <2 x double> %res
182 declare <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double>, i64) nounwind readnone
184 define i64 @test_x86_sse2_cvttsd2si64(<2 x double> %a0) {
185 ; CHECK: vcvttsd2si {{.*}}encoding: [0x62
186 %res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
189 declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
192 define i64 @test_x86_sse_cvtss2si64(<4 x float> %a0) {
193 ; CHECK: vcvtss2si {{.*}}encoding: [0x62
194 %res = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %a0) ; <i64> [#uses=1]
197 declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) nounwind readnone
200 define <4 x float> @test_x86_sse_cvtsi642ss(<4 x float> %a0, i64 %a1) {
201 ; CHECK: vcvtsi2ssq {{.*}}encoding: [0x62
202 %res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0, i64 %a1) ; <<4 x float>> [#uses=1]
205 declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone
208 define i64 @test_x86_sse_cvttss2si64(<4 x float> %a0) {
209 ; CHECK: vcvttss2si {{.*}}encoding: [0x62
210 %res = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %a0) ; <i64> [#uses=1]
213 declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone
215 define i64 @test_x86_avx512_cvtsd2usi64(<2 x double> %a0) {
216 ; CHECK: vcvtsd2usi {{.*}}encoding: [0x62
217 %res = call i64 @llvm.x86.avx512.cvtsd2usi64(<2 x double> %a0) ; <i64> [#uses=1]
220 declare i64 @llvm.x86.avx512.cvtsd2usi64(<2 x double>) nounwind readnone
222 define <16 x float> @test_x86_vcvtph2ps_512(<16 x i16> %a0) {
223 ; CHECK: vcvtph2ps %ymm0, %zmm0 ## encoding: [0x62,0xf2,0x7d,0x48,0x13,0xc0]
224 %res = call <16 x float> @llvm.x86.avx512.mask.vcvtph2ps.512(<16 x i16> %a0, <16 x float> zeroinitializer, i16 -1, i32 4)
225 ret <16 x float> %res
227 declare <16 x float> @llvm.x86.avx512.mask.vcvtph2ps.512(<16 x i16>, <16 x float>, i16, i32) nounwind readonly
230 define <16 x i16> @test_x86_vcvtps2ph_256(<16 x float> %a0) {
231 ; CHECK: vcvtps2ph $2, %zmm0, %ymm0 ## encoding: [0x62,0xf3,0x7d,0x48,0x1d,0xc0,0x02]
232 %res = call <16 x i16> @llvm.x86.avx512.mask.vcvtps2ph.512(<16 x float> %a0, i32 2, <16 x i16> zeroinitializer, i16 -1)
236 declare <16 x i16> @llvm.x86.avx512.mask.vcvtps2ph.512(<16 x float>, i32, <16 x i16>, i16) nounwind readonly
238 define <16 x float> @test_x86_vbroadcast_ss_512(i8* %a0) {
239 ; CHECK: vbroadcastss
240 %res = call <16 x float> @llvm.x86.avx512.vbroadcast.ss.512(i8* %a0) ; <<16 x float>> [#uses=1]
241 ret <16 x float> %res
243 declare <16 x float> @llvm.x86.avx512.vbroadcast.ss.512(i8*) nounwind readonly
245 define <8 x double> @test_x86_vbroadcast_sd_512(i8* %a0) {
246 ; CHECK: vbroadcastsd
247 %res = call <8 x double> @llvm.x86.avx512.vbroadcast.sd.512(i8* %a0) ; <<8 x double>> [#uses=1]
248 ret <8 x double> %res
250 declare <8 x double> @llvm.x86.avx512.vbroadcast.sd.512(i8*) nounwind readonly
252 define <16 x float> @test_x86_vbroadcast_ss_ps_512(<4 x float> %a0) {
253 ; CHECK: vbroadcastss
254 %res = call <16 x float> @llvm.x86.avx512.vbroadcast.ss.ps.512(<4 x float> %a0) ; <<16 x float>> [#uses=1]
255 ret <16 x float> %res
257 declare <16 x float> @llvm.x86.avx512.vbroadcast.ss.ps.512(<4 x float>) nounwind readonly
259 define <8 x double> @test_x86_vbroadcast_sd_pd_512(<2 x double> %a0) {
260 ; CHECK: vbroadcastsd
261 %res = call <8 x double> @llvm.x86.avx512.vbroadcast.sd.pd.512(<2 x double> %a0) ; <<8 x double>> [#uses=1]
262 ret <8 x double> %res
264 declare <8 x double> @llvm.x86.avx512.vbroadcast.sd.pd.512(<2 x double>) nounwind readonly
266 define <16 x i32> @test_x86_pbroadcastd_512(<4 x i32> %a0) {
267 ; CHECK: vpbroadcastd
268 %res = call <16 x i32> @llvm.x86.avx512.pbroadcastd.512(<4 x i32> %a0) ; <<16 x i32>> [#uses=1]
271 declare <16 x i32> @llvm.x86.avx512.pbroadcastd.512(<4 x i32>) nounwind readonly
273 define <16 x i32> @test_x86_pbroadcastd_i32_512(i32 %a0) {
274 ; CHECK: vpbroadcastd
275 %res = call <16 x i32> @llvm.x86.avx512.pbroadcastd.i32.512(i32 %a0) ; <<16 x i32>> [#uses=1]
278 declare <16 x i32> @llvm.x86.avx512.pbroadcastd.i32.512(i32) nounwind readonly
280 define <8 x i64> @test_x86_pbroadcastq_512(<2 x i64> %a0) {
281 ; CHECK: vpbroadcastq
282 %res = call <8 x i64> @llvm.x86.avx512.pbroadcastq.512(<2 x i64> %a0) ; <<8 x i64>> [#uses=1]
285 declare <8 x i64> @llvm.x86.avx512.pbroadcastq.512(<2 x i64>) nounwind readonly
287 define <8 x i64> @test_x86_pbroadcastq_i64_512(i64 %a0) {
288 ; CHECK: vpbroadcastq
289 %res = call <8 x i64> @llvm.x86.avx512.pbroadcastq.i64.512(i64 %a0) ; <<8 x i64>> [#uses=1]
292 declare <8 x i64> @llvm.x86.avx512.pbroadcastq.i64.512(i64) nounwind readonly
294 define <16 x i32> @test_conflict_d(<16 x i32> %a) {
295 ; CHECK: movw $-1, %ax
298 %res = call <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32> %a, <16 x i32> zeroinitializer, i16 -1)
302 declare <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32>, <16 x i32>, i16) nounwind readonly
304 define <8 x i64> @test_conflict_q(<8 x i64> %a) {
305 ; CHECK: movb $-1, %al
308 %res = call <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64> %a, <8 x i64> zeroinitializer, i8 -1)
312 declare <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64>, <8 x i64>, i8) nounwind readonly
314 define <16 x i32> @test_maskz_conflict_d(<16 x i32> %a, i16 %mask) {
316 %res = call <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32> %a, <16 x i32> zeroinitializer, i16 %mask)
320 define <8 x i64> @test_mask_conflict_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
322 %res = call <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
326 define <16 x i32> @test_lzcnt_d(<16 x i32> %a) {
327 ; CHECK: movw $-1, %ax
330 %res = call <16 x i32> @llvm.x86.avx512.mask.lzcnt.d.512(<16 x i32> %a, <16 x i32> zeroinitializer, i16 -1)
334 declare <16 x i32> @llvm.x86.avx512.mask.lzcnt.d.512(<16 x i32>, <16 x i32>, i16) nounwind readonly
336 define <8 x i64> @test_lzcnt_q(<8 x i64> %a) {
337 ; CHECK: movb $-1, %al
340 %res = call <8 x i64> @llvm.x86.avx512.mask.lzcnt.q.512(<8 x i64> %a, <8 x i64> zeroinitializer, i8 -1)
344 declare <8 x i64> @llvm.x86.avx512.mask.lzcnt.q.512(<8 x i64>, <8 x i64>, i8) nounwind readonly
347 define <16 x i32> @test_mask_lzcnt_d(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
349 %res = call <16 x i32> @llvm.x86.avx512.mask.lzcnt.d.512(<16 x i32> %a, <16 x i32> %b, i16 %mask)
353 define <8 x i64> @test_mask_lzcnt_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
355 %res = call <8 x i64> @llvm.x86.avx512.mask.lzcnt.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
359 define <16 x i32> @test_ctlz_d(<16 x i32> %a) {
360 ; CHECK-LABEL: test_ctlz_d
362 %res = call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %a, i1 false)
366 declare <16 x i32> @llvm.ctlz.v16i32(<16 x i32>, i1) nounwind readonly
368 define <8 x i64> @test_ctlz_q(<8 x i64> %a) {
369 ; CHECK-LABEL: test_ctlz_q
371 %res = call <8 x i64> @llvm.ctlz.v8i64(<8 x i64> %a, i1 false)
375 declare <8 x i64> @llvm.ctlz.v8i64(<8 x i64>, i1) nounwind readonly
377 define <16 x float> @test_x86_mask_blend_ps_512(i16 %a0, <16 x float> %a1, <16 x float> %a2) {
379 %res = call <16 x float> @llvm.x86.avx512.mask.blend.ps.512(<16 x float> %a1, <16 x float> %a2, i16 %a0) ; <<16 x float>> [#uses=1]
380 ret <16 x float> %res
383 declare <16 x float> @llvm.x86.avx512.mask.blend.ps.512(<16 x float>, <16 x float>, i16) nounwind readonly
385 define <8 x double> @test_x86_mask_blend_pd_512(i8 %a0, <8 x double> %a1, <8 x double> %a2) {
387 %res = call <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double> %a1, <8 x double> %a2, i8 %a0) ; <<8 x double>> [#uses=1]
388 ret <8 x double> %res
391 define <8 x double> @test_x86_mask_blend_pd_512_memop(<8 x double> %a, <8 x double>* %ptr, i8 %mask) {
392 ; CHECK-LABEL: test_x86_mask_blend_pd_512_memop
393 ; CHECK: vblendmpd (%
394 %b = load <8 x double>* %ptr
395 %res = call <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double> %a, <8 x double> %b, i8 %mask) ; <<8 x double>> [#uses=1]
396 ret <8 x double> %res
398 declare <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double>, <8 x double>, i8) nounwind readonly
400 define <16 x i32> @test_x86_mask_blend_d_512(i16 %a0, <16 x i32> %a1, <16 x i32> %a2) {
402 %res = call <16 x i32> @llvm.x86.avx512.mask.blend.d.512(<16 x i32> %a1, <16 x i32> %a2, i16 %a0) ; <<16 x i32>> [#uses=1]
405 declare <16 x i32> @llvm.x86.avx512.mask.blend.d.512(<16 x i32>, <16 x i32>, i16) nounwind readonly
407 define <8 x i64> @test_x86_mask_blend_q_512(i8 %a0, <8 x i64> %a1, <8 x i64> %a2) {
409 %res = call <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i64> %a1, <8 x i64> %a2, i8 %a0) ; <<8 x i64>> [#uses=1]
412 declare <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i64>, <8 x i64>, i8) nounwind readonly
414 define <8 x i32> @test_cvtpd2udq(<8 x double> %a) {
415 ;CHECK: vcvtpd2udq {ru-sae}{{.*}}encoding: [0x62,0xf1,0xfc,0x58,0x79,0xc0]
416 %res = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double> %a, <8 x i32>zeroinitializer, i8 -1, i32 2)
419 declare <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double>, <8 x i32>, i8, i32)
421 define <16 x i32> @test_cvtps2udq(<16 x float> %a) {
422 ;CHECK: vcvtps2udq {rd-sae}{{.*}}encoding: [0x62,0xf1,0x7c,0x38,0x79,0xc0]
423 %res = call <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float> %a, <16 x i32>zeroinitializer, i16 -1, i32 1)
426 declare <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float>, <16 x i32>, i16, i32)
428 define i16 @test_cmpps(<16 x float> %a, <16 x float> %b) {
429 ;CHECK: vcmpleps {sae}{{.*}}encoding: [0x62,0xf1,0x7c,0x18,0xc2,0xc1,0x02]
430 %res = call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a, <16 x float> %b, i32 2, i16 -1, i32 8)
433 declare i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> , <16 x float> , i32, i16, i32)
435 define i8 @test_cmppd(<8 x double> %a, <8 x double> %b) {
436 ;CHECK: vcmpneqpd %zmm{{.*}}encoding: [0x62,0xf1,0xfd,0x48,0xc2,0xc1,0x04]
437 %res = call i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %a, <8 x double> %b, i32 4, i8 -1, i32 4)
440 declare i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> , <8 x double> , i32, i8, i32)
443 define <16 x float> @test_cvtdq2ps(<16 x i32> %a) {
444 ;CHECK: vcvtdq2ps {rd-sae}{{.*}}encoding: [0x62,0xf1,0x7c,0x38,0x5b,0xc0]
445 %res = call <16 x float> @llvm.x86.avx512.mask.cvtdq2ps.512(<16 x i32> %a, <16 x float>zeroinitializer, i16 -1, i32 1)
448 declare <16 x float> @llvm.x86.avx512.mask.cvtdq2ps.512(<16 x i32>, <16 x float>, i16, i32)
450 define <16 x float> @test_cvtudq2ps(<16 x i32> %a) {
451 ;CHECK: vcvtudq2ps {rd-sae}{{.*}}encoding: [0x62,0xf1,0x7f,0x38,0x7a,0xc0]
452 %res = call <16 x float> @llvm.x86.avx512.mask.cvtudq2ps.512(<16 x i32> %a, <16 x float>zeroinitializer, i16 -1, i32 1)
455 declare <16 x float> @llvm.x86.avx512.mask.cvtudq2ps.512(<16 x i32>, <16 x float>, i16, i32)
457 define <8 x double> @test_cvtdq2pd(<8 x i32> %a) {
458 ;CHECK: vcvtdq2pd {{.*}}encoding: [0x62,0xf1,0x7e,0x48,0xe6,0xc0]
459 %res = call <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32> %a, <8 x double>zeroinitializer, i8 -1)
462 declare <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32>, <8 x double>, i8)
464 define <8 x double> @test_cvtudq2pd(<8 x i32> %a) {
465 ;CHECK: vcvtudq2pd {{.*}}encoding: [0x62,0xf1,0x7e,0x48,0x7a,0xc0]
466 %res = call <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32> %a, <8 x double>zeroinitializer, i8 -1)
469 declare <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32>, <8 x double>, i8)
472 define <16 x float> @test_vmaxps(<16 x float> %a0, <16 x float> %a1) {
474 %res = call <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float> %a0, <16 x float> %a1,
475 <16 x float>zeroinitializer, i16 -1, i32 4)
476 ret <16 x float> %res
478 declare <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float>, <16 x float>,
479 <16 x float>, i16, i32)
481 define <8 x double> @test_vmaxpd(<8 x double> %a0, <8 x double> %a1) {
483 %res = call <8 x double> @llvm.x86.avx512.mask.max.pd.512(<8 x double> %a0, <8 x double> %a1,
484 <8 x double>zeroinitializer, i8 -1, i32 4)
485 ret <8 x double> %res
487 declare <8 x double> @llvm.x86.avx512.mask.max.pd.512(<8 x double>, <8 x double>,
488 <8 x double>, i8, i32)
490 define <16 x float> @test_vminps(<16 x float> %a0, <16 x float> %a1) {
492 %res = call <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float> %a0, <16 x float> %a1,
493 <16 x float>zeroinitializer, i16 -1, i32 4)
494 ret <16 x float> %res
496 declare <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float>, <16 x float>,
497 <16 x float>, i16, i32)
499 define <8 x double> @test_vminpd(<8 x double> %a0, <8 x double> %a1) {
501 %res = call <8 x double> @llvm.x86.avx512.mask.min.pd.512(<8 x double> %a0, <8 x double> %a1,
502 <8 x double>zeroinitializer, i8 -1, i32 4)
503 ret <8 x double> %res
505 declare <8 x double> @llvm.x86.avx512.mask.min.pd.512(<8 x double>, <8 x double>,
506 <8 x double>, i8, i32)
508 define <8 x float> @test_cvtpd2ps(<8 x double> %a) {
509 ;CHECK: vcvtpd2ps {rd-sae}{{.*}}encoding: [0x62,0xf1,0xfd,0x38,0x5a,0xc0]
510 %res = call <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double> %a, <8 x float>zeroinitializer, i8 -1, i32 1)
513 declare <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double>, <8 x float>, i8, i32)
515 define <16 x i32> @test_pabsd(<16 x i32> %a) {
516 ;CHECK: vpabsd {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x1e,0xc0]
517 %res = call <16 x i32> @llvm.x86.avx512.mask.pabs.d.512(<16 x i32> %a, <16 x i32>zeroinitializer, i16 -1)
520 declare <16 x i32> @llvm.x86.avx512.mask.pabs.d.512(<16 x i32>, <16 x i32>, i16)
522 define <8 x i64> @test_pabsq(<8 x i64> %a) {
523 ;CHECK: vpabsq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x1f,0xc0]
524 %res = call <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64> %a, <8 x i64>zeroinitializer, i8 -1)
527 declare <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64>, <8 x i64>, i8)
529 define <8 x i64> @test_vpmaxq(<8 x i64> %a0, <8 x i64> %a1) {
530 ; CHECK: vpmaxsq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x3d,0xc1]
531 %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %a0, <8 x i64> %a1,
532 <8 x i64>zeroinitializer, i8 -1)
535 declare <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
537 define <16 x i32> @test_vpminud(<16 x i32> %a0, <16 x i32> %a1) {
538 ; CHECK: vpminud {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x3b,0xc1]
539 %res = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32> %a0, <16 x i32> %a1,
540 <16 x i32>zeroinitializer, i16 -1)
543 declare <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
545 define <16 x i32> @test_vpmaxsd(<16 x i32> %a0, <16 x i32> %a1) {
546 ; CHECK: vpmaxsd {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x3d,0xc1]
547 %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %a0, <16 x i32> %a1,
548 <16 x i32>zeroinitializer, i16 -1)
551 declare <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
553 define <8 x i64> @test_vpmuludq(<16 x i32> %a0, <16 x i32> %a1) {
554 ; CHECK: vpmuludq {{.*}}encoding: [0x62,0xf1,0xfd,0x48,0xf4,0xc1]
555 %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a0, <16 x i32> %a1,
556 <8 x i64>zeroinitializer, i8 -1)
559 declare <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32>, <16 x i32>, <8 x i64>, i8)
561 define i8 @test_vptestmq(<8 x i64> %a0, <8 x i64> %a1) {
562 ; CHECK: vptestmq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x27,0xc1]
563 %res = call i8 @llvm.x86.avx512.mask.ptestm.q.512(<8 x i64> %a0, <8 x i64> %a1, i8 -1)
566 declare i8 @llvm.x86.avx512.mask.ptestm.q.512(<8 x i64>, <8 x i64>, i8)
568 define i16 @test_vptestmd(<16 x i32> %a0, <16 x i32> %a1) {
569 ; CHECK: vptestmd {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x27,0xc1]
570 %res = call i16 @llvm.x86.avx512.mask.ptestm.d.512(<16 x i32> %a0, <16 x i32> %a1, i16 -1)
573 declare i16 @llvm.x86.avx512.mask.ptestm.d.512(<16 x i32>, <16 x i32>, i16)
575 define void @test_store1(<16 x float> %data, i8* %ptr, i16 %mask) {
576 ; CHECK: vmovups {{.*}}encoding: [0x62,0xf1,0x7c,0x49,0x11,0x07]
577 call void @llvm.x86.avx512.mask.storeu.ps.512(i8* %ptr, <16 x float> %data, i16 %mask)
581 declare void @llvm.x86.avx512.mask.storeu.ps.512(i8*, <16 x float>, i16 )
583 define void @test_store2(<8 x double> %data, i8* %ptr, i8 %mask) {
584 ; CHECK: vmovupd {{.*}}encoding: [0x62,0xf1,0xfd,0x49,0x11,0x07]
585 call void @llvm.x86.avx512.mask.storeu.pd.512(i8* %ptr, <8 x double> %data, i8 %mask)
589 declare void @llvm.x86.avx512.mask.storeu.pd.512(i8*, <8 x double>, i8 )
591 define <16 x float> @test_vpermt2ps(<16 x float>%x, <16 x float>%y, <16 x i32>%perm) {
592 ; CHECK: vpermt2ps {{.*}}encoding: [0x62,0xf2,0x6d,0x48,0x7f,0xc1]
593 %res = call <16 x float> @llvm.x86.avx512.mask.vpermt.ps.512(<16 x i32>%perm, <16 x float>%x, <16 x float>%y, i16 -1)
594 ret <16 x float> %res
597 define <16 x float> @test_vpermt2ps_mask(<16 x float>%x, <16 x float>%y, <16 x i32>%perm, i16 %mask) {
598 ; CHECK-LABEL: test_vpermt2ps_mask:
599 ; CHECK: vpermt2ps %zmm1, %zmm2, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x6d,0x49,0x7f,0xc1]
600 %res = call <16 x float> @llvm.x86.avx512.mask.vpermt.ps.512(<16 x i32>%perm, <16 x float>%x, <16 x float>%y, i16 %mask)
601 ret <16 x float> %res
604 declare <16 x float> @llvm.x86.avx512.mask.vpermt.ps.512(<16 x i32>, <16 x float>, <16 x float>, i16)
606 define <8 x i64> @test_vmovntdqa(i8 *%x) {
607 ; CHECK-LABEL: test_vmovntdqa:
608 ; CHECK: vmovntdqa (%rdi), %zmm0 ## encoding: [0x62,0xf2,0x7d,0x48,0x2a,0x07]
609 %res = call <8 x i64> @llvm.x86.avx512.movntdqa(i8* %x)
613 declare <8 x i64> @llvm.x86.avx512.movntdqa(i8*)
615 define <8 x i64> @test_valign_q(<8 x i64> %a, <8 x i64> %b) {
616 ; CHECK-LABEL: test_valign_q:
617 ; CHECK: valignq $2, %zmm1, %zmm0, %zmm0
618 %res = call <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64> %a, <8 x i64> %b, i8 2, <8 x i64> zeroinitializer, i8 -1)
622 define <8 x i64> @test_mask_valign_q(<8 x i64> %a, <8 x i64> %b, <8 x i64> %src, i8 %mask) {
623 ; CHECK-LABEL: test_mask_valign_q:
624 ; CHECK: valignq $2, %zmm1, %zmm0, %zmm2 {%k1}
625 %res = call <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64> %a, <8 x i64> %b, i8 2, <8 x i64> %src, i8 %mask)
629 declare <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64>, <8 x i64>, i8, <8 x i64>, i8)
631 define <16 x i32> @test_maskz_valign_d(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
632 ; CHECK-LABEL: test_maskz_valign_d:
633 ; CHECK: valignd $5, %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf3,0x7d,0xc9,0x03,0xc1,0x05]
634 %res = call <16 x i32> @llvm.x86.avx512.mask.valign.d.512(<16 x i32> %a, <16 x i32> %b, i8 5, <16 x i32> zeroinitializer, i16 %mask)
638 declare <16 x i32> @llvm.x86.avx512.mask.valign.d.512(<16 x i32>, <16 x i32>, i8, <16 x i32>, i16)
640 define void @test_mask_store_ss(i8* %ptr, <4 x float> %data, i8 %mask) {
641 ; CHECK-LABEL: test_mask_store_ss
642 ; CHECK: vmovss %xmm0, (%rdi) {%k1} ## encoding: [0x62,0xf1,0x7e,0x09,0x11,0x07]
643 call void @llvm.x86.avx512.mask.store.ss(i8* %ptr, <4 x float> %data, i8 %mask)
647 declare void @llvm.x86.avx512.mask.store.ss(i8*, <4 x float>, i8 )
649 define i16 @test_pcmpeq_d(<16 x i32> %a, <16 x i32> %b) {
650 ; CHECK-LABEL: test_pcmpeq_d
651 ; CHECK: vpcmpeqd %zmm1, %zmm0, %k0 ##
652 %res = call i16 @llvm.x86.avx512.mask.pcmpeq.d.512(<16 x i32> %a, <16 x i32> %b, i16 -1)
656 define i16 @test_mask_pcmpeq_d(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
657 ; CHECK-LABEL: test_mask_pcmpeq_d
658 ; CHECK: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ##
659 %res = call i16 @llvm.x86.avx512.mask.pcmpeq.d.512(<16 x i32> %a, <16 x i32> %b, i16 %mask)
663 declare i16 @llvm.x86.avx512.mask.pcmpeq.d.512(<16 x i32>, <16 x i32>, i16)
665 define i8 @test_pcmpeq_q(<8 x i64> %a, <8 x i64> %b) {
666 ; CHECK-LABEL: test_pcmpeq_q
667 ; CHECK: vpcmpeqq %zmm1, %zmm0, %k0 ##
668 %res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64> %a, <8 x i64> %b, i8 -1)
672 define i8 @test_mask_pcmpeq_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
673 ; CHECK-LABEL: test_mask_pcmpeq_q
674 ; CHECK: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ##
675 %res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
679 declare i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64>, <8 x i64>, i8)
681 define i16 @test_pcmpgt_d(<16 x i32> %a, <16 x i32> %b) {
682 ; CHECK-LABEL: test_pcmpgt_d
683 ; CHECK: vpcmpgtd %zmm1, %zmm0, %k0 ##
684 %res = call i16 @llvm.x86.avx512.mask.pcmpgt.d.512(<16 x i32> %a, <16 x i32> %b, i16 -1)
688 define i16 @test_mask_pcmpgt_d(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
689 ; CHECK-LABEL: test_mask_pcmpgt_d
690 ; CHECK: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ##
691 %res = call i16 @llvm.x86.avx512.mask.pcmpgt.d.512(<16 x i32> %a, <16 x i32> %b, i16 %mask)
695 declare i16 @llvm.x86.avx512.mask.pcmpgt.d.512(<16 x i32>, <16 x i32>, i16)
697 define i8 @test_pcmpgt_q(<8 x i64> %a, <8 x i64> %b) {
698 ; CHECK-LABEL: test_pcmpgt_q
699 ; CHECK: vpcmpgtq %zmm1, %zmm0, %k0 ##
700 %res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64> %a, <8 x i64> %b, i8 -1)
704 define i8 @test_mask_pcmpgt_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
705 ; CHECK-LABEL: test_mask_pcmpgt_q
706 ; CHECK: vpcmpgtq %zmm1, %zmm0, %k0 {%k1} ##
707 %res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
711 declare i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64>, <8 x i64>, i8)
713 define <8 x i16> @test_cmp_d_512(<16 x i32> %a0, <16 x i32> %a1) {
714 ; CHECK_LABEL: test_cmp_d_512
715 ; CHECK: vpcmpeqd %zmm1, %zmm0, %k0 ##
716 %res0 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 0, i16 -1)
717 %vec0 = insertelement <8 x i16> undef, i16 %res0, i32 0
718 ; CHECK: vpcmpltd %zmm1, %zmm0, %k0 ##
719 %res1 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 1, i16 -1)
720 %vec1 = insertelement <8 x i16> %vec0, i16 %res1, i32 1
721 ; CHECK: vpcmpled %zmm1, %zmm0, %k0 ##
722 %res2 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 2, i16 -1)
723 %vec2 = insertelement <8 x i16> %vec1, i16 %res2, i32 2
724 ; CHECK: vpcmpunordd %zmm1, %zmm0, %k0 ##
725 %res3 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 3, i16 -1)
726 %vec3 = insertelement <8 x i16> %vec2, i16 %res3, i32 3
727 ; CHECK: vpcmpneqd %zmm1, %zmm0, %k0 ##
728 %res4 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 4, i16 -1)
729 %vec4 = insertelement <8 x i16> %vec3, i16 %res4, i32 4
730 ; CHECK: vpcmpnltd %zmm1, %zmm0, %k0 ##
731 %res5 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 5, i16 -1)
732 %vec5 = insertelement <8 x i16> %vec4, i16 %res5, i32 5
733 ; CHECK: vpcmpnled %zmm1, %zmm0, %k0 ##
734 %res6 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 6, i16 -1)
735 %vec6 = insertelement <8 x i16> %vec5, i16 %res6, i32 6
736 ; CHECK: vpcmpordd %zmm1, %zmm0, %k0 ##
737 %res7 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 7, i16 -1)
738 %vec7 = insertelement <8 x i16> %vec6, i16 %res7, i32 7
742 define <8 x i16> @test_mask_cmp_d_512(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
743 ; CHECK_LABEL: test_mask_cmp_d_512
744 ; CHECK: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ##
745 %res0 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 0, i16 %mask)
746 %vec0 = insertelement <8 x i16> undef, i16 %res0, i32 0
747 ; CHECK: vpcmpltd %zmm1, %zmm0, %k0 {%k1} ##
748 %res1 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 1, i16 %mask)
749 %vec1 = insertelement <8 x i16> %vec0, i16 %res1, i32 1
750 ; CHECK: vpcmpled %zmm1, %zmm0, %k0 {%k1} ##
751 %res2 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 2, i16 %mask)
752 %vec2 = insertelement <8 x i16> %vec1, i16 %res2, i32 2
753 ; CHECK: vpcmpunordd %zmm1, %zmm0, %k0 {%k1} ##
754 %res3 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 3, i16 %mask)
755 %vec3 = insertelement <8 x i16> %vec2, i16 %res3, i32 3
756 ; CHECK: vpcmpneqd %zmm1, %zmm0, %k0 {%k1} ##
757 %res4 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 4, i16 %mask)
758 %vec4 = insertelement <8 x i16> %vec3, i16 %res4, i32 4
759 ; CHECK: vpcmpnltd %zmm1, %zmm0, %k0 {%k1} ##
760 %res5 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 5, i16 %mask)
761 %vec5 = insertelement <8 x i16> %vec4, i16 %res5, i32 5
762 ; CHECK: vpcmpnled %zmm1, %zmm0, %k0 {%k1} ##
763 %res6 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 6, i16 %mask)
764 %vec6 = insertelement <8 x i16> %vec5, i16 %res6, i32 6
765 ; CHECK: vpcmpordd %zmm1, %zmm0, %k0 {%k1} ##
766 %res7 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 7, i16 %mask)
767 %vec7 = insertelement <8 x i16> %vec6, i16 %res7, i32 7
771 declare i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32>, <16 x i32>, i32, i16) nounwind readnone
773 define <8 x i16> @test_ucmp_d_512(<16 x i32> %a0, <16 x i32> %a1) {
774 ; CHECK_LABEL: test_ucmp_d_512
775 ; CHECK: vpcmpequd %zmm1, %zmm0, %k0 ##
776 %res0 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 0, i16 -1)
777 %vec0 = insertelement <8 x i16> undef, i16 %res0, i32 0
778 ; CHECK: vpcmpltud %zmm1, %zmm0, %k0 ##
779 %res1 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 1, i16 -1)
780 %vec1 = insertelement <8 x i16> %vec0, i16 %res1, i32 1
781 ; CHECK: vpcmpleud %zmm1, %zmm0, %k0 ##
782 %res2 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 2, i16 -1)
783 %vec2 = insertelement <8 x i16> %vec1, i16 %res2, i32 2
784 ; CHECK: vpcmpunordud %zmm1, %zmm0, %k0 ##
785 %res3 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 3, i16 -1)
786 %vec3 = insertelement <8 x i16> %vec2, i16 %res3, i32 3
787 ; CHECK: vpcmpnequd %zmm1, %zmm0, %k0 ##
788 %res4 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 4, i16 -1)
789 %vec4 = insertelement <8 x i16> %vec3, i16 %res4, i32 4
790 ; CHECK: vpcmpnltud %zmm1, %zmm0, %k0 ##
791 %res5 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 5, i16 -1)
792 %vec5 = insertelement <8 x i16> %vec4, i16 %res5, i32 5
793 ; CHECK: vpcmpnleud %zmm1, %zmm0, %k0 ##
794 %res6 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 6, i16 -1)
795 %vec6 = insertelement <8 x i16> %vec5, i16 %res6, i32 6
796 ; CHECK: vpcmpordud %zmm1, %zmm0, %k0 ##
797 %res7 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 7, i16 -1)
798 %vec7 = insertelement <8 x i16> %vec6, i16 %res7, i32 7
802 define <8 x i16> @test_mask_ucmp_d_512(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
803 ; CHECK_LABEL: test_mask_ucmp_d_512
804 ; CHECK: vpcmpequd %zmm1, %zmm0, %k0 {%k1} ##
805 %res0 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 0, i16 %mask)
806 %vec0 = insertelement <8 x i16> undef, i16 %res0, i32 0
807 ; CHECK: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ##
808 %res1 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 1, i16 %mask)
809 %vec1 = insertelement <8 x i16> %vec0, i16 %res1, i32 1
810 ; CHECK: vpcmpleud %zmm1, %zmm0, %k0 {%k1} ##
811 %res2 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 2, i16 %mask)
812 %vec2 = insertelement <8 x i16> %vec1, i16 %res2, i32 2
813 ; CHECK: vpcmpunordud %zmm1, %zmm0, %k0 {%k1} ##
814 %res3 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 3, i16 %mask)
815 %vec3 = insertelement <8 x i16> %vec2, i16 %res3, i32 3
816 ; CHECK: vpcmpnequd %zmm1, %zmm0, %k0 {%k1} ##
817 %res4 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 4, i16 %mask)
818 %vec4 = insertelement <8 x i16> %vec3, i16 %res4, i32 4
819 ; CHECK: vpcmpnltud %zmm1, %zmm0, %k0 {%k1} ##
820 %res5 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 5, i16 %mask)
821 %vec5 = insertelement <8 x i16> %vec4, i16 %res5, i32 5
822 ; CHECK: vpcmpnleud %zmm1, %zmm0, %k0 {%k1} ##
823 %res6 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 6, i16 %mask)
824 %vec6 = insertelement <8 x i16> %vec5, i16 %res6, i32 6
825 ; CHECK: vpcmpordud %zmm1, %zmm0, %k0 {%k1} ##
826 %res7 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 7, i16 %mask)
827 %vec7 = insertelement <8 x i16> %vec6, i16 %res7, i32 7
831 declare i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32>, <16 x i32>, i32, i16) nounwind readnone
833 define <8 x i8> @test_cmp_q_512(<8 x i64> %a0, <8 x i64> %a1) {
834 ; CHECK_LABEL: test_cmp_q_512
835 ; CHECK: vpcmpeqq %zmm1, %zmm0, %k0 ##
836 %res0 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 0, i8 -1)
837 %vec0 = insertelement <8 x i8> undef, i8 %res0, i32 0
838 ; CHECK: vpcmpltq %zmm1, %zmm0, %k0 ##
839 %res1 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 1, i8 -1)
840 %vec1 = insertelement <8 x i8> %vec0, i8 %res1, i32 1
841 ; CHECK: vpcmpleq %zmm1, %zmm0, %k0 ##
842 %res2 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 2, i8 -1)
843 %vec2 = insertelement <8 x i8> %vec1, i8 %res2, i32 2
844 ; CHECK: vpcmpunordq %zmm1, %zmm0, %k0 ##
845 %res3 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 3, i8 -1)
846 %vec3 = insertelement <8 x i8> %vec2, i8 %res3, i32 3
847 ; CHECK: vpcmpneqq %zmm1, %zmm0, %k0 ##
848 %res4 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 4, i8 -1)
849 %vec4 = insertelement <8 x i8> %vec3, i8 %res4, i32 4
850 ; CHECK: vpcmpnltq %zmm1, %zmm0, %k0 ##
851 %res5 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 5, i8 -1)
852 %vec5 = insertelement <8 x i8> %vec4, i8 %res5, i32 5
853 ; CHECK: vpcmpnleq %zmm1, %zmm0, %k0 ##
854 %res6 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 6, i8 -1)
855 %vec6 = insertelement <8 x i8> %vec5, i8 %res6, i32 6
856 ; CHECK: vpcmpordq %zmm1, %zmm0, %k0 ##
857 %res7 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 7, i8 -1)
858 %vec7 = insertelement <8 x i8> %vec6, i8 %res7, i32 7
862 define <8 x i8> @test_mask_cmp_q_512(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
863 ; CHECK_LABEL: test_mask_cmp_q_512
864 ; CHECK: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ##
865 %res0 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 0, i8 %mask)
866 %vec0 = insertelement <8 x i8> undef, i8 %res0, i32 0
867 ; CHECK: vpcmpltq %zmm1, %zmm0, %k0 {%k1} ##
868 %res1 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 1, i8 %mask)
869 %vec1 = insertelement <8 x i8> %vec0, i8 %res1, i32 1
870 ; CHECK: vpcmpleq %zmm1, %zmm0, %k0 {%k1} ##
871 %res2 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 2, i8 %mask)
872 %vec2 = insertelement <8 x i8> %vec1, i8 %res2, i32 2
873 ; CHECK: vpcmpunordq %zmm1, %zmm0, %k0 {%k1} ##
874 %res3 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 3, i8 %mask)
875 %vec3 = insertelement <8 x i8> %vec2, i8 %res3, i32 3
876 ; CHECK: vpcmpneqq %zmm1, %zmm0, %k0 {%k1} ##
877 %res4 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 4, i8 %mask)
878 %vec4 = insertelement <8 x i8> %vec3, i8 %res4, i32 4
879 ; CHECK: vpcmpnltq %zmm1, %zmm0, %k0 {%k1} ##
880 %res5 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 5, i8 %mask)
881 %vec5 = insertelement <8 x i8> %vec4, i8 %res5, i32 5
882 ; CHECK: vpcmpnleq %zmm1, %zmm0, %k0 {%k1} ##
883 %res6 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 6, i8 %mask)
884 %vec6 = insertelement <8 x i8> %vec5, i8 %res6, i32 6
885 ; CHECK: vpcmpordq %zmm1, %zmm0, %k0 {%k1} ##
886 %res7 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 7, i8 %mask)
887 %vec7 = insertelement <8 x i8> %vec6, i8 %res7, i32 7
891 declare i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64>, <8 x i64>, i32, i8) nounwind readnone
893 define <8 x i8> @test_ucmp_q_512(<8 x i64> %a0, <8 x i64> %a1) {
894 ; CHECK_LABEL: test_ucmp_q_512
895 ; CHECK: vpcmpequq %zmm1, %zmm0, %k0 ##
896 %res0 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 0, i8 -1)
897 %vec0 = insertelement <8 x i8> undef, i8 %res0, i32 0
898 ; CHECK: vpcmpltuq %zmm1, %zmm0, %k0 ##
899 %res1 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 1, i8 -1)
900 %vec1 = insertelement <8 x i8> %vec0, i8 %res1, i32 1
901 ; CHECK: vpcmpleuq %zmm1, %zmm0, %k0 ##
902 %res2 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 2, i8 -1)
903 %vec2 = insertelement <8 x i8> %vec1, i8 %res2, i32 2
904 ; CHECK: vpcmpunorduq %zmm1, %zmm0, %k0 ##
905 %res3 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 3, i8 -1)
906 %vec3 = insertelement <8 x i8> %vec2, i8 %res3, i32 3
907 ; CHECK: vpcmpnequq %zmm1, %zmm0, %k0 ##
908 %res4 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 4, i8 -1)
909 %vec4 = insertelement <8 x i8> %vec3, i8 %res4, i32 4
910 ; CHECK: vpcmpnltuq %zmm1, %zmm0, %k0 ##
911 %res5 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 5, i8 -1)
912 %vec5 = insertelement <8 x i8> %vec4, i8 %res5, i32 5
913 ; CHECK: vpcmpnleuq %zmm1, %zmm0, %k0 ##
914 %res6 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 6, i8 -1)
915 %vec6 = insertelement <8 x i8> %vec5, i8 %res6, i32 6
916 ; CHECK: vpcmporduq %zmm1, %zmm0, %k0 ##
917 %res7 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 7, i8 -1)
918 %vec7 = insertelement <8 x i8> %vec6, i8 %res7, i32 7
922 define <8 x i8> @test_mask_ucmp_q_512(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
923 ; CHECK_LABEL: test_mask_ucmp_q_512
924 ; CHECK: vpcmpequq %zmm1, %zmm0, %k0 {%k1} ##
925 %res0 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 0, i8 %mask)
926 %vec0 = insertelement <8 x i8> undef, i8 %res0, i32 0
927 ; CHECK: vpcmpltuq %zmm1, %zmm0, %k0 {%k1} ##
928 %res1 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 1, i8 %mask)
929 %vec1 = insertelement <8 x i8> %vec0, i8 %res1, i32 1
930 ; CHECK: vpcmpleuq %zmm1, %zmm0, %k0 {%k1} ##
931 %res2 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 2, i8 %mask)
932 %vec2 = insertelement <8 x i8> %vec1, i8 %res2, i32 2
933 ; CHECK: vpcmpunorduq %zmm1, %zmm0, %k0 {%k1} ##
934 %res3 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 3, i8 %mask)
935 %vec3 = insertelement <8 x i8> %vec2, i8 %res3, i32 3
936 ; CHECK: vpcmpnequq %zmm1, %zmm0, %k0 {%k1} ##
937 %res4 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 4, i8 %mask)
938 %vec4 = insertelement <8 x i8> %vec3, i8 %res4, i32 4
939 ; CHECK: vpcmpnltuq %zmm1, %zmm0, %k0 {%k1} ##
940 %res5 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 5, i8 %mask)
941 %vec5 = insertelement <8 x i8> %vec4, i8 %res5, i32 5
942 ; CHECK: vpcmpnleuq %zmm1, %zmm0, %k0 {%k1} ##
943 %res6 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 6, i8 %mask)
944 %vec6 = insertelement <8 x i8> %vec5, i8 %res6, i32 6
945 ; CHECK: vpcmporduq %zmm1, %zmm0, %k0 {%k1} ##
946 %res7 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 7, i8 %mask)
947 %vec7 = insertelement <8 x i8> %vec6, i8 %res7, i32 7
951 declare i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64>, <8 x i64>, i32, i8) nounwind readnone
953 define <4 x float> @test_mask_vextractf32x4(<4 x float> %b, <16 x float> %a, i8 %mask) {
954 ; CHECK-LABEL: test_mask_vextractf32x4:
955 ; CHECK: vextractf32x4 $2, %zmm1, %xmm0 {%k1}
956 %res = call <4 x float> @llvm.x86.avx512.mask.vextractf32x4.512(<16 x float> %a, i8 2, <4 x float> %b, i8 %mask)
960 declare <4 x float> @llvm.x86.avx512.mask.vextractf32x4.512(<16 x float>, i8, <4 x float>, i8)
962 define <4 x i64> @test_mask_vextracti64x4(<4 x i64> %b, <8 x i64> %a, i8 %mask) {
963 ; CHECK-LABEL: test_mask_vextracti64x4:
964 ; CHECK: vextracti64x4 $2, %zmm1, %ymm0 {%k1}
965 %res = call <4 x i64> @llvm.x86.avx512.mask.vextracti64x4.512(<8 x i64> %a, i8 2, <4 x i64> %b, i8 %mask)
969 declare <4 x i64> @llvm.x86.avx512.mask.vextracti64x4.512(<8 x i64>, i8, <4 x i64>, i8)
971 define <4 x i32> @test_maskz_vextracti32x4(<16 x i32> %a, i8 %mask) {
972 ; CHECK-LABEL: test_maskz_vextracti32x4:
973 ; CHECK: vextracti32x4 $2, %zmm0, %xmm0 {%k1} {z}
974 %res = call <4 x i32> @llvm.x86.avx512.mask.vextracti32x4.512(<16 x i32> %a, i8 2, <4 x i32> zeroinitializer, i8 %mask)
978 declare <4 x i32> @llvm.x86.avx512.mask.vextracti32x4.512(<16 x i32>, i8, <4 x i32>, i8)
980 define <4 x double> @test_vextractf64x4(<8 x double> %a) {
981 ; CHECK-LABEL: test_vextractf64x4:
982 ; CHECK: vextractf64x4 $2, %zmm0, %ymm0 ##
983 %res = call <4 x double> @llvm.x86.avx512.mask.vextractf64x4.512(<8 x double> %a, i8 2, <4 x double> zeroinitializer, i8 -1)
984 ret <4 x double> %res
987 declare <4 x double> @llvm.x86.avx512.mask.vextractf64x4.512(<8 x double>, i8, <4 x double>, i8)