1 ; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s
3 target triple = "x86_64-unknown-linux-gnu"
5 ; Make sure that we don't crash when legalizng vselect and vsetcc and that
6 ; we are able to generate vector blend instructions.
11 define void @simple_widen() {
13 %0 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef
14 store <2 x float> %0, <2 x float>* undef
18 ; CHECK: complex_inreg_work
22 define void @complex_inreg_work() {
24 %0 = fcmp oeq <2 x float> undef, undef
25 %1 = select <2 x i1> %0, <2 x float> undef, <2 x float> undef
26 store <2 x float> %1, <2 x float>* undef
34 define void @zero_test() {
36 %0 = select <2 x i1> undef, <2 x float> undef, <2 x float> zeroinitializer
37 store <2 x float> %0, <2 x float>* undef
45 define void @full_test() {
47 %Cy300 = alloca <4 x float>
48 %Cy11a = alloca <2 x float>
49 %Cy118 = alloca <2 x float>
50 %Cy119 = alloca <2 x float>
54 %0 = load <2 x float>* %Cy119
55 %1 = fptosi <2 x float> %0 to <2 x i32>
56 %2 = sitofp <2 x i32> %1 to <2 x float>
57 %3 = fcmp ogt <2 x float> %0, zeroinitializer
58 %4 = fadd <2 x float> %2, <float 1.000000e+00, float 1.000000e+00>
59 %5 = select <2 x i1> %3, <2 x float> %4, <2 x float> %2
60 %6 = fcmp oeq <2 x float> %2, %0
61 %7 = select <2 x i1> %6, <2 x float> %0, <2 x float> %5
62 store <2 x float> %7, <2 x float>* %Cy118
63 %8 = load <2 x float>* %Cy118
64 store <2 x float> %8, <2 x float>* %Cy11a