1 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-fp-elim | FileCheck %s
2 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC
6 @GV = external global i32 ; <i32*> [#uses=2]
8 define void @t1(i32* nocapture %vals, i32 %c) nounwind {
12 %0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
13 br i1 %0, label %return, label %bb.nph
15 bb.nph: ; preds = %entry
17 ; CHECK: movw r[[R2:[0-9]+]], :lower16:L_GV$non_lazy_ptr
18 ; CHECK: movt r[[R2]], :upper16:L_GV$non_lazy_ptr
19 ; CHECK: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]]
20 ; CHECK: ldr{{.*}}, [r[[R2b]]
25 ; PIC: movw r[[R2:[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4))
26 ; PIC: movt r[[R2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4))
27 ; PIC: add r[[R2]], pc
28 ; PIC: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]]
29 ; PIC: ldr{{.*}}, [r[[R2b]]
33 %.pre = load i32* @GV, align 4 ; <i32> [#uses=1]
36 bb: ; preds = %bb, %bb.nph
37 %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; <i32> [#uses=1]
38 %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; <i32> [#uses=2]
39 %scevgep = getelementptr i32* %vals, i32 %i.03 ; <i32*> [#uses=1]
40 %2 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
41 %3 = add nsw i32 %1, %2 ; <i32> [#uses=2]
42 store i32 %3, i32* @GV, align 4
43 %4 = add i32 %i.03, 1 ; <i32> [#uses=2]
44 %exitcond = icmp eq i32 %4, %c ; <i1> [#uses=1]
45 br i1 %exitcond, label %return, label %bb
47 return: ; preds = %bb, %entry
52 define void @t2(i8* %ptr1, i8* %ptr2) nounwind {
55 ; CHECK: mov.w r3, #1065353216
56 ; CHECK: vdup.32 q{{.*}}, r3
57 br i1 undef, label %bb1, label %bb2
61 %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ]
62 %tmp1 = shl i32 %indvar, 2
63 %gep1 = getelementptr i8* %ptr1, i32 %tmp1
64 %tmp2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %gep1, i32 1)
65 %tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <4 x float> %tmp2)
66 %gep2 = getelementptr i8* %ptr2, i32 %tmp1
67 call void @llvm.arm.neon.vst1.v4f32(i8* %gep2, <4 x float> %tmp3, i32 1)
68 %indvar.next = add i32 %indvar, 1
69 %cond = icmp eq i32 %indvar.next, 10
70 br i1 %cond, label %bb2, label %bb1
78 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
80 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
82 declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
85 ; isel should not fold immediate into eor's which would have prevented LICM.
86 define zeroext i16 @t3(i8 zeroext %data, i16 zeroext %crc) nounwind readnone {
90 ; CHECK: movw {{(r[0-9])|(lr)}}, #32768
91 ; CHECK: movs {{(r[0-9]+)|(lr)}}, #0
92 ; CHECK: movw [[REGISTER:(r[0-9]+)|(lr)]], #16386
93 ; CHECK: movw {{(r[0-9]+)|(lr)}}, #65534
94 ; CHECK: movt {{(r[0-9]+)|(lr)}}, #65535
97 bb: ; preds = %bb, %bb.nph
99 ; CHECK: eor.w {{(r[0-9])|(lr)}}, {{(r[0-9])|(lr)}}, [[REGISTER]]
103 %data_addr.013 = phi i8 [ %data, %bb.nph ], [ %8, %bb ] ; <i8> [#uses=2]
104 %crc_addr.112 = phi i16 [ %crc, %bb.nph ], [ %crc_addr.2, %bb ] ; <i16> [#uses=3]
105 %i.011 = phi i8 [ 0, %bb.nph ], [ %7, %bb ] ; <i8> [#uses=1]
106 %0 = trunc i16 %crc_addr.112 to i8 ; <i8> [#uses=1]
107 %1 = xor i8 %data_addr.013, %0 ; <i8> [#uses=1]
108 %2 = and i8 %1, 1 ; <i8> [#uses=1]
109 %3 = icmp eq i8 %2, 0 ; <i1> [#uses=2]
110 %4 = xor i16 %crc_addr.112, 16386 ; <i16> [#uses=1]
111 %crc_addr.0 = select i1 %3, i16 %crc_addr.112, i16 %4 ; <i16> [#uses=1]
112 %5 = lshr i16 %crc_addr.0, 1 ; <i16> [#uses=2]
113 %6 = or i16 %5, -32768 ; <i16> [#uses=1]
114 %crc_addr.2 = select i1 %3, i16 %5, i16 %6 ; <i16> [#uses=2]
115 %7 = add i8 %i.011, 1 ; <i8> [#uses=2]
116 %8 = lshr i8 %data_addr.013, 1 ; <i8> [#uses=1]
117 %exitcond = icmp eq i8 %7, 8 ; <i1> [#uses=1]
118 br i1 %exitcond, label %bb8, label %bb