1 ; Test vector zero-extending loads.
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
5 ; Test a v16i1->v16i8 extension.
6 define <16 x i8> @f1(<16 x i1> *%ptr) {
7 ; No expected output, but must compile.
8 %val = load <16 x i1>, <16 x i1> *%ptr
9 %ret = zext <16 x i1> %val to <16 x i8>
13 ; Test a v8i1->v8i16 extension.
14 define <8 x i16> @f2(<8 x i1> *%ptr) {
15 ; No expected output, but must compile.
16 %val = load <8 x i1>, <8 x i1> *%ptr
17 %ret = zext <8 x i1> %val to <8 x i16>
21 ; Test a v8i8->v8i16 extension.
22 define <8 x i16> @f3(<8 x i8> *%ptr) {
24 ; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
25 ; CHECK: vuplhb %v24, [[REG1]]
27 %val = load <8 x i8>, <8 x i8> *%ptr
28 %ret = zext <8 x i8> %val to <8 x i16>
32 ; Test a v4i1->v4i32 extension.
33 define <4 x i32> @f4(<4 x i1> *%ptr) {
34 ; No expected output, but must compile.
35 %val = load <4 x i1>, <4 x i1> *%ptr
36 %ret = zext <4 x i1> %val to <4 x i32>
40 ; Test a v4i8->v4i32 extension.
41 define <4 x i32> @f5(<4 x i8> *%ptr) {
43 ; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)
44 ; CHECK: vuplhb [[REG2:%v[0-9]+]], [[REG1]]
45 ; CHECK: vuplhh %v24, [[REG2]]
47 %val = load <4 x i8>, <4 x i8> *%ptr
48 %ret = zext <4 x i8> %val to <4 x i32>
52 ; Test a v4i16->v4i32 extension.
53 define <4 x i32> @f6(<4 x i16> *%ptr) {
55 ; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
56 ; CHECK: vuplhh %v24, [[REG1]]
58 %val = load <4 x i16>, <4 x i16> *%ptr
59 %ret = zext <4 x i16> %val to <4 x i32>
63 ; Test a v2i1->v2i64 extension.
64 define <2 x i64> @f7(<2 x i1> *%ptr) {
65 ; No expected output, but must compile.
66 %val = load <2 x i1>, <2 x i1> *%ptr
67 %ret = zext <2 x i1> %val to <2 x i64>
71 ; Test a v2i8->v2i64 extension.
72 define <2 x i64> @f8(<2 x i8> *%ptr) {
74 ; CHECK: vlrepb [[REG1:%v[0-9]+]], 0(%r2)
75 ; CHECK: vleb [[REG1]], 1(%r2), 1
76 ; CHECK: vuplhb [[REG2:%v[0-9]+]], [[REG1]]
77 ; CHECK: vuplhh [[REG3:%v[0-9]+]], [[REG2]]
78 ; CHECK: vuplhf %v24, [[REG3]]
80 %val = load <2 x i8>, <2 x i8> *%ptr
81 %ret = zext <2 x i8> %val to <2 x i64>
85 ; Test a v2i16->v2i64 extension.
86 define <2 x i64> @f9(<2 x i16> *%ptr) {
88 ; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)
89 ; CHECK: vuplhh [[REG2:%v[0-9]+]], [[REG1]]
90 ; CHECK: vuplhf %v24, [[REG2]]
92 %val = load <2 x i16>, <2 x i16> *%ptr
93 %ret = zext <2 x i16> %val to <2 x i64>
97 ; Test a v2i32->v2i64 extension.
98 define <2 x i64> @f10(<2 x i32> *%ptr) {
100 ; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
101 ; CHECK: vuplhf %v24, [[REG1]]
103 %val = load <2 x i32>, <2 x i32> *%ptr
104 %ret = zext <2 x i32> %val to <2 x i64>