1 ; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
2 target datalayout = "E-m:e-i64:64-n32:64"
3 target triple = "powerpc64-unknown-linux-gnu"
5 ; Function Attrs: nounwind readnone
6 define zeroext i1 @test1(float %v1, float %v2) #0 {
8 %cmp = fcmp oge float %v1, %v2
9 %cmp2 = fcmp ole float %v2, 0.000000e+00
10 %and5 = and i1 %cmp, %cmp2
14 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
15 ; CHECK-DAG: li [[REG1:[0-9]+]], 1
16 ; CHECK-DAG: lfs [[REG2:[0-9]+]],
17 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
20 ; CHECK: crnand [[REG4:[0-9]+]],
21 ; CHECK: isel 3, 0, [[REG1]], [[REG4]]
25 ; Function Attrs: nounwind readnone
26 define zeroext i1 @test2(float %v1, float %v2) #0 {
28 %cmp = fcmp oge float %v1, %v2
29 %cmp2 = fcmp ole float %v2, 0.000000e+00
30 %xor5 = xor i1 %cmp, %cmp2
34 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
35 ; CHECK-DAG: li [[REG1:[0-9]+]], 1
36 ; CHECK-DAG: lfs [[REG2:[0-9]+]],
37 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
40 ; CHECK: creqv [[REG4:[0-9]+]],
41 ; CHECK: isel 3, 0, [[REG1]], [[REG4]]
45 ; Function Attrs: nounwind readnone
46 define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 {
48 %cmp = fcmp oge float %v1, %v2
49 %cmp2 = fcmp ole float %v2, 0.000000e+00
50 %cmp4 = icmp ne i32 %x, -2
51 %and7 = and i1 %cmp2, %cmp4
52 %xor8 = xor i1 %cmp, %and7
56 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
57 ; CHECK-DAG: li [[REG1:[0-9]+]], 1
58 ; CHECK-DAG: lfs [[REG2:[0-9]+]],
59 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
63 ; CHECK: creqv [[REG4:[0-9]+]],
64 ; CHECK: isel 3, 0, [[REG1]], [[REG4]]
68 ; Function Attrs: nounwind readnone
69 define zeroext i1 @test4(i1 zeroext %v1, i1 zeroext %v2, i1 zeroext %v3) #0 {
71 %and8 = and i1 %v1, %v2
72 %or9 = or i1 %and8, %v3
76 ; CHECK: and [[REG1:[0-9]+]], 3, 4
77 ; CHECK: or 3, [[REG1]], 5
81 ; Function Attrs: nounwind readnone
82 define zeroext i1 @test5(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 {
84 %and6 = and i1 %v1, %v2
85 %cmp = icmp ne i32 %v3, -2
86 %or7 = or i1 %and6, %cmp
90 ; CHECK-DAG: and [[REG1:[0-9]+]], 3, 4
91 ; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2
92 ; CHECK-DAG: li [[REG3:[0-9]+]], 1
93 ; CHECK-DAG: andi. {{[0-9]+}}, [[REG1]], 1
94 ; CHECK-DAG: crandc [[REG5:[0-9]+]],
95 ; CHECK: isel 3, 0, [[REG3]], [[REG5]]
99 ; Function Attrs: nounwind readnone
100 define zeroext i1 @test6(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 {
102 %cmp = icmp ne i32 %v3, -2
103 %or6 = or i1 %cmp, %v2
104 %and7 = and i1 %or6, %v1
107 ; CHECK-LABEL: @test6
108 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
109 ; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2
110 ; CHECK-DAG: cror [[REG1:[0-9]+]], 1, 1
111 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
112 ; CHECK-DAG: li [[REG2:[0-9]+]], 1
113 ; CHECK-DAG: crorc [[REG4:[0-9]+]], 1,
114 ; CHECK-DAG: crnand [[REG5:[0-9]+]], [[REG4]], [[REG1]]
115 ; CHECK: isel 3, 0, [[REG2]], [[REG5]]
119 ; Function Attrs: nounwind readnone
120 define signext i32 @test7(i1 zeroext %v2, i32 signext %i1, i32 signext %i2) #0 {
122 %cond = select i1 %v2, i32 %i1, i32 %i2
125 ; CHECK-LABEL: @test7
126 ; CHECK: andi. {{[0-9]+}}, 3, 1
127 ; CHECK: isel [[REG1:[0-9]+]], 4, 5, 1
128 ; CHECK: extsw 3, [[REG1]]
132 ; Function Attrs: nounwind readnone
133 define float @test8(i1 zeroext %v2, float %v1, float %v3) #0 {
135 %cond = select i1 %v2, float %v1, float %v3
138 ; CHECK-LABEL: @test8
139 ; CHECK: andi. {{[0-9]+}}, 3, 1
140 ; CHECK: bclr 12, 1, 0
145 ; Function Attrs: nounwind readnone
146 define signext i32 @test10(i32 signext %v1, i32 signext %v2) #0 {
148 %tobool = icmp ne i32 %v1, 0
149 %lnot = icmp eq i32 %v2, 0
150 %and3 = and i1 %tobool, %lnot
151 %and = zext i1 %and3 to i32
154 ; CHECK-LABEL: @test10
155 ; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 0
156 ; CHECK-DAG: cmpwi {{[0-9]+}}, 4, 0
157 ; CHECK-DAG: li [[REG2:[0-9]+]], 1
158 ; CHECK-DAG: crorc [[REG3:[0-9]+]],
159 ; CHECK: isel 3, 0, [[REG2]], [[REG3]]
163 attributes #0 = { nounwind readnone }