1 ; Test the MSA intrinsics that are encoded with the I8 instruction format.
3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 @llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
6 @llvm_mips_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
8 define void @llvm_mips_andi_b_test() nounwind {
10 %0 = load <16 x i8>* @llvm_mips_andi_b_ARG1
11 %1 = tail call <16 x i8> @llvm.mips.andi.b(<16 x i8> %0, i32 25)
12 store <16 x i8> %1, <16 x i8>* @llvm_mips_andi_b_RES
16 declare <16 x i8> @llvm.mips.andi.b(<16 x i8>, i32) nounwind
18 ; CHECK: llvm_mips_andi_b_test:
22 ; CHECK: .size llvm_mips_andi_b_test
24 @llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
25 @llvm_mips_bmnzi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
26 @llvm_mips_bmnzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
28 define void @llvm_mips_bmnzi_b_test() nounwind {
30 %0 = load <16 x i8>* @llvm_mips_bmnzi_b_ARG1
31 %1 = load <16 x i8>* @llvm_mips_bmnzi_b_ARG2
32 %2 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 25)
33 store <16 x i8> %2, <16 x i8>* @llvm_mips_bmnzi_b_RES
37 declare <16 x i8> @llvm.mips.bmnzi.b(<16 x i8>, <16 x i8>, i32) nounwind
39 ; CHECK: llvm_mips_bmnzi_b_test:
40 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG1)(
41 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG2)(
42 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])
43 ; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])
44 ; CHECK-DAG: bmnzi.b [[R3]], [[R4]], 25
45 ; CHECK-DAG: st.b [[R3]], 0(
46 ; CHECK: .size llvm_mips_bmnzi_b_test
48 @llvm_mips_bmzi_b_ARG1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
49 @llvm_mips_bmzi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
50 @llvm_mips_bmzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
52 define void @llvm_mips_bmzi_b_test() nounwind {
54 %0 = load <16 x i8>* @llvm_mips_bmzi_b_ARG1
55 %1 = load <16 x i8>* @llvm_mips_bmzi_b_ARG2
56 %2 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 25)
57 store <16 x i8> %2, <16 x i8>* @llvm_mips_bmzi_b_RES
61 declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, <16 x i8>, i32) nounwind
63 ; CHECK: llvm_mips_bmzi_b_test:
64 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmzi_b_ARG1)(
65 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmzi_b_ARG2)(
66 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])
67 ; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])
68 ; bmnzi.b is the same as bmzi.b with ws and wd_in swapped
69 ; CHECK-DAG: bmnzi.b [[R4]], [[R3]], 25
70 ; CHECK-DAG: st.b [[R4]], 0(
71 ; CHECK: .size llvm_mips_bmzi_b_test
73 @llvm_mips_bseli_b_ARG1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
74 @llvm_mips_bseli_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
75 @llvm_mips_bseli_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
77 define void @llvm_mips_bseli_b_test() nounwind {
79 %0 = load <16 x i8>* @llvm_mips_bseli_b_ARG1
80 %1 = load <16 x i8>* @llvm_mips_bseli_b_ARG2
81 %2 = tail call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %0, <16 x i8> %1, i32 25)
82 store <16 x i8> %2, <16 x i8>* @llvm_mips_bseli_b_RES
86 declare <16 x i8> @llvm.mips.bseli.b(<16 x i8>, <16 x i8>, i32) nounwind
88 ; CHECK: llvm_mips_bseli_b_test:
89 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bseli_b_ARG1)(
90 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bseli_b_ARG2)(
91 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])
92 ; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])
93 ; CHECK-DAG: bseli.b [[R3]], [[R4]], 25
94 ; CHECK-DAG: st.b [[R3]], 0(
95 ; CHECK: .size llvm_mips_bseli_b_test
97 @llvm_mips_nori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
98 @llvm_mips_nori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
100 define void @llvm_mips_nori_b_test() nounwind {
102 %0 = load <16 x i8>* @llvm_mips_nori_b_ARG1
103 %1 = tail call <16 x i8> @llvm.mips.nori.b(<16 x i8> %0, i32 25)
104 store <16 x i8> %1, <16 x i8>* @llvm_mips_nori_b_RES
108 declare <16 x i8> @llvm.mips.nori.b(<16 x i8>, i32) nounwind
110 ; CHECK: llvm_mips_nori_b_test:
114 ; CHECK: .size llvm_mips_nori_b_test
116 @llvm_mips_ori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
117 @llvm_mips_ori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
119 define void @llvm_mips_ori_b_test() nounwind {
121 %0 = load <16 x i8>* @llvm_mips_ori_b_ARG1
122 %1 = tail call <16 x i8> @llvm.mips.ori.b(<16 x i8> %0, i32 25)
123 store <16 x i8> %1, <16 x i8>* @llvm_mips_ori_b_RES
127 declare <16 x i8> @llvm.mips.ori.b(<16 x i8>, i32) nounwind
129 ; CHECK: llvm_mips_ori_b_test:
133 ; CHECK: .size llvm_mips_ori_b_test
135 @llvm_mips_shf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
136 @llvm_mips_shf_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
138 define void @llvm_mips_shf_b_test() nounwind {
140 %0 = load <16 x i8>* @llvm_mips_shf_b_ARG1
141 %1 = tail call <16 x i8> @llvm.mips.shf.b(<16 x i8> %0, i32 25)
142 store <16 x i8> %1, <16 x i8>* @llvm_mips_shf_b_RES
146 declare <16 x i8> @llvm.mips.shf.b(<16 x i8>, i32) nounwind
148 ; CHECK: llvm_mips_shf_b_test:
152 ; CHECK: .size llvm_mips_shf_b_test
154 @llvm_mips_shf_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
155 @llvm_mips_shf_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
157 define void @llvm_mips_shf_h_test() nounwind {
159 %0 = load <8 x i16>* @llvm_mips_shf_h_ARG1
160 %1 = tail call <8 x i16> @llvm.mips.shf.h(<8 x i16> %0, i32 25)
161 store <8 x i16> %1, <8 x i16>* @llvm_mips_shf_h_RES
165 declare <8 x i16> @llvm.mips.shf.h(<8 x i16>, i32) nounwind
167 ; CHECK: llvm_mips_shf_h_test:
171 ; CHECK: .size llvm_mips_shf_h_test
173 @llvm_mips_shf_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
174 @llvm_mips_shf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
176 define void @llvm_mips_shf_w_test() nounwind {
178 %0 = load <4 x i32>* @llvm_mips_shf_w_ARG1
179 %1 = tail call <4 x i32> @llvm.mips.shf.w(<4 x i32> %0, i32 25)
180 store <4 x i32> %1, <4 x i32>* @llvm_mips_shf_w_RES
184 declare <4 x i32> @llvm.mips.shf.w(<4 x i32>, i32) nounwind
186 ; CHECK: llvm_mips_shf_w_test:
190 ; CHECK: .size llvm_mips_shf_w_test
192 @llvm_mips_xori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
193 @llvm_mips_xori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
195 define void @llvm_mips_xori_b_test() nounwind {
197 %0 = load <16 x i8>* @llvm_mips_xori_b_ARG1
198 %1 = tail call <16 x i8> @llvm.mips.xori.b(<16 x i8> %0, i32 25)
199 store <16 x i8> %1, <16 x i8>* @llvm_mips_xori_b_RES
203 declare <16 x i8> @llvm.mips.xori.b(<16 x i8>, i32) nounwind
205 ; CHECK: llvm_mips_xori_b_test:
209 ; CHECK: .size llvm_mips_xori_b_test