1 ; Test the MSA intrinsics that are encoded with the ELM instruction format and
2 ; are element extraction operations.
4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
5 ; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
6 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \
7 ; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32
9 @llvm_mips_copy_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
10 @llvm_mips_copy_s_b_RES = global i32 0, align 16
12 define void @llvm_mips_copy_s_b_test() nounwind {
14 %0 = load <16 x i8>* @llvm_mips_copy_s_b_ARG1
15 %1 = tail call i32 @llvm.mips.copy.s.b(<16 x i8> %0, i32 1)
16 store i32 %1, i32* @llvm_mips_copy_s_b_RES
20 declare i32 @llvm.mips.copy.s.b(<16 x i8>, i32) nounwind
22 ; MIPS-ANY: llvm_mips_copy_s_b_test:
23 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_b_ARG1)
24 ; MIPS-ANY-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])
25 ; MIPS-ANY-DAG: copy_s.b [[RD:\$[0-9]+]], [[WS]][1]
26 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_b_RES)
27 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
28 ; MIPS-ANY: .size llvm_mips_copy_s_b_test
30 @llvm_mips_copy_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
31 @llvm_mips_copy_s_h_RES = global i32 0, align 16
33 define void @llvm_mips_copy_s_h_test() nounwind {
35 %0 = load <8 x i16>* @llvm_mips_copy_s_h_ARG1
36 %1 = tail call i32 @llvm.mips.copy.s.h(<8 x i16> %0, i32 1)
37 store i32 %1, i32* @llvm_mips_copy_s_h_RES
41 declare i32 @llvm.mips.copy.s.h(<8 x i16>, i32) nounwind
43 ; MIPS-ANY: llvm_mips_copy_s_h_test:
44 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_h_ARG1)
45 ; MIPS-ANY-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])
46 ; MIPS-ANY-DAG: copy_s.h [[RD:\$[0-9]+]], [[WS]][1]
47 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_h_RES)
48 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
49 ; MIPS-ANY: .size llvm_mips_copy_s_h_test
51 @llvm_mips_copy_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
52 @llvm_mips_copy_s_w_RES = global i32 0, align 16
54 define void @llvm_mips_copy_s_w_test() nounwind {
56 %0 = load <4 x i32>* @llvm_mips_copy_s_w_ARG1
57 %1 = tail call i32 @llvm.mips.copy.s.w(<4 x i32> %0, i32 1)
58 store i32 %1, i32* @llvm_mips_copy_s_w_RES
62 declare i32 @llvm.mips.copy.s.w(<4 x i32>, i32) nounwind
64 ; MIPS-ANY: llvm_mips_copy_s_w_test:
65 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_w_ARG1)
66 ; MIPS-ANY-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
67 ; MIPS-ANY-DAG: copy_s.w [[RD:\$[0-9]+]], [[WS]][1]
68 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_w_RES)
69 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
70 ; MIPS-ANY: .size llvm_mips_copy_s_w_test
72 @llvm_mips_copy_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
73 @llvm_mips_copy_s_d_RES = global i64 0, align 16
75 define void @llvm_mips_copy_s_d_test() nounwind {
77 %0 = load <2 x i64>* @llvm_mips_copy_s_d_ARG1
78 %1 = tail call i64 @llvm.mips.copy.s.d(<2 x i64> %0, i32 1)
79 store i64 %1, i64* @llvm_mips_copy_s_d_RES
83 declare i64 @llvm.mips.copy.s.d(<2 x i64>, i32) nounwind
85 ; MIPS-ANY: llvm_mips_copy_s_d_test:
86 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_s_d_ARG1)
87 ; MIPS32-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
88 ; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2]
89 ; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]
90 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_d_RES)
91 ; MIPS32-DAG: sw [[RD1]], 0([[RES]])
92 ; MIPS32-DAG: sw [[RD2]], 4([[RES]])
93 ; MIPS-ANY: .size llvm_mips_copy_s_d_test
95 @llvm_mips_copy_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
96 @llvm_mips_copy_u_b_RES = global i32 0, align 16
98 define void @llvm_mips_copy_u_b_test() nounwind {
100 %0 = load <16 x i8>* @llvm_mips_copy_u_b_ARG1
101 %1 = tail call i32 @llvm.mips.copy.u.b(<16 x i8> %0, i32 1)
102 store i32 %1, i32* @llvm_mips_copy_u_b_RES
106 declare i32 @llvm.mips.copy.u.b(<16 x i8>, i32) nounwind
108 ; MIPS-ANY: llvm_mips_copy_u_b_test:
109 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_b_ARG1)
110 ; MIPS-ANY-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])
111 ; MIPS-ANY-DAG: copy_u.b [[RD:\$[0-9]+]], [[WS]][1]
112 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_b_RES)
113 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
114 ; MIPS-ANY: .size llvm_mips_copy_u_b_test
116 @llvm_mips_copy_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
117 @llvm_mips_copy_u_h_RES = global i32 0, align 16
119 define void @llvm_mips_copy_u_h_test() nounwind {
121 %0 = load <8 x i16>* @llvm_mips_copy_u_h_ARG1
122 %1 = tail call i32 @llvm.mips.copy.u.h(<8 x i16> %0, i32 1)
123 store i32 %1, i32* @llvm_mips_copy_u_h_RES
127 declare i32 @llvm.mips.copy.u.h(<8 x i16>, i32) nounwind
129 ; MIPS-ANY: llvm_mips_copy_u_h_test:
130 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_h_ARG1)
131 ; MIPS-ANY-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])
132 ; MIPS-ANY-DAG: copy_u.h [[RD:\$[0-9]+]], [[WS]][1]
133 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_h_RES)
134 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
135 ; MIPS-ANY: .size llvm_mips_copy_u_h_test
137 @llvm_mips_copy_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
138 @llvm_mips_copy_u_w_RES = global i32 0, align 16
140 define void @llvm_mips_copy_u_w_test() nounwind {
142 %0 = load <4 x i32>* @llvm_mips_copy_u_w_ARG1
143 %1 = tail call i32 @llvm.mips.copy.u.w(<4 x i32> %0, i32 1)
144 store i32 %1, i32* @llvm_mips_copy_u_w_RES
148 declare i32 @llvm.mips.copy.u.w(<4 x i32>, i32) nounwind
150 ; MIPS-ANY: llvm_mips_copy_u_w_test:
151 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_w_ARG1)
152 ; MIPS-ANY-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
153 ; MIPS-ANY-DAG: copy_u.w [[RD:\$[0-9]+]], [[WS]][1]
154 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_w_RES)
155 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
156 ; MIPS-ANY: .size llvm_mips_copy_u_w_test
158 @llvm_mips_copy_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
159 @llvm_mips_copy_u_d_RES = global i64 0, align 16
161 define void @llvm_mips_copy_u_d_test() nounwind {
163 %0 = load <2 x i64>* @llvm_mips_copy_u_d_ARG1
164 %1 = tail call i64 @llvm.mips.copy.u.d(<2 x i64> %0, i32 1)
165 store i64 %1, i64* @llvm_mips_copy_u_d_RES
169 declare i64 @llvm.mips.copy.u.d(<2 x i64>, i32) nounwind
171 ; MIPS-ANY: llvm_mips_copy_u_d_test:
172 ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_d_ARG1)
173 ; MIPS32-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
174 ; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2]
175 ; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]
176 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_d_RES)
177 ; MIPS32-DAG: sw [[RD1]], 0([[RES]])
178 ; MIPS32-DAG: sw [[RD2]], 4([[RES]])
179 ; MIPS-ANY: .size llvm_mips_copy_u_d_test