1 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
3 define void @ceq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
6 %1 = load <16 x i8>* %a
7 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
8 %2 = load <16 x i8>* %b
9 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
10 %3 = icmp eq <16 x i8> %1, %2
11 %4 = sext <16 x i1> %3 to <16 x i8>
12 ; CHECK-DAG: ceq.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
13 store <16 x i8> %4, <16 x i8>* %c
14 ; CHECK-DAG: st.b [[R3]], 0($4)
17 ; CHECK: .size ceq_v16i8
20 define void @ceq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
23 %1 = load <8 x i16>* %a
24 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
25 %2 = load <8 x i16>* %b
26 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
27 %3 = icmp eq <8 x i16> %1, %2
28 %4 = sext <8 x i1> %3 to <8 x i16>
29 ; CHECK-DAG: ceq.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
30 store <8 x i16> %4, <8 x i16>* %c
31 ; CHECK-DAG: st.h [[R3]], 0($4)
34 ; CHECK: .size ceq_v8i16
37 define void @ceq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
40 %1 = load <4 x i32>* %a
41 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
42 %2 = load <4 x i32>* %b
43 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
44 %3 = icmp eq <4 x i32> %1, %2
45 %4 = sext <4 x i1> %3 to <4 x i32>
46 ; CHECK-DAG: ceq.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
47 store <4 x i32> %4, <4 x i32>* %c
48 ; CHECK-DAG: st.w [[R3]], 0($4)
51 ; CHECK: .size ceq_v4i32
54 define void @ceq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
57 %1 = load <2 x i64>* %a
58 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
59 %2 = load <2 x i64>* %b
60 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
61 %3 = icmp eq <2 x i64> %1, %2
62 %4 = sext <2 x i1> %3 to <2 x i64>
63 ; CHECK-DAG: ceq.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
64 store <2 x i64> %4, <2 x i64>* %c
65 ; CHECK-DAG: st.d [[R3]], 0($4)
68 ; CHECK: .size ceq_v2i64
71 define void @cle_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
74 %1 = load <16 x i8>* %a
75 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
76 %2 = load <16 x i8>* %b
77 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
78 %3 = icmp sle <16 x i8> %1, %2
79 %4 = sext <16 x i1> %3 to <16 x i8>
80 ; CHECK-DAG: cle_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
81 store <16 x i8> %4, <16 x i8>* %c
82 ; CHECK-DAG: st.b [[R3]], 0($4)
85 ; CHECK: .size cle_s_v16i8
88 define void @cle_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
91 %1 = load <8 x i16>* %a
92 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
93 %2 = load <8 x i16>* %b
94 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
95 %3 = icmp sle <8 x i16> %1, %2
96 %4 = sext <8 x i1> %3 to <8 x i16>
97 ; CHECK-DAG: cle_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
98 store <8 x i16> %4, <8 x i16>* %c
99 ; CHECK-DAG: st.h [[R3]], 0($4)
102 ; CHECK: .size cle_s_v8i16
105 define void @cle_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
106 ; CHECK: cle_s_v4i32:
108 %1 = load <4 x i32>* %a
109 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
110 %2 = load <4 x i32>* %b
111 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
112 %3 = icmp sle <4 x i32> %1, %2
113 %4 = sext <4 x i1> %3 to <4 x i32>
114 ; CHECK-DAG: cle_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
115 store <4 x i32> %4, <4 x i32>* %c
116 ; CHECK-DAG: st.w [[R3]], 0($4)
119 ; CHECK: .size cle_s_v4i32
122 define void @cle_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
123 ; CHECK: cle_s_v2i64:
125 %1 = load <2 x i64>* %a
126 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
127 %2 = load <2 x i64>* %b
128 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
129 %3 = icmp sle <2 x i64> %1, %2
130 %4 = sext <2 x i1> %3 to <2 x i64>
131 ; CHECK-DAG: cle_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
132 store <2 x i64> %4, <2 x i64>* %c
133 ; CHECK-DAG: st.d [[R3]], 0($4)
136 ; CHECK: .size cle_s_v2i64
139 define void @cle_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
140 ; CHECK: cle_u_v16i8:
142 %1 = load <16 x i8>* %a
143 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
144 %2 = load <16 x i8>* %b
145 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
146 %3 = icmp ule <16 x i8> %1, %2
147 %4 = sext <16 x i1> %3 to <16 x i8>
148 ; CHECK-DAG: cle_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
149 store <16 x i8> %4, <16 x i8>* %c
150 ; CHECK-DAG: st.b [[R3]], 0($4)
153 ; CHECK: .size cle_u_v16i8
156 define void @cle_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
157 ; CHECK: cle_u_v8i16:
159 %1 = load <8 x i16>* %a
160 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
161 %2 = load <8 x i16>* %b
162 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
163 %3 = icmp ule <8 x i16> %1, %2
164 %4 = sext <8 x i1> %3 to <8 x i16>
165 ; CHECK-DAG: cle_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
166 store <8 x i16> %4, <8 x i16>* %c
167 ; CHECK-DAG: st.h [[R3]], 0($4)
170 ; CHECK: .size cle_u_v8i16
173 define void @cle_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
174 ; CHECK: cle_u_v4i32:
176 %1 = load <4 x i32>* %a
177 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
178 %2 = load <4 x i32>* %b
179 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
180 %3 = icmp ule <4 x i32> %1, %2
181 %4 = sext <4 x i1> %3 to <4 x i32>
182 ; CHECK-DAG: cle_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
183 store <4 x i32> %4, <4 x i32>* %c
184 ; CHECK-DAG: st.w [[R3]], 0($4)
187 ; CHECK: .size cle_u_v4i32
190 define void @cle_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
191 ; CHECK: cle_u_v2i64:
193 %1 = load <2 x i64>* %a
194 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
195 %2 = load <2 x i64>* %b
196 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
197 %3 = icmp ule <2 x i64> %1, %2
198 %4 = sext <2 x i1> %3 to <2 x i64>
199 ; CHECK-DAG: cle_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
200 store <2 x i64> %4, <2 x i64>* %c
201 ; CHECK-DAG: st.d [[R3]], 0($4)
204 ; CHECK: .size cle_u_v2i64
207 define void @clt_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
208 ; CHECK: clt_s_v16i8:
210 %1 = load <16 x i8>* %a
211 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
212 %2 = load <16 x i8>* %b
213 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
214 %3 = icmp slt <16 x i8> %1, %2
215 %4 = sext <16 x i1> %3 to <16 x i8>
216 ; CHECK-DAG: clt_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
217 store <16 x i8> %4, <16 x i8>* %c
218 ; CHECK-DAG: st.b [[R3]], 0($4)
221 ; CHECK: .size clt_s_v16i8
224 define void @clt_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
225 ; CHECK: clt_s_v8i16:
227 %1 = load <8 x i16>* %a
228 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
229 %2 = load <8 x i16>* %b
230 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
231 %3 = icmp slt <8 x i16> %1, %2
232 %4 = sext <8 x i1> %3 to <8 x i16>
233 ; CHECK-DAG: clt_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
234 store <8 x i16> %4, <8 x i16>* %c
235 ; CHECK-DAG: st.h [[R3]], 0($4)
238 ; CHECK: .size clt_s_v8i16
241 define void @clt_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
242 ; CHECK: clt_s_v4i32:
244 %1 = load <4 x i32>* %a
245 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
246 %2 = load <4 x i32>* %b
247 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
248 %3 = icmp slt <4 x i32> %1, %2
249 %4 = sext <4 x i1> %3 to <4 x i32>
250 ; CHECK-DAG: clt_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
251 store <4 x i32> %4, <4 x i32>* %c
252 ; CHECK-DAG: st.w [[R3]], 0($4)
255 ; CHECK: .size clt_s_v4i32
258 define void @clt_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
259 ; CHECK: clt_s_v2i64:
261 %1 = load <2 x i64>* %a
262 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
263 %2 = load <2 x i64>* %b
264 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
265 %3 = icmp slt <2 x i64> %1, %2
266 %4 = sext <2 x i1> %3 to <2 x i64>
267 ; CHECK-DAG: clt_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
268 store <2 x i64> %4, <2 x i64>* %c
269 ; CHECK-DAG: st.d [[R3]], 0($4)
272 ; CHECK: .size clt_s_v2i64
275 define void @clt_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
276 ; CHECK: clt_u_v16i8:
278 %1 = load <16 x i8>* %a
279 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
280 %2 = load <16 x i8>* %b
281 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
282 %3 = icmp ult <16 x i8> %1, %2
283 %4 = sext <16 x i1> %3 to <16 x i8>
284 ; CHECK-DAG: clt_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
285 store <16 x i8> %4, <16 x i8>* %c
286 ; CHECK-DAG: st.b [[R3]], 0($4)
289 ; CHECK: .size clt_u_v16i8
292 define void @clt_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
293 ; CHECK: clt_u_v8i16:
295 %1 = load <8 x i16>* %a
296 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
297 %2 = load <8 x i16>* %b
298 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
299 %3 = icmp ult <8 x i16> %1, %2
300 %4 = sext <8 x i1> %3 to <8 x i16>
301 ; CHECK-DAG: clt_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
302 store <8 x i16> %4, <8 x i16>* %c
303 ; CHECK-DAG: st.h [[R3]], 0($4)
306 ; CHECK: .size clt_u_v8i16
309 define void @clt_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
310 ; CHECK: clt_u_v4i32:
312 %1 = load <4 x i32>* %a
313 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
314 %2 = load <4 x i32>* %b
315 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
316 %3 = icmp ult <4 x i32> %1, %2
317 %4 = sext <4 x i1> %3 to <4 x i32>
318 ; CHECK-DAG: clt_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
319 store <4 x i32> %4, <4 x i32>* %c
320 ; CHECK-DAG: st.w [[R3]], 0($4)
323 ; CHECK: .size clt_u_v4i32
326 define void @clt_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
327 ; CHECK: clt_u_v2i64:
329 %1 = load <2 x i64>* %a
330 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
331 %2 = load <2 x i64>* %b
332 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
333 %3 = icmp ult <2 x i64> %1, %2
334 %4 = sext <2 x i1> %3 to <2 x i64>
335 ; CHECK-DAG: clt_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
336 store <2 x i64> %4, <2 x i64>* %c
337 ; CHECK-DAG: st.d [[R3]], 0($4)
340 ; CHECK: .size clt_u_v2i64
343 define void @ceqi_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
346 %1 = load <16 x i8>* %a
347 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
348 %2 = icmp eq <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
349 %3 = sext <16 x i1> %2 to <16 x i8>
350 ; CHECK-DAG: ceqi.b [[R3:\$w[0-9]+]], [[R1]], 1
351 store <16 x i8> %3, <16 x i8>* %c
352 ; CHECK-DAG: st.b [[R3]], 0($4)
355 ; CHECK: .size ceqi_v16i8
358 define void @ceqi_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
361 %1 = load <8 x i16>* %a
362 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
363 %2 = icmp eq <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
364 %3 = sext <8 x i1> %2 to <8 x i16>
365 ; CHECK-DAG: ceqi.h [[R3:\$w[0-9]+]], [[R1]], 1
366 store <8 x i16> %3, <8 x i16>* %c
367 ; CHECK-DAG: st.h [[R3]], 0($4)
370 ; CHECK: .size ceqi_v8i16
373 define void @ceqi_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
376 %1 = load <4 x i32>* %a
377 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
378 %2 = icmp eq <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
379 %3 = sext <4 x i1> %2 to <4 x i32>
380 ; CHECK-DAG: ceqi.w [[R3:\$w[0-9]+]], [[R1]], 1
381 store <4 x i32> %3, <4 x i32>* %c
382 ; CHECK-DAG: st.w [[R3]], 0($4)
385 ; CHECK: .size ceqi_v4i32
388 define void @ceqi_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
391 %1 = load <2 x i64>* %a
392 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
393 %2 = icmp eq <2 x i64> %1, <i64 1, i64 1>
394 %3 = sext <2 x i1> %2 to <2 x i64>
395 ; CHECK-DAG: ceqi.d [[R3:\$w[0-9]+]], [[R1]], 1
396 store <2 x i64> %3, <2 x i64>* %c
397 ; CHECK-DAG: st.d [[R3]], 0($4)
400 ; CHECK: .size ceqi_v2i64
403 define void @clei_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
404 ; CHECK: clei_s_v16i8:
406 %1 = load <16 x i8>* %a
407 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
408 %2 = icmp sle <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
409 %3 = sext <16 x i1> %2 to <16 x i8>
410 ; CHECK-DAG: clei_s.b [[R3:\$w[0-9]+]], [[R1]], 1
411 store <16 x i8> %3, <16 x i8>* %c
412 ; CHECK-DAG: st.b [[R3]], 0($4)
415 ; CHECK: .size clei_s_v16i8
418 define void @clei_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
419 ; CHECK: clei_s_v8i16:
421 %1 = load <8 x i16>* %a
422 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
423 %2 = icmp sle <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
424 %3 = sext <8 x i1> %2 to <8 x i16>
425 ; CHECK-DAG: clei_s.h [[R3:\$w[0-9]+]], [[R1]], 1
426 store <8 x i16> %3, <8 x i16>* %c
427 ; CHECK-DAG: st.h [[R3]], 0($4)
430 ; CHECK: .size clei_s_v8i16
433 define void @clei_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
434 ; CHECK: clei_s_v4i32:
436 %1 = load <4 x i32>* %a
437 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
438 %2 = icmp sle <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
439 %3 = sext <4 x i1> %2 to <4 x i32>
440 ; CHECK-DAG: clei_s.w [[R3:\$w[0-9]+]], [[R1]], 1
441 store <4 x i32> %3, <4 x i32>* %c
442 ; CHECK-DAG: st.w [[R3]], 0($4)
445 ; CHECK: .size clei_s_v4i32
448 define void @clei_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
449 ; CHECK: clei_s_v2i64:
451 %1 = load <2 x i64>* %a
452 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
453 %2 = icmp sle <2 x i64> %1, <i64 1, i64 1>
454 %3 = sext <2 x i1> %2 to <2 x i64>
455 ; CHECK-DAG: clei_s.d [[R3:\$w[0-9]+]], [[R1]], 1
456 store <2 x i64> %3, <2 x i64>* %c
457 ; CHECK-DAG: st.d [[R3]], 0($4)
460 ; CHECK: .size clei_s_v2i64
463 define void @clei_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
464 ; CHECK: clei_u_v16i8:
466 %1 = load <16 x i8>* %a
467 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
468 %2 = icmp ule <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
469 %3 = sext <16 x i1> %2 to <16 x i8>
470 ; CHECK-DAG: clei_u.b [[R3:\$w[0-9]+]], [[R1]], 1
471 store <16 x i8> %3, <16 x i8>* %c
472 ; CHECK-DAG: st.b [[R3]], 0($4)
475 ; CHECK: .size clei_u_v16i8
478 define void @clei_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
479 ; CHECK: clei_u_v8i16:
481 %1 = load <8 x i16>* %a
482 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
483 %2 = icmp ule <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
484 %3 = sext <8 x i1> %2 to <8 x i16>
485 ; CHECK-DAG: clei_u.h [[R3:\$w[0-9]+]], [[R1]], 1
486 store <8 x i16> %3, <8 x i16>* %c
487 ; CHECK-DAG: st.h [[R3]], 0($4)
490 ; CHECK: .size clei_u_v8i16
493 define void @clei_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
494 ; CHECK: clei_u_v4i32:
496 %1 = load <4 x i32>* %a
497 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
498 %2 = icmp ule <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
499 %3 = sext <4 x i1> %2 to <4 x i32>
500 ; CHECK-DAG: clei_u.w [[R3:\$w[0-9]+]], [[R1]], 1
501 store <4 x i32> %3, <4 x i32>* %c
502 ; CHECK-DAG: st.w [[R3]], 0($4)
505 ; CHECK: .size clei_u_v4i32
508 define void @clei_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
509 ; CHECK: clei_u_v2i64:
511 %1 = load <2 x i64>* %a
512 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
513 %2 = icmp ule <2 x i64> %1, <i64 1, i64 1>
514 %3 = sext <2 x i1> %2 to <2 x i64>
515 ; CHECK-DAG: clei_u.d [[R3:\$w[0-9]+]], [[R1]], 1
516 store <2 x i64> %3, <2 x i64>* %c
517 ; CHECK-DAG: st.d [[R3]], 0($4)
520 ; CHECK: .size clei_u_v2i64
523 define void @clti_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
524 ; CHECK: clti_s_v16i8:
526 %1 = load <16 x i8>* %a
527 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
528 %2 = icmp slt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
529 %3 = sext <16 x i1> %2 to <16 x i8>
530 ; CHECK-DAG: clti_s.b [[R3:\$w[0-9]+]], [[R1]], 1
531 store <16 x i8> %3, <16 x i8>* %c
532 ; CHECK-DAG: st.b [[R3]], 0($4)
535 ; CHECK: .size clti_s_v16i8
538 define void @clti_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
539 ; CHECK: clti_s_v8i16:
541 %1 = load <8 x i16>* %a
542 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
543 %2 = icmp slt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
544 %3 = sext <8 x i1> %2 to <8 x i16>
545 ; CHECK-DAG: clti_s.h [[R3:\$w[0-9]+]], [[R1]], 1
546 store <8 x i16> %3, <8 x i16>* %c
547 ; CHECK-DAG: st.h [[R3]], 0($4)
550 ; CHECK: .size clti_s_v8i16
553 define void @clti_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
554 ; CHECK: clti_s_v4i32:
556 %1 = load <4 x i32>* %a
557 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
558 %2 = icmp slt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
559 %3 = sext <4 x i1> %2 to <4 x i32>
560 ; CHECK-DAG: clti_s.w [[R3:\$w[0-9]+]], [[R1]], 1
561 store <4 x i32> %3, <4 x i32>* %c
562 ; CHECK-DAG: st.w [[R3]], 0($4)
565 ; CHECK: .size clti_s_v4i32
568 define void @clti_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
569 ; CHECK: clti_s_v2i64:
571 %1 = load <2 x i64>* %a
572 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
573 %2 = icmp slt <2 x i64> %1, <i64 1, i64 1>
574 %3 = sext <2 x i1> %2 to <2 x i64>
575 ; CHECK-DAG: clti_s.d [[R3:\$w[0-9]+]], [[R1]], 1
576 store <2 x i64> %3, <2 x i64>* %c
577 ; CHECK-DAG: st.d [[R3]], 0($4)
580 ; CHECK: .size clti_s_v2i64
583 define void @clti_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
584 ; CHECK: clti_u_v16i8:
586 %1 = load <16 x i8>* %a
587 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
588 %2 = icmp ult <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
589 %3 = sext <16 x i1> %2 to <16 x i8>
590 ; CHECK-DAG: clti_u.b [[R3:\$w[0-9]+]], [[R1]], 1
591 store <16 x i8> %3, <16 x i8>* %c
592 ; CHECK-DAG: st.b [[R3]], 0($4)
595 ; CHECK: .size clti_u_v16i8
598 define void @clti_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
599 ; CHECK: clti_u_v8i16:
601 %1 = load <8 x i16>* %a
602 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
603 %2 = icmp ult <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
604 %3 = sext <8 x i1> %2 to <8 x i16>
605 ; CHECK-DAG: clti_u.h [[R3:\$w[0-9]+]], [[R1]], 1
606 store <8 x i16> %3, <8 x i16>* %c
607 ; CHECK-DAG: st.h [[R3]], 0($4)
610 ; CHECK: .size clti_u_v8i16
613 define void @clti_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
614 ; CHECK: clti_u_v4i32:
616 %1 = load <4 x i32>* %a
617 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
618 %2 = icmp ult <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
619 %3 = sext <4 x i1> %2 to <4 x i32>
620 ; CHECK-DAG: clti_u.w [[R3:\$w[0-9]+]], [[R1]], 1
621 store <4 x i32> %3, <4 x i32>* %c
622 ; CHECK-DAG: st.w [[R3]], 0($4)
625 ; CHECK: .size clti_u_v4i32
628 define void @clti_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
629 ; CHECK: clti_u_v2i64:
631 %1 = load <2 x i64>* %a
632 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
633 %2 = icmp ult <2 x i64> %1, <i64 1, i64 1>
634 %3 = sext <2 x i1> %2 to <2 x i64>
635 ; CHECK-DAG: clti_u.d [[R3:\$w[0-9]+]], [[R1]], 1
636 store <2 x i64> %3, <2 x i64>* %c
637 ; CHECK-DAG: st.d [[R3]], 0($4)
640 ; CHECK: .size clti_u_v2i64
643 define void @bsel_s_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
644 <16 x i8>* %c) nounwind {
645 ; CHECK: bsel_s_v16i8:
647 %1 = load <16 x i8>* %a
648 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
649 %2 = load <16 x i8>* %b
650 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
651 %3 = load <16 x i8>* %c
652 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
653 %4 = icmp sgt <16 x i8> %1, %2
654 ; CHECK-DAG: clt_s.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
655 %5 = select <16 x i1> %4, <16 x i8> %1, <16 x i8> %3
656 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
657 store <16 x i8> %5, <16 x i8>* %d
658 ; CHECK-DAG: st.b [[R4]], 0($4)
661 ; CHECK: .size bsel_s_v16i8
664 define void @bsel_s_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
665 <8 x i16>* %c) nounwind {
666 ; CHECK: bsel_s_v8i16:
668 %1 = load <8 x i16>* %a
669 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
670 %2 = load <8 x i16>* %b
671 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
672 %3 = load <8 x i16>* %c
673 ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
674 %4 = icmp sgt <8 x i16> %1, %2
675 ; CHECK-DAG: clt_s.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
676 %5 = select <8 x i1> %4, <8 x i16> %1, <8 x i16> %3
677 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
678 store <8 x i16> %5, <8 x i16>* %d
679 ; CHECK-DAG: st.h [[R4]], 0($4)
682 ; CHECK: .size bsel_s_v8i16
685 define void @bsel_s_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
686 <4 x i32>* %c) nounwind {
687 ; CHECK: bsel_s_v4i32:
689 %1 = load <4 x i32>* %a
690 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
691 %2 = load <4 x i32>* %b
692 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
693 %3 = load <4 x i32>* %c
694 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
695 %4 = icmp sgt <4 x i32> %1, %2
696 ; CHECK-DAG: clt_s.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
697 %5 = select <4 x i1> %4, <4 x i32> %1, <4 x i32> %3
698 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
699 store <4 x i32> %5, <4 x i32>* %d
700 ; CHECK-DAG: st.w [[R4]], 0($4)
703 ; CHECK: .size bsel_s_v4i32
706 define void @bsel_s_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
707 <2 x i64>* %c) nounwind {
708 ; CHECK: bsel_s_v2i64:
710 %1 = load <2 x i64>* %a
711 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
712 %2 = load <2 x i64>* %b
713 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
714 %3 = load <2 x i64>* %c
715 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
716 %4 = icmp sgt <2 x i64> %1, %2
717 ; CHECK-DAG: clt_s.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
718 %5 = select <2 x i1> %4, <2 x i64> %1, <2 x i64> %3
719 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
720 store <2 x i64> %5, <2 x i64>* %d
721 ; CHECK-DAG: st.d [[R4]], 0($4)
724 ; CHECK: .size bsel_s_v2i64
727 define void @bsel_u_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
728 <16 x i8>* %c) nounwind {
729 ; CHECK: bsel_u_v16i8:
731 %1 = load <16 x i8>* %a
732 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
733 %2 = load <16 x i8>* %b
734 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
735 %3 = load <16 x i8>* %c
736 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0($7)
737 %4 = icmp ugt <16 x i8> %1, %2
738 ; CHECK-DAG: clt_u.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
739 %5 = select <16 x i1> %4, <16 x i8> %1, <16 x i8> %3
740 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
741 store <16 x i8> %5, <16 x i8>* %d
742 ; CHECK-DAG: st.b [[R4]], 0($4)
745 ; CHECK: .size bsel_u_v16i8
748 define void @bsel_u_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
749 <8 x i16>* %c) nounwind {
750 ; CHECK: bsel_u_v8i16:
752 %1 = load <8 x i16>* %a
753 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
754 %2 = load <8 x i16>* %b
755 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
756 %3 = load <8 x i16>* %c
757 ; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0($7)
758 %4 = icmp ugt <8 x i16> %1, %2
759 ; CHECK-DAG: clt_u.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
760 %5 = select <8 x i1> %4, <8 x i16> %1, <8 x i16> %3
761 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
762 store <8 x i16> %5, <8 x i16>* %d
763 ; CHECK-DAG: st.h [[R4]], 0($4)
766 ; CHECK: .size bsel_u_v8i16
769 define void @bsel_u_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
770 <4 x i32>* %c) nounwind {
771 ; CHECK: bsel_u_v4i32:
773 %1 = load <4 x i32>* %a
774 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
775 %2 = load <4 x i32>* %b
776 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
777 %3 = load <4 x i32>* %c
778 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
779 %4 = icmp ugt <4 x i32> %1, %2
780 ; CHECK-DAG: clt_u.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
781 %5 = select <4 x i1> %4, <4 x i32> %1, <4 x i32> %3
782 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
783 store <4 x i32> %5, <4 x i32>* %d
784 ; CHECK-DAG: st.w [[R4]], 0($4)
787 ; CHECK: .size bsel_u_v4i32
790 define void @bsel_u_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
791 <2 x i64>* %c) nounwind {
792 ; CHECK: bsel_u_v2i64:
794 %1 = load <2 x i64>* %a
795 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
796 %2 = load <2 x i64>* %b
797 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
798 %3 = load <2 x i64>* %c
799 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
800 %4 = icmp ugt <2 x i64> %1, %2
801 ; CHECK-DAG: clt_u.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
802 %5 = select <2 x i1> %4, <2 x i64> %1, <2 x i64> %3
803 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
804 store <2 x i64> %5, <2 x i64>* %d
805 ; CHECK-DAG: st.d [[R4]], 0($4)
808 ; CHECK: .size bsel_u_v2i64
811 define void @bseli_s_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
812 <16 x i8>* %c) nounwind {
813 ; CHECK: bseli_s_v16i8:
815 %1 = load <16 x i8>* %a
816 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
817 %2 = load <16 x i8>* %b
818 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
819 %3 = icmp sgt <16 x i8> %1, %2
820 ; CHECK-DAG: clt_s.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
821 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
822 ; CHECK-DAG: bseli.b [[R4]], [[R1]], 1
823 store <16 x i8> %4, <16 x i8>* %d
824 ; CHECK-DAG: st.b [[R4]], 0($4)
827 ; CHECK: .size bseli_s_v16i8
830 define void @bseli_s_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
831 <8 x i16>* %c) nounwind {
832 ; CHECK: bseli_s_v8i16:
834 %1 = load <8 x i16>* %a
835 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
836 %2 = load <8 x i16>* %b
837 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
838 %3 = icmp sgt <8 x i16> %1, %2
839 ; CHECK-DAG: clt_s.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
840 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
841 ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
842 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
843 store <8 x i16> %4, <8 x i16>* %d
844 ; CHECK-DAG: st.h [[R4]], 0($4)
847 ; CHECK: .size bseli_s_v8i16
850 define void @bseli_s_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
851 <4 x i32>* %c) nounwind {
852 ; CHECK: bseli_s_v4i32:
854 %1 = load <4 x i32>* %a
855 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
856 %2 = load <4 x i32>* %b
857 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
858 %3 = icmp sgt <4 x i32> %1, %2
859 ; CHECK-DAG: clt_s.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
860 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
861 ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
862 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
863 store <4 x i32> %4, <4 x i32>* %d
864 ; CHECK-DAG: st.w [[R4]], 0($4)
867 ; CHECK: .size bseli_s_v4i32
870 define void @bseli_s_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
871 <2 x i64>* %c) nounwind {
872 ; CHECK: bseli_s_v2i64:
874 %1 = load <2 x i64>* %a
875 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
876 %2 = load <2 x i64>* %b
877 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
878 %3 = icmp sgt <2 x i64> %1, %2
879 ; CHECK-DAG: clt_s.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
880 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
881 ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
882 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
883 store <2 x i64> %4, <2 x i64>* %d
884 ; CHECK-DAG: st.d [[R4]], 0($4)
887 ; CHECK: .size bseli_s_v2i64
890 define void @bseli_u_v16i8(<16 x i8>* %d, <16 x i8>* %a, <16 x i8>* %b,
891 <16 x i8>* %c) nounwind {
892 ; CHECK: bseli_u_v16i8:
894 %1 = load <16 x i8>* %a
895 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
896 %2 = load <16 x i8>* %b
897 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
898 %3 = icmp ugt <16 x i8> %1, %2
899 ; CHECK-DAG: clt_u.b [[R4:\$w[0-9]+]], [[R2]], [[R1]]
900 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
901 ; CHECK-DAG: bseli.b [[R4]], [[R1]], 1
902 store <16 x i8> %4, <16 x i8>* %d
903 ; CHECK-DAG: st.b [[R4]], 0($4)
906 ; CHECK: .size bseli_u_v16i8
909 define void @bseli_u_v8i16(<8 x i16>* %d, <8 x i16>* %a, <8 x i16>* %b,
910 <8 x i16>* %c) nounwind {
911 ; CHECK: bseli_u_v8i16:
913 %1 = load <8 x i16>* %a
914 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
915 %2 = load <8 x i16>* %b
916 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
917 %3 = icmp ugt <8 x i16> %1, %2
918 ; CHECK-DAG: clt_u.h [[R4:\$w[0-9]+]], [[R2]], [[R1]]
919 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
920 ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 1
921 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
922 store <8 x i16> %4, <8 x i16>* %d
923 ; CHECK-DAG: st.h [[R4]], 0($4)
926 ; CHECK: .size bseli_u_v8i16
929 define void @bseli_u_v4i32(<4 x i32>* %d, <4 x i32>* %a, <4 x i32>* %b,
930 <4 x i32>* %c) nounwind {
931 ; CHECK: bseli_u_v4i32:
933 %1 = load <4 x i32>* %a
934 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
935 %2 = load <4 x i32>* %b
936 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
937 %3 = icmp ugt <4 x i32> %1, %2
938 ; CHECK-DAG: clt_u.w [[R4:\$w[0-9]+]], [[R2]], [[R1]]
939 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
940 ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
941 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
942 store <4 x i32> %4, <4 x i32>* %d
943 ; CHECK-DAG: st.w [[R4]], 0($4)
946 ; CHECK: .size bseli_u_v4i32
949 define void @bseli_u_v2i64(<2 x i64>* %d, <2 x i64>* %a, <2 x i64>* %b,
950 <2 x i64>* %c) nounwind {
951 ; CHECK: bseli_u_v2i64:
953 %1 = load <2 x i64>* %a
954 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
955 %2 = load <2 x i64>* %b
956 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
957 %3 = icmp ugt <2 x i64> %1, %2
958 ; CHECK-DAG: clt_u.d [[R4:\$w[0-9]+]], [[R2]], [[R1]]
959 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
960 ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
961 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]]
962 store <2 x i64> %4, <2 x i64>* %d
963 ; CHECK-DAG: st.d [[R4]], 0($4)
966 ; CHECK: .size bseli_u_v2i64
969 define void @max_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
970 ; CHECK: max_s_v16i8:
972 %1 = load <16 x i8>* %a
973 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
974 %2 = load <16 x i8>* %b
975 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
976 %3 = icmp sgt <16 x i8> %1, %2
977 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
978 ; CHECK-DAG: max_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
979 store <16 x i8> %4, <16 x i8>* %c
980 ; CHECK-DAG: st.b [[R3]], 0($4)
983 ; CHECK: .size max_s_v16i8
986 define void @max_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
987 ; CHECK: max_s_v8i16:
989 %1 = load <8 x i16>* %a
990 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
991 %2 = load <8 x i16>* %b
992 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
993 %3 = icmp sgt <8 x i16> %1, %2
994 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
995 ; CHECK-DAG: max_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
996 store <8 x i16> %4, <8 x i16>* %c
997 ; CHECK-DAG: st.h [[R3]], 0($4)
1000 ; CHECK: .size max_s_v8i16
1003 define void @max_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1004 ; CHECK: max_s_v4i32:
1006 %1 = load <4 x i32>* %a
1007 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1008 %2 = load <4 x i32>* %b
1009 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1010 %3 = icmp sgt <4 x i32> %1, %2
1011 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1012 ; CHECK-DAG: max_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1013 store <4 x i32> %4, <4 x i32>* %c
1014 ; CHECK-DAG: st.w [[R3]], 0($4)
1017 ; CHECK: .size max_s_v4i32
1020 define void @max_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1021 ; CHECK: max_s_v2i64:
1023 %1 = load <2 x i64>* %a
1024 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1025 %2 = load <2 x i64>* %b
1026 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1027 %3 = icmp sgt <2 x i64> %1, %2
1028 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1029 ; CHECK-DAG: max_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1030 store <2 x i64> %4, <2 x i64>* %c
1031 ; CHECK-DAG: st.d [[R3]], 0($4)
1034 ; CHECK: .size max_s_v2i64
1037 define void @max_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1038 ; CHECK: max_u_v16i8:
1040 %1 = load <16 x i8>* %a
1041 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1042 %2 = load <16 x i8>* %b
1043 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1044 %3 = icmp ugt <16 x i8> %1, %2
1045 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1046 ; CHECK-DAG: max_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1047 store <16 x i8> %4, <16 x i8>* %c
1048 ; CHECK-DAG: st.b [[R3]], 0($4)
1051 ; CHECK: .size max_u_v16i8
1054 define void @max_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1055 ; CHECK: max_u_v8i16:
1057 %1 = load <8 x i16>* %a
1058 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1059 %2 = load <8 x i16>* %b
1060 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1061 %3 = icmp ugt <8 x i16> %1, %2
1062 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1063 ; CHECK-DAG: max_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1064 store <8 x i16> %4, <8 x i16>* %c
1065 ; CHECK-DAG: st.h [[R3]], 0($4)
1068 ; CHECK: .size max_u_v8i16
1071 define void @max_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1072 ; CHECK: max_u_v4i32:
1074 %1 = load <4 x i32>* %a
1075 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1076 %2 = load <4 x i32>* %b
1077 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1078 %3 = icmp ugt <4 x i32> %1, %2
1079 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1080 ; CHECK-DAG: max_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1081 store <4 x i32> %4, <4 x i32>* %c
1082 ; CHECK-DAG: st.w [[R3]], 0($4)
1085 ; CHECK: .size max_u_v4i32
1088 define void @max_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1089 ; CHECK: max_u_v2i64:
1091 %1 = load <2 x i64>* %a
1092 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1093 %2 = load <2 x i64>* %b
1094 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1095 %3 = icmp ugt <2 x i64> %1, %2
1096 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1097 ; CHECK-DAG: max_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1098 store <2 x i64> %4, <2 x i64>* %c
1099 ; CHECK-DAG: st.d [[R3]], 0($4)
1102 ; CHECK: .size max_u_v2i64
1105 define void @max_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1106 ; CHECK: max_s_eq_v16i8:
1108 %1 = load <16 x i8>* %a
1109 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1110 %2 = load <16 x i8>* %b
1111 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1112 %3 = icmp sge <16 x i8> %1, %2
1113 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1114 ; CHECK-DAG: max_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1115 store <16 x i8> %4, <16 x i8>* %c
1116 ; CHECK-DAG: st.b [[R3]], 0($4)
1119 ; CHECK: .size max_s_eq_v16i8
1122 define void @max_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1123 ; CHECK: max_s_eq_v8i16:
1125 %1 = load <8 x i16>* %a
1126 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1127 %2 = load <8 x i16>* %b
1128 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1129 %3 = icmp sge <8 x i16> %1, %2
1130 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1131 ; CHECK-DAG: max_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1132 store <8 x i16> %4, <8 x i16>* %c
1133 ; CHECK-DAG: st.h [[R3]], 0($4)
1136 ; CHECK: .size max_s_eq_v8i16
1139 define void @max_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1140 ; CHECK: max_s_eq_v4i32:
1142 %1 = load <4 x i32>* %a
1143 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1144 %2 = load <4 x i32>* %b
1145 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1146 %3 = icmp sge <4 x i32> %1, %2
1147 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1148 ; CHECK-DAG: max_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1149 store <4 x i32> %4, <4 x i32>* %c
1150 ; CHECK-DAG: st.w [[R3]], 0($4)
1153 ; CHECK: .size max_s_eq_v4i32
1156 define void @max_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1157 ; CHECK: max_s_eq_v2i64:
1159 %1 = load <2 x i64>* %a
1160 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1161 %2 = load <2 x i64>* %b
1162 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1163 %3 = icmp sge <2 x i64> %1, %2
1164 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1165 ; CHECK-DAG: max_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1166 store <2 x i64> %4, <2 x i64>* %c
1167 ; CHECK-DAG: st.d [[R3]], 0($4)
1170 ; CHECK: .size max_s_eq_v2i64
1173 define void @max_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1174 ; CHECK: max_u_eq_v16i8:
1176 %1 = load <16 x i8>* %a
1177 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1178 %2 = load <16 x i8>* %b
1179 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1180 %3 = icmp uge <16 x i8> %1, %2
1181 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1182 ; CHECK-DAG: max_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1183 store <16 x i8> %4, <16 x i8>* %c
1184 ; CHECK-DAG: st.b [[R3]], 0($4)
1187 ; CHECK: .size max_u_eq_v16i8
1190 define void @max_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1191 ; CHECK: max_u_eq_v8i16:
1193 %1 = load <8 x i16>* %a
1194 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1195 %2 = load <8 x i16>* %b
1196 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1197 %3 = icmp uge <8 x i16> %1, %2
1198 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1199 ; CHECK-DAG: max_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1200 store <8 x i16> %4, <8 x i16>* %c
1201 ; CHECK-DAG: st.h [[R3]], 0($4)
1204 ; CHECK: .size max_u_eq_v8i16
1207 define void @max_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1208 ; CHECK: max_u_eq_v4i32:
1210 %1 = load <4 x i32>* %a
1211 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1212 %2 = load <4 x i32>* %b
1213 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1214 %3 = icmp uge <4 x i32> %1, %2
1215 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1216 ; CHECK-DAG: max_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1217 store <4 x i32> %4, <4 x i32>* %c
1218 ; CHECK-DAG: st.w [[R3]], 0($4)
1221 ; CHECK: .size max_u_eq_v4i32
1224 define void @max_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1225 ; CHECK: max_u_eq_v2i64:
1227 %1 = load <2 x i64>* %a
1228 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1229 %2 = load <2 x i64>* %b
1230 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1231 %3 = icmp uge <2 x i64> %1, %2
1232 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1233 ; CHECK-DAG: max_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1234 store <2 x i64> %4, <2 x i64>* %c
1235 ; CHECK-DAG: st.d [[R3]], 0($4)
1238 ; CHECK: .size max_u_eq_v2i64
1241 define void @maxi_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1242 ; CHECK: maxi_s_v16i8:
1244 %1 = load <16 x i8>* %a
1245 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1246 %2 = icmp sgt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1247 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1248 ; CHECK-DAG: maxi_s.b [[R3:\$w[0-9]+]], [[R1]], 1
1249 store <16 x i8> %3, <16 x i8>* %c
1250 ; CHECK-DAG: st.b [[R3]], 0($4)
1253 ; CHECK: .size maxi_s_v16i8
1256 define void @maxi_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1257 ; CHECK: maxi_s_v8i16:
1259 %1 = load <8 x i16>* %a
1260 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1261 %2 = icmp sgt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1262 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1263 ; CHECK-DAG: maxi_s.h [[R3:\$w[0-9]+]], [[R1]], 1
1264 store <8 x i16> %3, <8 x i16>* %c
1265 ; CHECK-DAG: st.h [[R3]], 0($4)
1268 ; CHECK: .size maxi_s_v8i16
1271 define void @maxi_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1272 ; CHECK: maxi_s_v4i32:
1274 %1 = load <4 x i32>* %a
1275 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1276 %2 = icmp sgt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1277 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1278 ; CHECK-DAG: maxi_s.w [[R3:\$w[0-9]+]], [[R1]], 1
1279 store <4 x i32> %3, <4 x i32>* %c
1280 ; CHECK-DAG: st.w [[R3]], 0($4)
1283 ; CHECK: .size maxi_s_v4i32
1286 define void @maxi_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1287 ; CHECK: maxi_s_v2i64:
1289 %1 = load <2 x i64>* %a
1290 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1291 %2 = icmp sgt <2 x i64> %1, <i64 1, i64 1>
1292 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1293 ; CHECK-DAG: maxi_s.d [[R3:\$w[0-9]+]], [[R1]], 1
1294 store <2 x i64> %3, <2 x i64>* %c
1295 ; CHECK-DAG: st.d [[R3]], 0($4)
1298 ; CHECK: .size maxi_s_v2i64
1301 define void @maxi_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1302 ; CHECK: maxi_u_v16i8:
1304 %1 = load <16 x i8>* %a
1305 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1306 %2 = icmp ugt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1307 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1308 ; CHECK-DAG: maxi_u.b [[R3:\$w[0-9]+]], [[R1]], 1
1309 store <16 x i8> %3, <16 x i8>* %c
1310 ; CHECK-DAG: st.b [[R3]], 0($4)
1313 ; CHECK: .size maxi_u_v16i8
1316 define void @maxi_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1317 ; CHECK: maxi_u_v8i16:
1319 %1 = load <8 x i16>* %a
1320 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1321 %2 = icmp ugt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1322 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1323 ; CHECK-DAG: maxi_u.h [[R3:\$w[0-9]+]], [[R1]], 1
1324 store <8 x i16> %3, <8 x i16>* %c
1325 ; CHECK-DAG: st.h [[R3]], 0($4)
1328 ; CHECK: .size maxi_u_v8i16
1331 define void @maxi_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1332 ; CHECK: maxi_u_v4i32:
1334 %1 = load <4 x i32>* %a
1335 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1336 %2 = icmp ugt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1337 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1338 ; CHECK-DAG: maxi_u.w [[R3:\$w[0-9]+]], [[R1]], 1
1339 store <4 x i32> %3, <4 x i32>* %c
1340 ; CHECK-DAG: st.w [[R3]], 0($4)
1343 ; CHECK: .size maxi_u_v4i32
1346 define void @maxi_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1347 ; CHECK: maxi_u_v2i64:
1349 %1 = load <2 x i64>* %a
1350 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1351 %2 = icmp ugt <2 x i64> %1, <i64 1, i64 1>
1352 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1353 ; CHECK-DAG: maxi_u.d [[R3:\$w[0-9]+]], [[R1]], 1
1354 store <2 x i64> %3, <2 x i64>* %c
1355 ; CHECK-DAG: st.d [[R3]], 0($4)
1358 ; CHECK: .size maxi_u_v2i64
1361 define void @maxi_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1362 ; CHECK: maxi_s_eq_v16i8:
1364 %1 = load <16 x i8>* %a
1365 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1366 %2 = icmp sge <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1367 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1368 ; CHECK-DAG: maxi_s.b [[R3:\$w[0-9]+]], [[R1]], 1
1369 store <16 x i8> %3, <16 x i8>* %c
1370 ; CHECK-DAG: st.b [[R3]], 0($4)
1373 ; CHECK: .size maxi_s_eq_v16i8
1376 define void @maxi_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1377 ; CHECK: maxi_s_eq_v8i16:
1379 %1 = load <8 x i16>* %a
1380 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1381 %2 = icmp sge <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1382 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1383 ; CHECK-DAG: maxi_s.h [[R3:\$w[0-9]+]], [[R1]], 1
1384 store <8 x i16> %3, <8 x i16>* %c
1385 ; CHECK-DAG: st.h [[R3]], 0($4)
1388 ; CHECK: .size maxi_s_eq_v8i16
1391 define void @maxi_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1392 ; CHECK: maxi_s_eq_v4i32:
1394 %1 = load <4 x i32>* %a
1395 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1396 %2 = icmp sge <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1397 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1398 ; CHECK-DAG: maxi_s.w [[R3:\$w[0-9]+]], [[R1]], 1
1399 store <4 x i32> %3, <4 x i32>* %c
1400 ; CHECK-DAG: st.w [[R3]], 0($4)
1403 ; CHECK: .size maxi_s_eq_v4i32
1406 define void @maxi_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1407 ; CHECK: maxi_s_eq_v2i64:
1409 %1 = load <2 x i64>* %a
1410 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1411 %2 = icmp sge <2 x i64> %1, <i64 1, i64 1>
1412 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1413 ; CHECK-DAG: maxi_s.d [[R3:\$w[0-9]+]], [[R1]], 1
1414 store <2 x i64> %3, <2 x i64>* %c
1415 ; CHECK-DAG: st.d [[R3]], 0($4)
1418 ; CHECK: .size maxi_s_eq_v2i64
1421 define void @maxi_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1422 ; CHECK: maxi_u_eq_v16i8:
1424 %1 = load <16 x i8>* %a
1425 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1426 %2 = icmp uge <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1427 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1428 ; CHECK-DAG: maxi_u.b [[R3:\$w[0-9]+]], [[R1]], 1
1429 store <16 x i8> %3, <16 x i8>* %c
1430 ; CHECK-DAG: st.b [[R3]], 0($4)
1433 ; CHECK: .size maxi_u_eq_v16i8
1436 define void @maxi_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1437 ; CHECK: maxi_u_eq_v8i16:
1439 %1 = load <8 x i16>* %a
1440 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1441 %2 = icmp uge <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1442 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1443 ; CHECK-DAG: maxi_u.h [[R3:\$w[0-9]+]], [[R1]], 1
1444 store <8 x i16> %3, <8 x i16>* %c
1445 ; CHECK-DAG: st.h [[R3]], 0($4)
1448 ; CHECK: .size maxi_u_eq_v8i16
1451 define void @maxi_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1452 ; CHECK: maxi_u_eq_v4i32:
1454 %1 = load <4 x i32>* %a
1455 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1456 %2 = icmp uge <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1457 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1458 ; CHECK-DAG: maxi_u.w [[R3:\$w[0-9]+]], [[R1]], 1
1459 store <4 x i32> %3, <4 x i32>* %c
1460 ; CHECK-DAG: st.w [[R3]], 0($4)
1463 ; CHECK: .size maxi_u_eq_v4i32
1466 define void @maxi_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1467 ; CHECK: maxi_u_eq_v2i64:
1469 %1 = load <2 x i64>* %a
1470 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1471 %2 = icmp uge <2 x i64> %1, <i64 1, i64 1>
1472 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1473 ; CHECK-DAG: maxi_u.d [[R3:\$w[0-9]+]], [[R1]], 1
1474 store <2 x i64> %3, <2 x i64>* %c
1475 ; CHECK-DAG: st.d [[R3]], 0($4)
1478 ; CHECK: .size maxi_u_eq_v2i64
1481 define void @min_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1482 ; CHECK: min_s_v16i8:
1484 %1 = load <16 x i8>* %a
1485 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1486 %2 = load <16 x i8>* %b
1487 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1488 %3 = icmp sle <16 x i8> %1, %2
1489 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1490 ; CHECK-DAG: min_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1491 store <16 x i8> %4, <16 x i8>* %c
1492 ; CHECK-DAG: st.b [[R3]], 0($4)
1495 ; CHECK: .size min_s_v16i8
1498 define void @min_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1499 ; CHECK: min_s_v8i16:
1501 %1 = load <8 x i16>* %a
1502 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1503 %2 = load <8 x i16>* %b
1504 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1505 %3 = icmp slt <8 x i16> %1, %2
1506 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1507 ; CHECK-DAG: min_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1508 store <8 x i16> %4, <8 x i16>* %c
1509 ; CHECK-DAG: st.h [[R3]], 0($4)
1512 ; CHECK: .size min_s_v8i16
1515 define void @min_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1516 ; CHECK: min_s_v4i32:
1518 %1 = load <4 x i32>* %a
1519 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1520 %2 = load <4 x i32>* %b
1521 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1522 %3 = icmp slt <4 x i32> %1, %2
1523 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1524 ; CHECK-DAG: min_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1525 store <4 x i32> %4, <4 x i32>* %c
1526 ; CHECK-DAG: st.w [[R3]], 0($4)
1529 ; CHECK: .size min_s_v4i32
1532 define void @min_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1533 ; CHECK: min_s_v2i64:
1535 %1 = load <2 x i64>* %a
1536 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1537 %2 = load <2 x i64>* %b
1538 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1539 %3 = icmp slt <2 x i64> %1, %2
1540 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1541 ; CHECK-DAG: min_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1542 store <2 x i64> %4, <2 x i64>* %c
1543 ; CHECK-DAG: st.d [[R3]], 0($4)
1546 ; CHECK: .size min_s_v2i64
1549 define void @min_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1550 ; CHECK: min_u_v16i8:
1552 %1 = load <16 x i8>* %a
1553 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1554 %2 = load <16 x i8>* %b
1555 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1556 %3 = icmp ult <16 x i8> %1, %2
1557 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1558 ; CHECK-DAG: min_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1559 store <16 x i8> %4, <16 x i8>* %c
1560 ; CHECK-DAG: st.b [[R3]], 0($4)
1563 ; CHECK: .size min_u_v16i8
1566 define void @min_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1567 ; CHECK: min_u_v8i16:
1569 %1 = load <8 x i16>* %a
1570 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1571 %2 = load <8 x i16>* %b
1572 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1573 %3 = icmp ult <8 x i16> %1, %2
1574 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1575 ; CHECK-DAG: min_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1576 store <8 x i16> %4, <8 x i16>* %c
1577 ; CHECK-DAG: st.h [[R3]], 0($4)
1580 ; CHECK: .size min_u_v8i16
1583 define void @min_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1584 ; CHECK: min_u_v4i32:
1586 %1 = load <4 x i32>* %a
1587 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1588 %2 = load <4 x i32>* %b
1589 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1590 %3 = icmp ult <4 x i32> %1, %2
1591 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1592 ; CHECK-DAG: min_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1593 store <4 x i32> %4, <4 x i32>* %c
1594 ; CHECK-DAG: st.w [[R3]], 0($4)
1597 ; CHECK: .size min_u_v4i32
1600 define void @min_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1601 ; CHECK: min_u_v2i64:
1603 %1 = load <2 x i64>* %a
1604 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1605 %2 = load <2 x i64>* %b
1606 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1607 %3 = icmp ult <2 x i64> %1, %2
1608 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1609 ; CHECK-DAG: min_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1610 store <2 x i64> %4, <2 x i64>* %c
1611 ; CHECK-DAG: st.d [[R3]], 0($4)
1614 ; CHECK: .size min_u_v2i64
1617 define void @min_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1618 ; CHECK: min_s_eq_v16i8:
1620 %1 = load <16 x i8>* %a
1621 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1622 %2 = load <16 x i8>* %b
1623 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1624 %3 = icmp sle <16 x i8> %1, %2
1625 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1626 ; CHECK-DAG: min_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1627 store <16 x i8> %4, <16 x i8>* %c
1628 ; CHECK-DAG: st.b [[R3]], 0($4)
1631 ; CHECK: .size min_s_eq_v16i8
1634 define void @min_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1635 ; CHECK: min_s_eq_v8i16:
1637 %1 = load <8 x i16>* %a
1638 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1639 %2 = load <8 x i16>* %b
1640 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1641 %3 = icmp sle <8 x i16> %1, %2
1642 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1643 ; CHECK-DAG: min_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1644 store <8 x i16> %4, <8 x i16>* %c
1645 ; CHECK-DAG: st.h [[R3]], 0($4)
1648 ; CHECK: .size min_s_eq_v8i16
1651 define void @min_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1652 ; CHECK: min_s_eq_v4i32:
1654 %1 = load <4 x i32>* %a
1655 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1656 %2 = load <4 x i32>* %b
1657 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1658 %3 = icmp sle <4 x i32> %1, %2
1659 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1660 ; CHECK-DAG: min_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1661 store <4 x i32> %4, <4 x i32>* %c
1662 ; CHECK-DAG: st.w [[R3]], 0($4)
1665 ; CHECK: .size min_s_eq_v4i32
1668 define void @min_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1669 ; CHECK: min_s_eq_v2i64:
1671 %1 = load <2 x i64>* %a
1672 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1673 %2 = load <2 x i64>* %b
1674 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1675 %3 = icmp sle <2 x i64> %1, %2
1676 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1677 ; CHECK-DAG: min_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1678 store <2 x i64> %4, <2 x i64>* %c
1679 ; CHECK-DAG: st.d [[R3]], 0($4)
1682 ; CHECK: .size min_s_eq_v2i64
1685 define void @min_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
1686 ; CHECK: min_u_eq_v16i8:
1688 %1 = load <16 x i8>* %a
1689 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1690 %2 = load <16 x i8>* %b
1691 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
1692 %3 = icmp ule <16 x i8> %1, %2
1693 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1694 ; CHECK-DAG: min_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1695 store <16 x i8> %4, <16 x i8>* %c
1696 ; CHECK-DAG: st.b [[R3]], 0($4)
1699 ; CHECK: .size min_u_eq_v16i8
1702 define void @min_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
1703 ; CHECK: min_u_eq_v8i16:
1705 %1 = load <8 x i16>* %a
1706 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1707 %2 = load <8 x i16>* %b
1708 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
1709 %3 = icmp ule <8 x i16> %1, %2
1710 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1711 ; CHECK-DAG: min_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1712 store <8 x i16> %4, <8 x i16>* %c
1713 ; CHECK-DAG: st.h [[R3]], 0($4)
1716 ; CHECK: .size min_u_eq_v8i16
1719 define void @min_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
1720 ; CHECK: min_u_eq_v4i32:
1722 %1 = load <4 x i32>* %a
1723 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1724 %2 = load <4 x i32>* %b
1725 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
1726 %3 = icmp ule <4 x i32> %1, %2
1727 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1728 ; CHECK-DAG: min_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1729 store <4 x i32> %4, <4 x i32>* %c
1730 ; CHECK-DAG: st.w [[R3]], 0($4)
1733 ; CHECK: .size min_u_eq_v4i32
1736 define void @min_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1737 ; CHECK: min_u_eq_v2i64:
1739 %1 = load <2 x i64>* %a
1740 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1741 %2 = load <2 x i64>* %b
1742 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
1743 %3 = icmp ule <2 x i64> %1, %2
1744 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1745 ; CHECK-DAG: min_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1746 store <2 x i64> %4, <2 x i64>* %c
1747 ; CHECK-DAG: st.d [[R3]], 0($4)
1750 ; CHECK: .size min_u_eq_v2i64
1753 define void @mini_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1754 ; CHECK: mini_s_v16i8:
1756 %1 = load <16 x i8>* %a
1757 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1758 %2 = icmp slt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1759 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1760 ; CHECK-DAG: mini_s.b [[R3:\$w[0-9]+]], [[R1]], 1
1761 store <16 x i8> %3, <16 x i8>* %c
1762 ; CHECK-DAG: st.b [[R3]], 0($4)
1765 ; CHECK: .size mini_s_v16i8
1768 define void @mini_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1769 ; CHECK: mini_s_v8i16:
1771 %1 = load <8 x i16>* %a
1772 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1773 %2 = icmp slt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1774 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1775 ; CHECK-DAG: mini_s.h [[R3:\$w[0-9]+]], [[R1]], 1
1776 store <8 x i16> %3, <8 x i16>* %c
1777 ; CHECK-DAG: st.h [[R3]], 0($4)
1780 ; CHECK: .size mini_s_v8i16
1783 define void @mini_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1784 ; CHECK: mini_s_v4i32:
1786 %1 = load <4 x i32>* %a
1787 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1788 %2 = icmp slt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1789 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1790 ; CHECK-DAG: mini_s.w [[R3:\$w[0-9]+]], [[R1]], 1
1791 store <4 x i32> %3, <4 x i32>* %c
1792 ; CHECK-DAG: st.w [[R3]], 0($4)
1795 ; CHECK: .size mini_s_v4i32
1798 define void @mini_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1799 ; CHECK: mini_s_v2i64:
1801 %1 = load <2 x i64>* %a
1802 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1803 %2 = icmp slt <2 x i64> %1, <i64 1, i64 1>
1804 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1805 ; CHECK-DAG: mini_s.d [[R3:\$w[0-9]+]], [[R1]], 1
1806 store <2 x i64> %3, <2 x i64>* %c
1807 ; CHECK-DAG: st.d [[R3]], 0($4)
1810 ; CHECK: .size mini_s_v2i64
1813 define void @mini_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1814 ; CHECK: mini_u_v16i8:
1816 %1 = load <16 x i8>* %a
1817 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1818 %2 = icmp ult <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1819 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1820 ; CHECK-DAG: mini_u.b [[R3:\$w[0-9]+]], [[R1]], 1
1821 store <16 x i8> %3, <16 x i8>* %c
1822 ; CHECK-DAG: st.b [[R3]], 0($4)
1825 ; CHECK: .size mini_u_v16i8
1828 define void @mini_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1829 ; CHECK: mini_u_v8i16:
1831 %1 = load <8 x i16>* %a
1832 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1833 %2 = icmp ult <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1834 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1835 ; CHECK-DAG: mini_u.h [[R3:\$w[0-9]+]], [[R1]], 1
1836 store <8 x i16> %3, <8 x i16>* %c
1837 ; CHECK-DAG: st.h [[R3]], 0($4)
1840 ; CHECK: .size mini_u_v8i16
1843 define void @mini_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1844 ; CHECK: mini_u_v4i32:
1846 %1 = load <4 x i32>* %a
1847 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1848 %2 = icmp ult <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1849 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1850 ; CHECK-DAG: mini_u.w [[R3:\$w[0-9]+]], [[R1]], 1
1851 store <4 x i32> %3, <4 x i32>* %c
1852 ; CHECK-DAG: st.w [[R3]], 0($4)
1855 ; CHECK: .size mini_u_v4i32
1858 define void @mini_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1859 ; CHECK: mini_u_v2i64:
1861 %1 = load <2 x i64>* %a
1862 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1863 %2 = icmp ult <2 x i64> %1, <i64 1, i64 1>
1864 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1865 ; CHECK-DAG: mini_u.d [[R3:\$w[0-9]+]], [[R1]], 1
1866 store <2 x i64> %3, <2 x i64>* %c
1867 ; CHECK-DAG: st.d [[R3]], 0($4)
1870 ; CHECK: .size mini_u_v2i64
1873 define void @mini_s_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1874 ; CHECK: mini_s_eq_v16i8:
1876 %1 = load <16 x i8>* %a
1877 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1878 %2 = icmp sle <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1879 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1880 ; CHECK-DAG: mini_s.b [[R3:\$w[0-9]+]], [[R1]], 1
1881 store <16 x i8> %3, <16 x i8>* %c
1882 ; CHECK-DAG: st.b [[R3]], 0($4)
1885 ; CHECK: .size mini_s_eq_v16i8
1888 define void @mini_s_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1889 ; CHECK: mini_s_eq_v8i16:
1891 %1 = load <8 x i16>* %a
1892 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1893 %2 = icmp sle <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1894 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1895 ; CHECK-DAG: mini_s.h [[R3:\$w[0-9]+]], [[R1]], 1
1896 store <8 x i16> %3, <8 x i16>* %c
1897 ; CHECK-DAG: st.h [[R3]], 0($4)
1900 ; CHECK: .size mini_s_eq_v8i16
1903 define void @mini_s_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1904 ; CHECK: mini_s_eq_v4i32:
1906 %1 = load <4 x i32>* %a
1907 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1908 %2 = icmp sle <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1909 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1910 ; CHECK-DAG: mini_s.w [[R3:\$w[0-9]+]], [[R1]], 1
1911 store <4 x i32> %3, <4 x i32>* %c
1912 ; CHECK-DAG: st.w [[R3]], 0($4)
1915 ; CHECK: .size mini_s_eq_v4i32
1918 define void @mini_s_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1919 ; CHECK: mini_s_eq_v2i64:
1921 %1 = load <2 x i64>* %a
1922 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1923 %2 = icmp sle <2 x i64> %1, <i64 1, i64 1>
1924 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1925 ; CHECK-DAG: mini_s.d [[R3:\$w[0-9]+]], [[R1]], 1
1926 store <2 x i64> %3, <2 x i64>* %c
1927 ; CHECK-DAG: st.d [[R3]], 0($4)
1930 ; CHECK: .size mini_s_eq_v2i64
1933 define void @mini_u_eq_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
1934 ; CHECK: mini_u_eq_v16i8:
1936 %1 = load <16 x i8>* %a
1937 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
1938 %2 = icmp ule <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1939 %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1940 ; CHECK-DAG: mini_u.b [[R3:\$w[0-9]+]], [[R1]], 1
1941 store <16 x i8> %3, <16 x i8>* %c
1942 ; CHECK-DAG: st.b [[R3]], 0($4)
1945 ; CHECK: .size mini_u_eq_v16i8
1948 define void @mini_u_eq_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
1949 ; CHECK: mini_u_eq_v8i16:
1951 %1 = load <8 x i16>* %a
1952 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
1953 %2 = icmp ule <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1954 %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1955 ; CHECK-DAG: mini_u.h [[R3:\$w[0-9]+]], [[R1]], 1
1956 store <8 x i16> %3, <8 x i16>* %c
1957 ; CHECK-DAG: st.h [[R3]], 0($4)
1960 ; CHECK: .size mini_u_eq_v8i16
1963 define void @mini_u_eq_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
1964 ; CHECK: mini_u_eq_v4i32:
1966 %1 = load <4 x i32>* %a
1967 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
1968 %2 = icmp ule <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
1969 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1970 ; CHECK-DAG: mini_u.w [[R3:\$w[0-9]+]], [[R1]], 1
1971 store <4 x i32> %3, <4 x i32>* %c
1972 ; CHECK-DAG: st.w [[R3]], 0($4)
1975 ; CHECK: .size mini_u_eq_v4i32
1978 define void @mini_u_eq_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
1979 ; CHECK: mini_u_eq_v2i64:
1981 %1 = load <2 x i64>* %a
1982 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
1983 %2 = icmp ule <2 x i64> %1, <i64 1, i64 1>
1984 %3 = select <2 x i1> %2, <2 x i64> %1, <2 x i64> <i64 1, i64 1>
1985 ; CHECK-DAG: mini_u.d [[R3:\$w[0-9]+]], [[R1]], 1
1986 store <2 x i64> %3, <2 x i64>* %c
1987 ; CHECK-DAG: st.d [[R3]], 0($4)
1990 ; CHECK: .size mini_u_eq_v2i64