1 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
3 define void @ceq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
6 %1 = load <16 x i8>* %a
7 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
8 %2 = load <16 x i8>* %b
9 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
10 %3 = icmp eq <16 x i8> %1, %2
11 %4 = sext <16 x i1> %3 to <16 x i8>
12 ; CHECK-DAG: ceq.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
13 store <16 x i8> %4, <16 x i8>* %c
14 ; CHECK-DAG: st.b [[R3]], 0($4)
17 ; CHECK: .size ceq_v16i8
20 define void @ceq_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
23 %1 = load <8 x i16>* %a
24 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
25 %2 = load <8 x i16>* %b
26 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
27 %3 = icmp eq <8 x i16> %1, %2
28 %4 = sext <8 x i1> %3 to <8 x i16>
29 ; CHECK-DAG: ceq.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
30 store <8 x i16> %4, <8 x i16>* %c
31 ; CHECK-DAG: st.h [[R3]], 0($4)
34 ; CHECK: .size ceq_v8i16
37 define void @ceq_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
40 %1 = load <4 x i32>* %a
41 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
42 %2 = load <4 x i32>* %b
43 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
44 %3 = icmp eq <4 x i32> %1, %2
45 %4 = sext <4 x i1> %3 to <4 x i32>
46 ; CHECK-DAG: ceq.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
47 store <4 x i32> %4, <4 x i32>* %c
48 ; CHECK-DAG: st.w [[R3]], 0($4)
51 ; CHECK: .size ceq_v4i32
54 define void @ceq_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
57 %1 = load <2 x i64>* %a
58 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
59 %2 = load <2 x i64>* %b
60 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
61 %3 = icmp eq <2 x i64> %1, %2
62 %4 = sext <2 x i1> %3 to <2 x i64>
63 ; CHECK-DAG: ceq.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
64 store <2 x i64> %4, <2 x i64>* %c
65 ; CHECK-DAG: st.d [[R3]], 0($4)
68 ; CHECK: .size ceq_v2i64
71 define void @cle_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
74 %1 = load <16 x i8>* %a
75 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
76 %2 = load <16 x i8>* %b
77 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
78 %3 = icmp sle <16 x i8> %1, %2
79 %4 = sext <16 x i1> %3 to <16 x i8>
80 ; CHECK-DAG: cle_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
81 store <16 x i8> %4, <16 x i8>* %c
82 ; CHECK-DAG: st.b [[R3]], 0($4)
85 ; CHECK: .size cle_s_v16i8
88 define void @cle_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
91 %1 = load <8 x i16>* %a
92 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
93 %2 = load <8 x i16>* %b
94 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
95 %3 = icmp sle <8 x i16> %1, %2
96 %4 = sext <8 x i1> %3 to <8 x i16>
97 ; CHECK-DAG: cle_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
98 store <8 x i16> %4, <8 x i16>* %c
99 ; CHECK-DAG: st.h [[R3]], 0($4)
102 ; CHECK: .size cle_s_v8i16
105 define void @cle_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
106 ; CHECK: cle_s_v4i32:
108 %1 = load <4 x i32>* %a
109 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
110 %2 = load <4 x i32>* %b
111 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
112 %3 = icmp sle <4 x i32> %1, %2
113 %4 = sext <4 x i1> %3 to <4 x i32>
114 ; CHECK-DAG: cle_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
115 store <4 x i32> %4, <4 x i32>* %c
116 ; CHECK-DAG: st.w [[R3]], 0($4)
119 ; CHECK: .size cle_s_v4i32
122 define void @cle_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
123 ; CHECK: cle_s_v2i64:
125 %1 = load <2 x i64>* %a
126 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
127 %2 = load <2 x i64>* %b
128 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
129 %3 = icmp sle <2 x i64> %1, %2
130 %4 = sext <2 x i1> %3 to <2 x i64>
131 ; CHECK-DAG: cle_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
132 store <2 x i64> %4, <2 x i64>* %c
133 ; CHECK-DAG: st.d [[R3]], 0($4)
136 ; CHECK: .size cle_s_v2i64
139 define void @cle_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
140 ; CHECK: cle_u_v16i8:
142 %1 = load <16 x i8>* %a
143 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
144 %2 = load <16 x i8>* %b
145 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
146 %3 = icmp ule <16 x i8> %1, %2
147 %4 = sext <16 x i1> %3 to <16 x i8>
148 ; CHECK-DAG: cle_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
149 store <16 x i8> %4, <16 x i8>* %c
150 ; CHECK-DAG: st.b [[R3]], 0($4)
153 ; CHECK: .size cle_u_v16i8
156 define void @cle_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
157 ; CHECK: cle_u_v8i16:
159 %1 = load <8 x i16>* %a
160 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
161 %2 = load <8 x i16>* %b
162 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
163 %3 = icmp ule <8 x i16> %1, %2
164 %4 = sext <8 x i1> %3 to <8 x i16>
165 ; CHECK-DAG: cle_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
166 store <8 x i16> %4, <8 x i16>* %c
167 ; CHECK-DAG: st.h [[R3]], 0($4)
170 ; CHECK: .size cle_u_v8i16
173 define void @cle_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
174 ; CHECK: cle_u_v4i32:
176 %1 = load <4 x i32>* %a
177 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
178 %2 = load <4 x i32>* %b
179 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
180 %3 = icmp ule <4 x i32> %1, %2
181 %4 = sext <4 x i1> %3 to <4 x i32>
182 ; CHECK-DAG: cle_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
183 store <4 x i32> %4, <4 x i32>* %c
184 ; CHECK-DAG: st.w [[R3]], 0($4)
187 ; CHECK: .size cle_u_v4i32
190 define void @cle_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
191 ; CHECK: cle_u_v2i64:
193 %1 = load <2 x i64>* %a
194 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
195 %2 = load <2 x i64>* %b
196 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
197 %3 = icmp ule <2 x i64> %1, %2
198 %4 = sext <2 x i1> %3 to <2 x i64>
199 ; CHECK-DAG: cle_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
200 store <2 x i64> %4, <2 x i64>* %c
201 ; CHECK-DAG: st.d [[R3]], 0($4)
204 ; CHECK: .size cle_u_v2i64
207 define void @clt_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
208 ; CHECK: clt_s_v16i8:
210 %1 = load <16 x i8>* %a
211 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
212 %2 = load <16 x i8>* %b
213 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
214 %3 = icmp slt <16 x i8> %1, %2
215 %4 = sext <16 x i1> %3 to <16 x i8>
216 ; CHECK-DAG: clt_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
217 store <16 x i8> %4, <16 x i8>* %c
218 ; CHECK-DAG: st.b [[R3]], 0($4)
221 ; CHECK: .size clt_s_v16i8
224 define void @clt_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
225 ; CHECK: clt_s_v8i16:
227 %1 = load <8 x i16>* %a
228 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
229 %2 = load <8 x i16>* %b
230 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
231 %3 = icmp slt <8 x i16> %1, %2
232 %4 = sext <8 x i1> %3 to <8 x i16>
233 ; CHECK-DAG: clt_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
234 store <8 x i16> %4, <8 x i16>* %c
235 ; CHECK-DAG: st.h [[R3]], 0($4)
238 ; CHECK: .size clt_s_v8i16
241 define void @clt_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
242 ; CHECK: clt_s_v4i32:
244 %1 = load <4 x i32>* %a
245 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
246 %2 = load <4 x i32>* %b
247 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
248 %3 = icmp slt <4 x i32> %1, %2
249 %4 = sext <4 x i1> %3 to <4 x i32>
250 ; CHECK-DAG: clt_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
251 store <4 x i32> %4, <4 x i32>* %c
252 ; CHECK-DAG: st.w [[R3]], 0($4)
255 ; CHECK: .size clt_s_v4i32
258 define void @clt_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
259 ; CHECK: clt_s_v2i64:
261 %1 = load <2 x i64>* %a
262 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
263 %2 = load <2 x i64>* %b
264 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
265 %3 = icmp slt <2 x i64> %1, %2
266 %4 = sext <2 x i1> %3 to <2 x i64>
267 ; CHECK-DAG: clt_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
268 store <2 x i64> %4, <2 x i64>* %c
269 ; CHECK-DAG: st.d [[R3]], 0($4)
272 ; CHECK: .size clt_s_v2i64
275 define void @clt_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
276 ; CHECK: clt_u_v16i8:
278 %1 = load <16 x i8>* %a
279 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
280 %2 = load <16 x i8>* %b
281 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
282 %3 = icmp ult <16 x i8> %1, %2
283 %4 = sext <16 x i1> %3 to <16 x i8>
284 ; CHECK-DAG: clt_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
285 store <16 x i8> %4, <16 x i8>* %c
286 ; CHECK-DAG: st.b [[R3]], 0($4)
289 ; CHECK: .size clt_u_v16i8
292 define void @clt_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
293 ; CHECK: clt_u_v8i16:
295 %1 = load <8 x i16>* %a
296 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
297 %2 = load <8 x i16>* %b
298 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
299 %3 = icmp ult <8 x i16> %1, %2
300 %4 = sext <8 x i1> %3 to <8 x i16>
301 ; CHECK-DAG: clt_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
302 store <8 x i16> %4, <8 x i16>* %c
303 ; CHECK-DAG: st.h [[R3]], 0($4)
306 ; CHECK: .size clt_u_v8i16
309 define void @clt_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
310 ; CHECK: clt_u_v4i32:
312 %1 = load <4 x i32>* %a
313 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
314 %2 = load <4 x i32>* %b
315 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
316 %3 = icmp ult <4 x i32> %1, %2
317 %4 = sext <4 x i1> %3 to <4 x i32>
318 ; CHECK-DAG: clt_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
319 store <4 x i32> %4, <4 x i32>* %c
320 ; CHECK-DAG: st.w [[R3]], 0($4)
323 ; CHECK: .size clt_u_v4i32
326 define void @clt_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
327 ; CHECK: clt_u_v2i64:
329 %1 = load <2 x i64>* %a
330 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
331 %2 = load <2 x i64>* %b
332 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
333 %3 = icmp ult <2 x i64> %1, %2
334 %4 = sext <2 x i1> %3 to <2 x i64>
335 ; CHECK-DAG: clt_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
336 store <2 x i64> %4, <2 x i64>* %c
337 ; CHECK-DAG: st.d [[R3]], 0($4)
340 ; CHECK: .size clt_u_v2i64
343 define void @ceqi_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
346 %1 = load <16 x i8>* %a
347 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
348 %2 = icmp eq <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
349 %3 = sext <16 x i1> %2 to <16 x i8>
350 ; CHECK-DAG: ceqi.b [[R3:\$w[0-9]+]], [[R1]], 1
351 store <16 x i8> %3, <16 x i8>* %c
352 ; CHECK-DAG: st.b [[R3]], 0($4)
355 ; CHECK: .size ceqi_v16i8
358 define void @ceqi_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
361 %1 = load <8 x i16>* %a
362 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
363 %2 = icmp eq <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
364 %3 = sext <8 x i1> %2 to <8 x i16>
365 ; CHECK-DAG: ceqi.h [[R3:\$w[0-9]+]], [[R1]], 1
366 store <8 x i16> %3, <8 x i16>* %c
367 ; CHECK-DAG: st.h [[R3]], 0($4)
370 ; CHECK: .size ceqi_v8i16
373 define void @ceqi_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
376 %1 = load <4 x i32>* %a
377 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
378 %2 = icmp eq <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
379 %3 = sext <4 x i1> %2 to <4 x i32>
380 ; CHECK-DAG: ceqi.w [[R3:\$w[0-9]+]], [[R1]], 1
381 store <4 x i32> %3, <4 x i32>* %c
382 ; CHECK-DAG: st.w [[R3]], 0($4)
385 ; CHECK: .size ceqi_v4i32
388 define void @ceqi_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
391 %1 = load <2 x i64>* %a
392 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
393 %2 = icmp eq <2 x i64> %1, <i64 1, i64 1>
394 %3 = sext <2 x i1> %2 to <2 x i64>
395 ; CHECK-DAG: ceqi.d [[R3:\$w[0-9]+]], [[R1]], 1
396 store <2 x i64> %3, <2 x i64>* %c
397 ; CHECK-DAG: st.d [[R3]], 0($4)
400 ; CHECK: .size ceqi_v2i64
403 define void @clei_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
404 ; CHECK: clei_s_v16i8:
406 %1 = load <16 x i8>* %a
407 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
408 %2 = icmp sle <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
409 %3 = sext <16 x i1> %2 to <16 x i8>
410 ; CHECK-DAG: clei_s.b [[R3:\$w[0-9]+]], [[R1]], 1
411 store <16 x i8> %3, <16 x i8>* %c
412 ; CHECK-DAG: st.b [[R3]], 0($4)
415 ; CHECK: .size clei_s_v16i8
418 define void @clei_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
419 ; CHECK: clei_s_v8i16:
421 %1 = load <8 x i16>* %a
422 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
423 %2 = icmp sle <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
424 %3 = sext <8 x i1> %2 to <8 x i16>
425 ; CHECK-DAG: clei_s.h [[R3:\$w[0-9]+]], [[R1]], 1
426 store <8 x i16> %3, <8 x i16>* %c
427 ; CHECK-DAG: st.h [[R3]], 0($4)
430 ; CHECK: .size clei_s_v8i16
433 define void @clei_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
434 ; CHECK: clei_s_v4i32:
436 %1 = load <4 x i32>* %a
437 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
438 %2 = icmp sle <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
439 %3 = sext <4 x i1> %2 to <4 x i32>
440 ; CHECK-DAG: clei_s.w [[R3:\$w[0-9]+]], [[R1]], 1
441 store <4 x i32> %3, <4 x i32>* %c
442 ; CHECK-DAG: st.w [[R3]], 0($4)
445 ; CHECK: .size clei_s_v4i32
448 define void @clei_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
449 ; CHECK: clei_s_v2i64:
451 %1 = load <2 x i64>* %a
452 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
453 %2 = icmp sle <2 x i64> %1, <i64 1, i64 1>
454 %3 = sext <2 x i1> %2 to <2 x i64>
455 ; CHECK-DAG: clei_s.d [[R3:\$w[0-9]+]], [[R1]], 1
456 store <2 x i64> %3, <2 x i64>* %c
457 ; CHECK-DAG: st.d [[R3]], 0($4)
460 ; CHECK: .size clei_s_v2i64
463 define void @clei_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
464 ; CHECK: clei_u_v16i8:
466 %1 = load <16 x i8>* %a
467 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
468 %2 = icmp ule <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
469 %3 = sext <16 x i1> %2 to <16 x i8>
470 ; CHECK-DAG: clei_u.b [[R3:\$w[0-9]+]], [[R1]], 1
471 store <16 x i8> %3, <16 x i8>* %c
472 ; CHECK-DAG: st.b [[R3]], 0($4)
475 ; CHECK: .size clei_u_v16i8
478 define void @clei_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
479 ; CHECK: clei_u_v8i16:
481 %1 = load <8 x i16>* %a
482 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
483 %2 = icmp ule <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
484 %3 = sext <8 x i1> %2 to <8 x i16>
485 ; CHECK-DAG: clei_u.h [[R3:\$w[0-9]+]], [[R1]], 1
486 store <8 x i16> %3, <8 x i16>* %c
487 ; CHECK-DAG: st.h [[R3]], 0($4)
490 ; CHECK: .size clei_u_v8i16
493 define void @clei_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
494 ; CHECK: clei_u_v4i32:
496 %1 = load <4 x i32>* %a
497 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
498 %2 = icmp ule <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
499 %3 = sext <4 x i1> %2 to <4 x i32>
500 ; CHECK-DAG: clei_u.w [[R3:\$w[0-9]+]], [[R1]], 1
501 store <4 x i32> %3, <4 x i32>* %c
502 ; CHECK-DAG: st.w [[R3]], 0($4)
505 ; CHECK: .size clei_u_v4i32
508 define void @clei_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
509 ; CHECK: clei_u_v2i64:
511 %1 = load <2 x i64>* %a
512 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
513 %2 = icmp ule <2 x i64> %1, <i64 1, i64 1>
514 %3 = sext <2 x i1> %2 to <2 x i64>
515 ; CHECK-DAG: clei_u.d [[R3:\$w[0-9]+]], [[R1]], 1
516 store <2 x i64> %3, <2 x i64>* %c
517 ; CHECK-DAG: st.d [[R3]], 0($4)
520 ; CHECK: .size clei_u_v2i64
523 define void @clti_s_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
524 ; CHECK: clti_s_v16i8:
526 %1 = load <16 x i8>* %a
527 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
528 %2 = icmp slt <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
529 %3 = sext <16 x i1> %2 to <16 x i8>
530 ; CHECK-DAG: clti_s.b [[R3:\$w[0-9]+]], [[R1]], 1
531 store <16 x i8> %3, <16 x i8>* %c
532 ; CHECK-DAG: st.b [[R3]], 0($4)
535 ; CHECK: .size clti_s_v16i8
538 define void @clti_s_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
539 ; CHECK: clti_s_v8i16:
541 %1 = load <8 x i16>* %a
542 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
543 %2 = icmp slt <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
544 %3 = sext <8 x i1> %2 to <8 x i16>
545 ; CHECK-DAG: clti_s.h [[R3:\$w[0-9]+]], [[R1]], 1
546 store <8 x i16> %3, <8 x i16>* %c
547 ; CHECK-DAG: st.h [[R3]], 0($4)
550 ; CHECK: .size clti_s_v8i16
553 define void @clti_s_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
554 ; CHECK: clti_s_v4i32:
556 %1 = load <4 x i32>* %a
557 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
558 %2 = icmp slt <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
559 %3 = sext <4 x i1> %2 to <4 x i32>
560 ; CHECK-DAG: clti_s.w [[R3:\$w[0-9]+]], [[R1]], 1
561 store <4 x i32> %3, <4 x i32>* %c
562 ; CHECK-DAG: st.w [[R3]], 0($4)
565 ; CHECK: .size clti_s_v4i32
568 define void @clti_s_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
569 ; CHECK: clti_s_v2i64:
571 %1 = load <2 x i64>* %a
572 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
573 %2 = icmp slt <2 x i64> %1, <i64 1, i64 1>
574 %3 = sext <2 x i1> %2 to <2 x i64>
575 ; CHECK-DAG: clti_s.d [[R3:\$w[0-9]+]], [[R1]], 1
576 store <2 x i64> %3, <2 x i64>* %c
577 ; CHECK-DAG: st.d [[R3]], 0($4)
580 ; CHECK: .size clti_s_v2i64
583 define void @clti_u_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
584 ; CHECK: clti_u_v16i8:
586 %1 = load <16 x i8>* %a
587 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
588 %2 = icmp ult <16 x i8> %1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
589 %3 = sext <16 x i1> %2 to <16 x i8>
590 ; CHECK-DAG: clti_u.b [[R3:\$w[0-9]+]], [[R1]], 1
591 store <16 x i8> %3, <16 x i8>* %c
592 ; CHECK-DAG: st.b [[R3]], 0($4)
595 ; CHECK: .size clti_u_v16i8
598 define void @clti_u_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
599 ; CHECK: clti_u_v8i16:
601 %1 = load <8 x i16>* %a
602 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
603 %2 = icmp ult <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
604 %3 = sext <8 x i1> %2 to <8 x i16>
605 ; CHECK-DAG: clti_u.h [[R3:\$w[0-9]+]], [[R1]], 1
606 store <8 x i16> %3, <8 x i16>* %c
607 ; CHECK-DAG: st.h [[R3]], 0($4)
610 ; CHECK: .size clti_u_v8i16
613 define void @clti_u_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
614 ; CHECK: clti_u_v4i32:
616 %1 = load <4 x i32>* %a
617 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
618 %2 = icmp ult <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
619 %3 = sext <4 x i1> %2 to <4 x i32>
620 ; CHECK-DAG: clti_u.w [[R3:\$w[0-9]+]], [[R1]], 1
621 store <4 x i32> %3, <4 x i32>* %c
622 ; CHECK-DAG: st.w [[R3]], 0($4)
625 ; CHECK: .size clti_u_v4i32
628 define void @clti_u_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
629 ; CHECK: clti_u_v2i64:
631 %1 = load <2 x i64>* %a
632 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
633 %2 = icmp ult <2 x i64> %1, <i64 1, i64 1>
634 %3 = sext <2 x i1> %2 to <2 x i64>
635 ; CHECK-DAG: clti_u.d [[R3:\$w[0-9]+]], [[R1]], 1
636 store <2 x i64> %3, <2 x i64>* %c
637 ; CHECK-DAG: st.d [[R3]], 0($4)
640 ; CHECK: .size clti_u_v2i64