1 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
3 @v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
4 @v2f64 = global <2 x double> <double 0.0, double 0.0>
5 @f32 = global float 0.0
6 @f64 = global double 0.0
8 define void @const_v4f32() nounwind {
11 store volatile <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>*@v4f32
12 ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
14 store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float>*@v4f32
15 ; MIPS32: lui [[R1:\$[0-9]+]], 16256
16 ; MIPS32: fill.w [[R2:\$w[0-9]+]], [[R1]]
18 store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
19 ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
21 store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
22 ; MIPS32: lui [[R1:\$[0-9]+]], 18304
23 ; MIPS32: ori [[R2:\$[0-9]+]], [[R1]], 128
24 ; MIPS32: fill.w [[R3:\$w[0-9]+]], [[R2]]
26 store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
27 ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
29 store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
30 ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
33 ; MIPS32: .size const_v4f32
36 define void @const_v2f64() nounwind {
37 ; MIPS32: const_v2f64:
39 store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64
40 ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
42 store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
43 ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
45 store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
46 ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
48 store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
49 ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
51 store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
52 ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
54 store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
55 ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
57 store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
58 ; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
61 ; MIPS32: .size const_v2f64
64 define void @nonconst_v4f32() nounwind {
65 ; MIPS32: nonconst_v4f32:
68 %2 = insertelement <4 x float> undef, float %1, i32 0
69 %3 = insertelement <4 x float> %2, float %1, i32 1
70 %4 = insertelement <4 x float> %3, float %1, i32 2
71 %5 = insertelement <4 x float> %4, float %1, i32 3
72 store volatile <4 x float> %5, <4 x float>*@v4f32
73 ; MIPS32: lwc1 $f[[R1:[0-9]+]], 0(
74 ; MIPS32: splati.w [[R2:\$w[0-9]+]], $w[[R1]]
77 ; MIPS32: .size nonconst_v4f32
80 define void @nonconst_v2f64() nounwind {
81 ; MIPS32: nonconst_v2f64:
83 %1 = load double *@f64
84 %2 = insertelement <2 x double> undef, double %1, i32 0
85 %3 = insertelement <2 x double> %2, double %1, i32 1
86 store volatile <2 x double> %3, <2 x double>*@v2f64
87 ; MIPS32: ldc1 $f[[R1:[0-9]+]], 0(
88 ; MIPS32: splati.d [[R2:\$w[0-9]+]], $w[[R1]]
91 ; MIPS32: .size nonconst_v2f64
94 define float @extract_v4f32() nounwind {
95 ; MIPS32: extract_v4f32:
97 %1 = load <4 x float>* @v4f32
98 ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
100 %2 = fadd <4 x float> %1, %1
101 ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
103 %3 = extractelement <4 x float> %2, i32 1
104 ; Element 1 can be obtained by splatting it across the vector and extracting
106 ; MIPS32-DAG: splati.w $w0, [[R1]][1]
109 ; MIPS32: .size extract_v4f32
112 define float @extract_v4f32_elt0() nounwind {
113 ; MIPS32: extract_v4f32_elt0:
115 %1 = load <4 x float>* @v4f32
116 ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
118 %2 = fadd <4 x float> %1, %1
119 ; MIPS32-DAG: fadd.w $w0, [[R1]], [[R1]]
121 %3 = extractelement <4 x float> %2, i32 0
122 ; Element 0 can be obtained by extracting $w0:sub_lo ($f0)
123 ; MIPS32-NOT: copy_u.w
127 ; MIPS32: .size extract_v4f32_elt0
130 define double @extract_v2f64() nounwind {
131 ; MIPS32: extract_v2f64:
133 %1 = load <2 x double>* @v2f64
134 ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
136 %2 = fadd <2 x double> %1, %1
137 ; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
139 %3 = extractelement <2 x double> %2, i32 1
140 ; Element 1 can be obtained by splatting it across the vector and extracting
142 ; MIPS32-DAG: splati.d $w0, [[R1]][1]
143 ; MIPS32-NOT: copy_u.w
150 ; MIPS32: .size extract_v2f64
153 define double @extract_v2f64_elt0() nounwind {
154 ; MIPS32: extract_v2f64_elt0:
156 %1 = load <2 x double>* @v2f64
157 ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
159 %2 = fadd <2 x double> %1, %1
160 ; MIPS32-DAG: fadd.d $w0, [[R1]], [[R1]]
162 %3 = extractelement <2 x double> %2, i32 0
163 ; Element 0 can be obtained by extracting $w0:sub_64 ($f0)
164 ; MIPS32-NOT: copy_u.w
171 ; MIPS32: .size extract_v2f64_elt0
174 define void @insert_v4f32(float %a) nounwind {
175 ; MIPS32: insert_v4f32:
177 %1 = load <4 x float>* @v4f32
178 ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
180 %2 = insertelement <4 x float> %1, float %a, i32 1
181 ; float argument passed in $f12
182 ; MIPS32-DAG: insve.w [[R1]][1], $w12[0]
184 store <4 x float> %2, <4 x float>* @v4f32
185 ; MIPS32-DAG: st.w [[R1]]
188 ; MIPS32: .size insert_v4f32
191 define void @insert_v2f64(double %a) nounwind {
192 ; MIPS32: insert_v2f64:
194 %1 = load <2 x double>* @v2f64
195 ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
197 %2 = insertelement <2 x double> %1, double %a, i32 1
198 ; double argument passed in $f12
199 ; MIPS32-DAG: insve.d [[R1]][1], $w12[0]
201 store <2 x double> %2, <2 x double>* @v2f64
202 ; MIPS32-DAG: st.d [[R1]]
205 ; MIPS32: .size insert_v2f64