1 ; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction
4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
6 @llvm_mips_mul_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
7 @llvm_mips_mul_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
8 @llvm_mips_mul_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
10 define void @llvm_mips_mul_q_h_test() nounwind {
12 %0 = load <8 x i16>* @llvm_mips_mul_q_h_ARG1
13 %1 = load <8 x i16>* @llvm_mips_mul_q_h_ARG2
14 %2 = tail call <8 x i16> @llvm.mips.mul.q.h(<8 x i16> %0, <8 x i16> %1)
15 store <8 x i16> %2, <8 x i16>* @llvm_mips_mul_q_h_RES
19 declare <8 x i16> @llvm.mips.mul.q.h(<8 x i16>, <8 x i16>) nounwind
21 ; CHECK: llvm_mips_mul_q_h_test:
26 ; CHECK: .size llvm_mips_mul_q_h_test
28 @llvm_mips_mul_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
29 @llvm_mips_mul_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
30 @llvm_mips_mul_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
32 define void @llvm_mips_mul_q_w_test() nounwind {
34 %0 = load <4 x i32>* @llvm_mips_mul_q_w_ARG1
35 %1 = load <4 x i32>* @llvm_mips_mul_q_w_ARG2
36 %2 = tail call <4 x i32> @llvm.mips.mul.q.w(<4 x i32> %0, <4 x i32> %1)
37 store <4 x i32> %2, <4 x i32>* @llvm_mips_mul_q_w_RES
41 declare <4 x i32> @llvm.mips.mul.q.w(<4 x i32>, <4 x i32>) nounwind
43 ; CHECK: llvm_mips_mul_q_w_test:
48 ; CHECK: .size llvm_mips_mul_q_w_test
50 @llvm_mips_mulr_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
51 @llvm_mips_mulr_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
52 @llvm_mips_mulr_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
54 define void @llvm_mips_mulr_q_h_test() nounwind {
56 %0 = load <8 x i16>* @llvm_mips_mulr_q_h_ARG1
57 %1 = load <8 x i16>* @llvm_mips_mulr_q_h_ARG2
58 %2 = tail call <8 x i16> @llvm.mips.mulr.q.h(<8 x i16> %0, <8 x i16> %1)
59 store <8 x i16> %2, <8 x i16>* @llvm_mips_mulr_q_h_RES
63 declare <8 x i16> @llvm.mips.mulr.q.h(<8 x i16>, <8 x i16>) nounwind
65 ; CHECK: llvm_mips_mulr_q_h_test:
70 ; CHECK: .size llvm_mips_mulr_q_h_test
72 @llvm_mips_mulr_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
73 @llvm_mips_mulr_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
74 @llvm_mips_mulr_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
76 define void @llvm_mips_mulr_q_w_test() nounwind {
78 %0 = load <4 x i32>* @llvm_mips_mulr_q_w_ARG1
79 %1 = load <4 x i32>* @llvm_mips_mulr_q_w_ARG2
80 %2 = tail call <4 x i32> @llvm.mips.mulr.q.w(<4 x i32> %0, <4 x i32> %1)
81 store <4 x i32> %2, <4 x i32>* @llvm_mips_mulr_q_w_RES
85 declare <4 x i32> @llvm.mips.mulr.q.w(<4 x i32>, <4 x i32>) nounwind
87 ; CHECK: llvm_mips_mulr_q_w_test:
92 ; CHECK: .size llvm_mips_mulr_q_w_test