1 ; Test the MSA intrinsics that are encoded with the 3RF instruction format and
2 ; use the result as a third operand and perform fixed-point operations.
4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
6 @llvm_mips_madd_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
7 @llvm_mips_madd_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
8 @llvm_mips_madd_q_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 16
9 @llvm_mips_madd_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
11 define void @llvm_mips_madd_q_h_test() nounwind {
13 %0 = load <8 x i16>* @llvm_mips_madd_q_h_ARG1
14 %1 = load <8 x i16>* @llvm_mips_madd_q_h_ARG2
15 %2 = load <8 x i16>* @llvm_mips_madd_q_h_ARG3
16 %3 = tail call <8 x i16> @llvm.mips.madd.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
17 store <8 x i16> %3, <8 x i16>* @llvm_mips_madd_q_h_RES
21 declare <8 x i16> @llvm.mips.madd.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
23 ; CHECK: llvm_mips_madd_q_h_test:
29 ; CHECK: .size llvm_mips_madd_q_h_test
31 @llvm_mips_madd_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
32 @llvm_mips_madd_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
33 @llvm_mips_madd_q_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 16
34 @llvm_mips_madd_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
36 define void @llvm_mips_madd_q_w_test() nounwind {
38 %0 = load <4 x i32>* @llvm_mips_madd_q_w_ARG1
39 %1 = load <4 x i32>* @llvm_mips_madd_q_w_ARG2
40 %2 = load <4 x i32>* @llvm_mips_madd_q_w_ARG3
41 %3 = tail call <4 x i32> @llvm.mips.madd.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
42 store <4 x i32> %3, <4 x i32>* @llvm_mips_madd_q_w_RES
46 declare <4 x i32> @llvm.mips.madd.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
48 ; CHECK: llvm_mips_madd_q_w_test:
54 ; CHECK: .size llvm_mips_madd_q_w_test
56 @llvm_mips_maddr_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
57 @llvm_mips_maddr_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
58 @llvm_mips_maddr_q_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 16
59 @llvm_mips_maddr_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
61 define void @llvm_mips_maddr_q_h_test() nounwind {
63 %0 = load <8 x i16>* @llvm_mips_maddr_q_h_ARG1
64 %1 = load <8 x i16>* @llvm_mips_maddr_q_h_ARG2
65 %2 = load <8 x i16>* @llvm_mips_maddr_q_h_ARG3
66 %3 = tail call <8 x i16> @llvm.mips.maddr.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
67 store <8 x i16> %3, <8 x i16>* @llvm_mips_maddr_q_h_RES
71 declare <8 x i16> @llvm.mips.maddr.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
73 ; CHECK: llvm_mips_maddr_q_h_test:
79 ; CHECK: .size llvm_mips_maddr_q_h_test
81 @llvm_mips_maddr_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
82 @llvm_mips_maddr_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
83 @llvm_mips_maddr_q_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 16
84 @llvm_mips_maddr_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
86 define void @llvm_mips_maddr_q_w_test() nounwind {
88 %0 = load <4 x i32>* @llvm_mips_maddr_q_w_ARG1
89 %1 = load <4 x i32>* @llvm_mips_maddr_q_w_ARG2
90 %2 = load <4 x i32>* @llvm_mips_maddr_q_w_ARG3
91 %3 = tail call <4 x i32> @llvm.mips.maddr.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
92 store <4 x i32> %3, <4 x i32>* @llvm_mips_maddr_q_w_RES
96 declare <4 x i32> @llvm.mips.maddr.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
98 ; CHECK: llvm_mips_maddr_q_w_test:
104 ; CHECK: .size llvm_mips_maddr_q_w_test
106 @llvm_mips_msub_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
107 @llvm_mips_msub_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
108 @llvm_mips_msub_q_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 16
109 @llvm_mips_msub_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
111 define void @llvm_mips_msub_q_h_test() nounwind {
113 %0 = load <8 x i16>* @llvm_mips_msub_q_h_ARG1
114 %1 = load <8 x i16>* @llvm_mips_msub_q_h_ARG2
115 %2 = load <8 x i16>* @llvm_mips_msub_q_h_ARG3
116 %3 = tail call <8 x i16> @llvm.mips.msub.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
117 store <8 x i16> %3, <8 x i16>* @llvm_mips_msub_q_h_RES
121 declare <8 x i16> @llvm.mips.msub.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
123 ; CHECK: llvm_mips_msub_q_h_test:
129 ; CHECK: .size llvm_mips_msub_q_h_test
131 @llvm_mips_msub_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
132 @llvm_mips_msub_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
133 @llvm_mips_msub_q_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 16
134 @llvm_mips_msub_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
136 define void @llvm_mips_msub_q_w_test() nounwind {
138 %0 = load <4 x i32>* @llvm_mips_msub_q_w_ARG1
139 %1 = load <4 x i32>* @llvm_mips_msub_q_w_ARG2
140 %2 = load <4 x i32>* @llvm_mips_msub_q_w_ARG3
141 %3 = tail call <4 x i32> @llvm.mips.msub.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
142 store <4 x i32> %3, <4 x i32>* @llvm_mips_msub_q_w_RES
146 declare <4 x i32> @llvm.mips.msub.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
148 ; CHECK: llvm_mips_msub_q_w_test:
154 ; CHECK: .size llvm_mips_msub_q_w_test
156 @llvm_mips_msubr_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
157 @llvm_mips_msubr_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
158 @llvm_mips_msubr_q_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23>, align 16
159 @llvm_mips_msubr_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
161 define void @llvm_mips_msubr_q_h_test() nounwind {
163 %0 = load <8 x i16>* @llvm_mips_msubr_q_h_ARG1
164 %1 = load <8 x i16>* @llvm_mips_msubr_q_h_ARG2
165 %2 = load <8 x i16>* @llvm_mips_msubr_q_h_ARG3
166 %3 = tail call <8 x i16> @llvm.mips.msubr.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
167 store <8 x i16> %3, <8 x i16>* @llvm_mips_msubr_q_h_RES
171 declare <8 x i16> @llvm.mips.msubr.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
173 ; CHECK: llvm_mips_msubr_q_h_test:
179 ; CHECK: .size llvm_mips_msubr_q_h_test
181 @llvm_mips_msubr_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
182 @llvm_mips_msubr_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
183 @llvm_mips_msubr_q_w_ARG3 = global <4 x i32> <i32 8, i32 9, i32 10, i32 11>, align 16
184 @llvm_mips_msubr_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
186 define void @llvm_mips_msubr_q_w_test() nounwind {
188 %0 = load <4 x i32>* @llvm_mips_msubr_q_w_ARG1
189 %1 = load <4 x i32>* @llvm_mips_msubr_q_w_ARG2
190 %2 = load <4 x i32>* @llvm_mips_msubr_q_w_ARG3
191 %3 = tail call <4 x i32> @llvm.mips.msubr.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
192 store <4 x i32> %3, <4 x i32>* @llvm_mips_msubr_q_w_RES
196 declare <4 x i32> @llvm.mips.msubr.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
198 ; CHECK: llvm_mips_msubr_q_w_test:
204 ; CHECK: .size llvm_mips_msubr_q_w_test