1 ; Test the MSA intrinsics that are encoded with the 3R instruction format.
2 ; There are lots of these so this covers those beginning with 'd'
4 ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
6 @llvm_mips_div_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
7 @llvm_mips_div_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
8 @llvm_mips_div_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
10 define void @llvm_mips_div_s_b_test() nounwind {
12 %0 = load <16 x i8>* @llvm_mips_div_s_b_ARG1
13 %1 = load <16 x i8>* @llvm_mips_div_s_b_ARG2
14 %2 = tail call <16 x i8> @llvm.mips.div.s.b(<16 x i8> %0, <16 x i8> %1)
15 store <16 x i8> %2, <16 x i8>* @llvm_mips_div_s_b_RES
19 declare <16 x i8> @llvm.mips.div.s.b(<16 x i8>, <16 x i8>) nounwind
21 ; CHECK: llvm_mips_div_s_b_test:
26 ; CHECK: .size llvm_mips_div_s_b_test
28 @llvm_mips_div_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
29 @llvm_mips_div_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
30 @llvm_mips_div_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
32 define void @llvm_mips_div_s_h_test() nounwind {
34 %0 = load <8 x i16>* @llvm_mips_div_s_h_ARG1
35 %1 = load <8 x i16>* @llvm_mips_div_s_h_ARG2
36 %2 = tail call <8 x i16> @llvm.mips.div.s.h(<8 x i16> %0, <8 x i16> %1)
37 store <8 x i16> %2, <8 x i16>* @llvm_mips_div_s_h_RES
41 declare <8 x i16> @llvm.mips.div.s.h(<8 x i16>, <8 x i16>) nounwind
43 ; CHECK: llvm_mips_div_s_h_test:
48 ; CHECK: .size llvm_mips_div_s_h_test
50 @llvm_mips_div_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
51 @llvm_mips_div_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
52 @llvm_mips_div_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
54 define void @llvm_mips_div_s_w_test() nounwind {
56 %0 = load <4 x i32>* @llvm_mips_div_s_w_ARG1
57 %1 = load <4 x i32>* @llvm_mips_div_s_w_ARG2
58 %2 = tail call <4 x i32> @llvm.mips.div.s.w(<4 x i32> %0, <4 x i32> %1)
59 store <4 x i32> %2, <4 x i32>* @llvm_mips_div_s_w_RES
63 declare <4 x i32> @llvm.mips.div.s.w(<4 x i32>, <4 x i32>) nounwind
65 ; CHECK: llvm_mips_div_s_w_test:
70 ; CHECK: .size llvm_mips_div_s_w_test
72 @llvm_mips_div_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
73 @llvm_mips_div_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
74 @llvm_mips_div_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
76 define void @llvm_mips_div_s_d_test() nounwind {
78 %0 = load <2 x i64>* @llvm_mips_div_s_d_ARG1
79 %1 = load <2 x i64>* @llvm_mips_div_s_d_ARG2
80 %2 = tail call <2 x i64> @llvm.mips.div.s.d(<2 x i64> %0, <2 x i64> %1)
81 store <2 x i64> %2, <2 x i64>* @llvm_mips_div_s_d_RES
85 declare <2 x i64> @llvm.mips.div.s.d(<2 x i64>, <2 x i64>) nounwind
87 ; CHECK: llvm_mips_div_s_d_test:
92 ; CHECK: .size llvm_mips_div_s_d_test
94 @llvm_mips_div_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
95 @llvm_mips_div_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
96 @llvm_mips_div_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
98 define void @llvm_mips_div_u_b_test() nounwind {
100 %0 = load <16 x i8>* @llvm_mips_div_u_b_ARG1
101 %1 = load <16 x i8>* @llvm_mips_div_u_b_ARG2
102 %2 = tail call <16 x i8> @llvm.mips.div.u.b(<16 x i8> %0, <16 x i8> %1)
103 store <16 x i8> %2, <16 x i8>* @llvm_mips_div_u_b_RES
107 declare <16 x i8> @llvm.mips.div.u.b(<16 x i8>, <16 x i8>) nounwind
109 ; CHECK: llvm_mips_div_u_b_test:
114 ; CHECK: .size llvm_mips_div_u_b_test
116 @llvm_mips_div_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
117 @llvm_mips_div_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
118 @llvm_mips_div_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
120 define void @llvm_mips_div_u_h_test() nounwind {
122 %0 = load <8 x i16>* @llvm_mips_div_u_h_ARG1
123 %1 = load <8 x i16>* @llvm_mips_div_u_h_ARG2
124 %2 = tail call <8 x i16> @llvm.mips.div.u.h(<8 x i16> %0, <8 x i16> %1)
125 store <8 x i16> %2, <8 x i16>* @llvm_mips_div_u_h_RES
129 declare <8 x i16> @llvm.mips.div.u.h(<8 x i16>, <8 x i16>) nounwind
131 ; CHECK: llvm_mips_div_u_h_test:
136 ; CHECK: .size llvm_mips_div_u_h_test
138 @llvm_mips_div_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
139 @llvm_mips_div_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
140 @llvm_mips_div_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
142 define void @llvm_mips_div_u_w_test() nounwind {
144 %0 = load <4 x i32>* @llvm_mips_div_u_w_ARG1
145 %1 = load <4 x i32>* @llvm_mips_div_u_w_ARG2
146 %2 = tail call <4 x i32> @llvm.mips.div.u.w(<4 x i32> %0, <4 x i32> %1)
147 store <4 x i32> %2, <4 x i32>* @llvm_mips_div_u_w_RES
151 declare <4 x i32> @llvm.mips.div.u.w(<4 x i32>, <4 x i32>) nounwind
153 ; CHECK: llvm_mips_div_u_w_test:
158 ; CHECK: .size llvm_mips_div_u_w_test
160 @llvm_mips_div_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
161 @llvm_mips_div_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
162 @llvm_mips_div_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
164 define void @llvm_mips_div_u_d_test() nounwind {
166 %0 = load <2 x i64>* @llvm_mips_div_u_d_ARG1
167 %1 = load <2 x i64>* @llvm_mips_div_u_d_ARG2
168 %2 = tail call <2 x i64> @llvm.mips.div.u.d(<2 x i64> %0, <2 x i64> %1)
169 store <2 x i64> %2, <2 x i64>* @llvm_mips_div_u_d_RES
173 declare <2 x i64> @llvm.mips.div.u.d(<2 x i64>, <2 x i64>) nounwind
175 ; CHECK: llvm_mips_div_u_d_test:
180 ; CHECK: .size llvm_mips_div_u_d_test
182 @llvm_mips_dotp_s_h_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3,
183 i8 4, i8 5, i8 6, i8 7,
184 i8 8, i8 9, i8 10, i8 11,
185 i8 12, i8 13, i8 14, i8 15>,
187 @llvm_mips_dotp_s_h_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19,
188 i8 20, i8 21, i8 22, i8 23,
189 i8 24, i8 25, i8 26, i8 27,
190 i8 28, i8 29, i8 30, i8 31>,
192 @llvm_mips_dotp_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0,
193 i16 0, i16 0, i16 0, i16 0>,
196 define void @llvm_mips_dotp_s_h_test() nounwind {
198 %0 = load <16 x i8>* @llvm_mips_dotp_s_h_ARG1
199 %1 = load <16 x i8>* @llvm_mips_dotp_s_h_ARG2
200 %2 = tail call <8 x i16> @llvm.mips.dotp.s.h(<16 x i8> %0, <16 x i8> %1)
201 store <8 x i16> %2, <8 x i16>* @llvm_mips_dotp_s_h_RES
205 declare <8 x i16> @llvm.mips.dotp.s.h(<16 x i8>, <16 x i8>) nounwind
207 ; CHECK: llvm_mips_dotp_s_h_test:
212 ; CHECK: .size llvm_mips_dotp_s_h_test
214 @llvm_mips_dotp_s_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3,
215 i16 4, i16 5, i16 6, i16 7>,
217 @llvm_mips_dotp_s_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7,
218 i16 8, i16 9, i16 10, i16 11>,
220 @llvm_mips_dotp_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>,
223 define void @llvm_mips_dotp_s_w_test() nounwind {
225 %0 = load <8 x i16>* @llvm_mips_dotp_s_w_ARG1
226 %1 = load <8 x i16>* @llvm_mips_dotp_s_w_ARG2
227 %2 = tail call <4 x i32> @llvm.mips.dotp.s.w(<8 x i16> %0, <8 x i16> %1)
228 store <4 x i32> %2, <4 x i32>* @llvm_mips_dotp_s_w_RES
232 declare <4 x i32> @llvm.mips.dotp.s.w(<8 x i16>, <8 x i16>) nounwind
234 ; CHECK: llvm_mips_dotp_s_w_test:
239 ; CHECK: .size llvm_mips_dotp_s_w_test
241 @llvm_mips_dotp_s_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 0, i32 1>,
243 @llvm_mips_dotp_s_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 2, i32 3>,
245 @llvm_mips_dotp_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
247 define void @llvm_mips_dotp_s_d_test() nounwind {
249 %0 = load <4 x i32>* @llvm_mips_dotp_s_d_ARG1
250 %1 = load <4 x i32>* @llvm_mips_dotp_s_d_ARG2
251 %2 = tail call <2 x i64> @llvm.mips.dotp.s.d(<4 x i32> %0, <4 x i32> %1)
252 store <2 x i64> %2, <2 x i64>* @llvm_mips_dotp_s_d_RES
256 declare <2 x i64> @llvm.mips.dotp.s.d(<4 x i32>, <4 x i32>) nounwind
258 ; CHECK: llvm_mips_dotp_s_d_test:
263 ; CHECK: .size llvm_mips_dotp_s_d_test
265 @llvm_mips_dotp_u_h_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3,
266 i8 4, i8 5, i8 6, i8 7,
267 i8 8, i8 9, i8 10, i8 11,
268 i8 12, i8 13, i8 14, i8 15>,
270 @llvm_mips_dotp_u_h_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19,
271 i8 20, i8 21, i8 22, i8 23,
272 i8 24, i8 25, i8 26, i8 27,
273 i8 28, i8 29, i8 30, i8 31>,
275 @llvm_mips_dotp_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0,
276 i16 0, i16 0, i16 0, i16 0>,
279 define void @llvm_mips_dotp_u_h_test() nounwind {
281 %0 = load <16 x i8>* @llvm_mips_dotp_u_h_ARG1
282 %1 = load <16 x i8>* @llvm_mips_dotp_u_h_ARG2
283 %2 = tail call <8 x i16> @llvm.mips.dotp.u.h(<16 x i8> %0, <16 x i8> %1)
284 store <8 x i16> %2, <8 x i16>* @llvm_mips_dotp_u_h_RES
288 declare <8 x i16> @llvm.mips.dotp.u.h(<16 x i8>, <16 x i8>) nounwind
290 ; CHECK: llvm_mips_dotp_u_h_test:
295 ; CHECK: .size llvm_mips_dotp_u_h_test
297 @llvm_mips_dotp_u_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3,
298 i16 4, i16 5, i16 6, i16 7>,
300 @llvm_mips_dotp_u_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7,
301 i16 8, i16 9, i16 10, i16 11>,
303 @llvm_mips_dotp_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>,
306 define void @llvm_mips_dotp_u_w_test() nounwind {
308 %0 = load <8 x i16>* @llvm_mips_dotp_u_w_ARG1
309 %1 = load <8 x i16>* @llvm_mips_dotp_u_w_ARG2
310 %2 = tail call <4 x i32> @llvm.mips.dotp.u.w(<8 x i16> %0, <8 x i16> %1)
311 store <4 x i32> %2, <4 x i32>* @llvm_mips_dotp_u_w_RES
315 declare <4 x i32> @llvm.mips.dotp.u.w(<8 x i16>, <8 x i16>) nounwind
317 ; CHECK: llvm_mips_dotp_u_w_test:
322 ; CHECK: .size llvm_mips_dotp_u_w_test
324 @llvm_mips_dotp_u_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 0, i32 1>,
326 @llvm_mips_dotp_u_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 2, i32 3>,
328 @llvm_mips_dotp_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
330 define void @llvm_mips_dotp_u_d_test() nounwind {
332 %0 = load <4 x i32>* @llvm_mips_dotp_u_d_ARG1
333 %1 = load <4 x i32>* @llvm_mips_dotp_u_d_ARG2
334 %2 = tail call <2 x i64> @llvm.mips.dotp.u.d(<4 x i32> %0, <4 x i32> %1)
335 store <2 x i64> %2, <2 x i64>* @llvm_mips_dotp_u_d_RES
339 declare <2 x i64> @llvm.mips.dotp.u.d(<4 x i32>, <4 x i32>) nounwind
341 ; CHECK: llvm_mips_dotp_u_d_test:
346 ; CHECK: .size llvm_mips_dotp_u_d_test