1 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2 ; RUN: -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3
3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4 ; RUN: -check-prefix=ALL -check-prefix=CMOV \
5 ; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
6 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
7 ; RUN: -check-prefix=ALL -check-prefix=CMOV \
8 ; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
9 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
10 ; RUN: -check-prefix=ALL -check-prefix=CMOV \
11 ; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
12 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
13 ; RUN: -check-prefix=ALL -check-prefix=CMOV \
14 ; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
15 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
16 ; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
17 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
18 ; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
19 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
20 ; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
21 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
22 ; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
23 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
24 ; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
25 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
26 ; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
27 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
28 ; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
29 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
30 ; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
32 define signext i1 @tst_select_i1_i1(i1 signext %s,
33 i1 signext %x, i1 signext %y) {
35 ; ALL-LABEL: tst_select_i1_i1:
37 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
38 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
45 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
46 ; CMOV: movn $6, $5, $[[T0]]
49 ; SEL: andi $[[T0:[0-9]+]], $4, 1
50 ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
51 ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
52 ; SEL: or $2, $[[T2]], $[[T1]]
53 %r = select i1 %s, i1 %x, i1 %y
57 define signext i8 @tst_select_i1_i8(i1 signext %s,
58 i8 signext %x, i8 signext %y) {
60 ; ALL-LABEL: tst_select_i1_i8:
62 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
63 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
70 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
71 ; CMOV: movn $6, $5, $[[T0]]
74 ; SEL: andi $[[T0:[0-9]+]], $4, 1
75 ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
76 ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
77 ; SEL: or $2, $[[T2]], $[[T1]]
78 %r = select i1 %s, i8 %x, i8 %y
82 define signext i32 @tst_select_i1_i32(i1 signext %s,
83 i32 signext %x, i32 signext %y) {
85 ; ALL-LABEL: tst_select_i1_i32:
87 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
88 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
95 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
96 ; CMOV: movn $6, $5, $[[T0]]
99 ; SEL: andi $[[T0:[0-9]+]], $4, 1
100 ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
101 ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
102 ; SEL: or $2, $[[T2]], $[[T1]]
103 %r = select i1 %s, i32 %x, i32 %y
107 define signext i64 @tst_select_i1_i64(i1 signext %s,
108 i64 signext %x, i64 signext %y) {
110 ; ALL-LABEL: tst_select_i1_i64:
112 ; M2: andi $[[T0:[0-9]+]], $4, 1
113 ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
115 ; M2: lw $[[T1:[0-9]+]], 16($sp)
117 ; FIXME: This branch is redundant
118 ; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]]
120 ; M2: lw $[[T2:[0-9]+]], 20($sp)
122 ; M2: move $2, $[[T1]]
124 ; M2: move $3, $[[T2]]
126 ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
127 ; CMOV-32: lw $2, 16($sp)
128 ; CMOV-32: movn $2, $6, $[[T0]]
129 ; CMOV-32: lw $3, 20($sp)
130 ; CMOV-32: movn $3, $7, $[[T0]]
132 ; SEL-32: andi $[[T0:[0-9]+]], $4, 1
133 ; SEL-32: selnez $[[T1:[0-9]+]], $6, $[[T0]]
134 ; SEL-32: lw $[[T2:[0-9]+]], 16($sp)
135 ; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]]
136 ; SEL-32: or $2, $[[T1]], $[[T3]]
137 ; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]]
138 ; SEL-32: lw $[[T5:[0-9]+]], 20($sp)
139 ; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]]
140 ; SEL-32: or $3, $[[T4]], $[[T6]]
142 ; M3: andi $[[T0:[0-9]+]], $4, 1
143 ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
150 ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
151 ; CMOV-64: movn $6, $5, $[[T0]]
152 ; CMOV-64: move $2, $6
154 ; SEL-64: andi $[[T0:[0-9]+]], $4, 1
155 ; FIXME: This shift is redundant
156 ; SEL-64: sll $[[T0]], $[[T0]], 0
157 ; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
158 ; SEL-64: selnez $[[T0]], $5, $[[T0]]
159 ; SEL-64: or $2, $[[T0]], $[[T1]]
160 %r = select i1 %s, i64 %x, i64 %y
164 define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
166 ; ALL-LABEL: tst_select_i1_float:
168 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
169 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
173 ; M3: mov.s $f13, $f14
177 ; M3: mov.s $f0, $f13
179 ; CMOV-32: mtc1 $6, $f0
180 ; CMOV-32: mtc1 $5, $f1
181 ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
182 ; CMOV-32: movn.s $f0, $f1, $[[T0]]
184 ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]]
185 ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]]
186 ; SEL-32: mtc1 $4, $f0
187 ; SEL-32: sel.s $f0, $[[F1]], $[[F0]]
189 ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
190 ; CMOV-64: movn.s $f14, $f13, $[[T0]]
191 ; CMOV-64: mov.s $f0, $f14
193 ; SEL-64: mtc1 $4, $f0
194 ; SEL-64: sel.s $f0, $f14, $f13
195 %r = select i1 %s, float %x, float %y
199 define float @tst_select_i1_float_reordered(float %x, float %y,
202 ; ALL-LABEL: tst_select_i1_float_reordered:
204 ; M2-M3: andi $[[T0:[0-9]+]], $6, 1
205 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
207 ; M2: mov.s $f12, $f14
208 ; M3: mov.s $f12, $f13
211 ; M2-M3: mov.s $f0, $f12
213 ; CMOV-32: andi $[[T0:[0-9]+]], $6, 1
214 ; CMOV-32: movn.s $f14, $f12, $[[T0]]
215 ; CMOV-32: mov.s $f0, $f14
217 ; SEL-32: mtc1 $6, $f0
218 ; SEL-32: sel.s $f0, $f14, $f12
220 ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
221 ; CMOV-64: movn.s $f13, $f12, $[[T0]]
222 ; CMOV-64: mov.s $f0, $f13
224 ; SEL-64: mtc1 $6, $f0
225 ; SEL-64: sel.s $f0, $f13, $f12
226 %r = select i1 %s, float %x, float %y
230 define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
232 ; ALL-LABEL: tst_select_i1_double:
234 ; M2: andi $[[T0:[0-9]+]], $4, 1
235 ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
237 ; M2: ldc1 $f0, 16($sp)
245 ; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]]
246 ; CMOV-32R1: mtc1 $6, $f{{[0-9]+}}
247 ; CMOV-32R2-R5: mthc1 $6, $[[F0]]
248 ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
249 ; CMOV-32: ldc1 $f0, 16($sp)
250 ; CMOV-32: movn.d $f0, $[[F0]], $[[T0]]
252 ; SEL-32: mtc1 $7, $[[F0:f[0-9]+]]
253 ; SEL-32: mthc1 $6, $[[F0]]
254 ; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp)
255 ; SEL-32: mtc1 $4, $f0
256 ; SEL-32: sel.d $f0, $[[F1]], $[[F0]]
258 ; M3: andi $[[T0:[0-9]+]], $4, 1
259 ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
261 ; M3: mov.d $f13, $f14
264 ; M3: mov.d $f0, $f13
266 ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
267 ; CMOV-64: movn.d $f14, $f13, $[[T0]]
268 ; CMOV-64: mov.d $f0, $f14
270 ; SEL-64: mtc1 $4, $f0
271 ; SEL-64: sel.d $f0, $f14, $f13
272 %r = select i1 %s, double %x, double %y
276 define double @tst_select_i1_double_reordered(double %x, double %y,
279 ; ALL-LABEL: tst_select_i1_double_reordered:
281 ; M2: lw $[[T0:[0-9]+]], 16($sp)
282 ; M2: andi $[[T1:[0-9]+]], $[[T0]], 1
283 ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]]
285 ; M2: mov.d $f12, $f14
288 ; M2: mov.d $f0, $f12
290 ; CMOV-32: lw $[[T0:[0-9]+]], 16($sp)
291 ; CMOV-32: andi $[[T1:[0-9]+]], $[[T0]], 1
292 ; CMOV-32: movn.d $f14, $f12, $[[T1]]
293 ; CMOV-32: mov.d $f0, $f14
295 ; SEL-32: lw $[[T0:[0-9]+]], 16($sp)
296 ; SEL-32: mtc1 $[[T0]], $f0
297 ; SEL-32: sel.d $f0, $f14, $f12
299 ; M3: andi $[[T0:[0-9]+]], $6, 1
300 ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
302 ; M3: mov.d $f12, $f13
305 ; M3: mov.d $f0, $f12
307 ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
308 ; CMOV-64: movn.d $f13, $f12, $[[T0]]
309 ; CMOV-64: mov.d $f0, $f13
311 ; SEL-64: mtc1 $6, $f0
312 ; SEL-64: sel.d $f0, $f13, $f12
313 %r = select i1 %s, double %x, double %y
317 define float @tst_select_fcmp_olt_float(float %x, float %y) {
319 ; ALL-LABEL: tst_select_fcmp_olt_float:
321 ; M2: c.olt.s $f12, $f14
322 ; M3: c.olt.s $f12, $f13
323 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
325 ; M2: mov.s $f12, $f14
326 ; M3: mov.s $f12, $f13
329 ; M2-M3: mov.s $f0, $f12
331 ; CMOV-32: c.olt.s $f12, $f14
332 ; CMOV-32: movt.s $f14, $f12, $fcc0
333 ; CMOV-32: mov.s $f0, $f14
335 ; SEL-32: cmp.lt.s $f0, $f12, $f14
336 ; SEL-32: sel.s $f0, $f14, $f12
338 ; CMOV-64: c.olt.s $f12, $f13
339 ; CMOV-64: movt.s $f13, $f12, $fcc0
340 ; CMOV-64: mov.s $f0, $f13
342 ; SEL-64: cmp.lt.s $f0, $f12, $f13
343 ; SEL-64: sel.s $f0, $f13, $f12
344 %s = fcmp olt float %x, %y
345 %r = select i1 %s, float %x, float %y
349 define float @tst_select_fcmp_ole_float(float %x, float %y) {
351 ; ALL-LABEL: tst_select_fcmp_ole_float:
353 ; M2: c.ole.s $f12, $f14
354 ; M3: c.ole.s $f12, $f13
355 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
357 ; M2: mov.s $f12, $f14
358 ; M3: mov.s $f12, $f13
361 ; M2-M3: mov.s $f0, $f12
363 ; CMOV-32: c.ole.s $f12, $f14
364 ; CMOV-32: movt.s $f14, $f12, $fcc0
365 ; CMOV-32: mov.s $f0, $f14
367 ; SEL-32: cmp.le.s $f0, $f12, $f14
368 ; SEL-32: sel.s $f0, $f14, $f12
370 ; CMOV-64: c.ole.s $f12, $f13
371 ; CMOV-64: movt.s $f13, $f12, $fcc0
372 ; CMOV-64: mov.s $f0, $f13
374 ; SEL-64: cmp.le.s $f0, $f12, $f13
375 ; SEL-64: sel.s $f0, $f13, $f12
376 %s = fcmp ole float %x, %y
377 %r = select i1 %s, float %x, float %y
381 define float @tst_select_fcmp_ogt_float(float %x, float %y) {
383 ; ALL-LABEL: tst_select_fcmp_ogt_float:
385 ; M2: c.ule.s $f12, $f14
386 ; M3: c.ule.s $f12, $f13
387 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
389 ; M2: mov.s $f12, $f14
390 ; M3: mov.s $f12, $f13
393 ; M2-M3: mov.s $f0, $f12
395 ; CMOV-32: c.ule.s $f12, $f14
396 ; CMOV-32: movf.s $f14, $f12, $fcc0
397 ; CMOV-32: mov.s $f0, $f14
399 ; SEL-32: cmp.lt.s $f0, $f14, $f12
400 ; SEL-32: sel.s $f0, $f14, $f12
402 ; CMOV-64: c.ule.s $f12, $f13
403 ; CMOV-64: movf.s $f13, $f12, $fcc0
404 ; CMOV-64: mov.s $f0, $f13
406 ; SEL-64: cmp.lt.s $f0, $f13, $f12
407 ; SEL-64: sel.s $f0, $f13, $f12
408 %s = fcmp ogt float %x, %y
409 %r = select i1 %s, float %x, float %y
413 define float @tst_select_fcmp_oge_float(float %x, float %y) {
415 ; ALL-LABEL: tst_select_fcmp_oge_float:
417 ; M2: c.ult.s $f12, $f14
418 ; M3: c.ult.s $f12, $f13
419 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
421 ; M2: mov.s $f12, $f14
422 ; M3: mov.s $f12, $f13
425 ; M2-M3: mov.s $f0, $f12
427 ; CMOV-32: c.ult.s $f12, $f14
428 ; CMOV-32: movf.s $f14, $f12, $fcc0
429 ; CMOV-32: mov.s $f0, $f14
431 ; SEL-32: cmp.le.s $f0, $f14, $f12
432 ; SEL-32: sel.s $f0, $f14, $f12
434 ; CMOV-64: c.ult.s $f12, $f13
435 ; CMOV-64: movf.s $f13, $f12, $fcc0
436 ; CMOV-64: mov.s $f0, $f13
438 ; SEL-64: cmp.le.s $f0, $f13, $f12
439 ; SEL-64: sel.s $f0, $f13, $f12
440 %s = fcmp oge float %x, %y
441 %r = select i1 %s, float %x, float %y
445 define float @tst_select_fcmp_oeq_float(float %x, float %y) {
447 ; ALL-LABEL: tst_select_fcmp_oeq_float:
449 ; M2: c.eq.s $f12, $f14
450 ; M3: c.eq.s $f12, $f13
451 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
453 ; M2: mov.s $f12, $f14
454 ; M3: mov.s $f12, $f13
457 ; M2-M3: mov.s $f0, $f12
459 ; CMOV-32: c.eq.s $f12, $f14
460 ; CMOV-32: movt.s $f14, $f12, $fcc0
461 ; CMOV-32: mov.s $f0, $f14
463 ; SEL-32: cmp.eq.s $f0, $f12, $f14
464 ; SEL-32: sel.s $f0, $f14, $f12
466 ; CMOV-64: c.eq.s $f12, $f13
467 ; CMOV-64: movt.s $f13, $f12, $fcc0
468 ; CMOV-64: mov.s $f0, $f13
470 ; SEL-64: cmp.eq.s $f0, $f12, $f13
471 ; SEL-64: sel.s $f0, $f13, $f12
472 %s = fcmp oeq float %x, %y
473 %r = select i1 %s, float %x, float %y
477 define float @tst_select_fcmp_one_float(float %x, float %y) {
479 ; ALL-LABEL: tst_select_fcmp_one_float:
481 ; M2: c.ueq.s $f12, $f14
482 ; M3: c.ueq.s $f12, $f13
483 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
485 ; M2: mov.s $f12, $f14
486 ; M3: mov.s $f12, $f13
489 ; M2-M3: mov.s $f0, $f12
491 ; CMOV-32: c.ueq.s $f12, $f14
492 ; CMOV-32: movf.s $f14, $f12, $fcc0
493 ; CMOV-32: mov.s $f0, $f14
495 ; SEL-32: cmp.ueq.s $f0, $f12, $f14
496 ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
497 ; SEL-32: not $[[T0]], $[[T0]]
498 ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
499 ; SEL-32: sel.s $f0, $f14, $f12
501 ; CMOV-64: c.ueq.s $f12, $f13
502 ; CMOV-64: movf.s $f13, $f12, $fcc0
503 ; CMOV-64: mov.s $f0, $f13
505 ; SEL-64: cmp.ueq.s $f0, $f12, $f13
506 ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0
507 ; SEL-64: not $[[T0]], $[[T0]]
508 ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
509 ; SEL-64: sel.s $f0, $f13, $f12
511 %s = fcmp one float %x, %y
512 %r = select i1 %s, float %x, float %y
516 define double @tst_select_fcmp_olt_double(double %x, double %y) {
518 ; ALL-LABEL: tst_select_fcmp_olt_double:
520 ; M2: c.olt.d $f12, $f14
521 ; M3: c.olt.d $f12, $f13
522 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
524 ; M2: mov.d $f12, $f14
525 ; M3: mov.d $f12, $f13
528 ; M2-M3: mov.d $f0, $f12
530 ; CMOV-32: c.olt.d $f12, $f14
531 ; CMOV-32: movt.d $f14, $f12, $fcc0
532 ; CMOV-32: mov.d $f0, $f14
534 ; SEL-32: cmp.lt.d $f0, $f12, $f14
535 ; SEL-32: sel.d $f0, $f14, $f12
537 ; CMOV-64: c.olt.d $f12, $f13
538 ; CMOV-64: movt.d $f13, $f12, $fcc0
539 ; CMOV-64: mov.d $f0, $f13
541 ; SEL-64: cmp.lt.d $f0, $f12, $f13
542 ; SEL-64: sel.d $f0, $f13, $f12
543 %s = fcmp olt double %x, %y
544 %r = select i1 %s, double %x, double %y
548 define double @tst_select_fcmp_ole_double(double %x, double %y) {
550 ; ALL-LABEL: tst_select_fcmp_ole_double:
552 ; M2: c.ole.d $f12, $f14
553 ; M3: c.ole.d $f12, $f13
554 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
556 ; M2: mov.d $f12, $f14
557 ; M3: mov.d $f12, $f13
560 ; M2-M3: mov.d $f0, $f12
562 ; CMOV-32: c.ole.d $f12, $f14
563 ; CMOV-32: movt.d $f14, $f12, $fcc0
564 ; CMOV-32: mov.d $f0, $f14
566 ; SEL-32: cmp.le.d $f0, $f12, $f14
567 ; SEL-32: sel.d $f0, $f14, $f12
569 ; CMOV-64: c.ole.d $f12, $f13
570 ; CMOV-64: movt.d $f13, $f12, $fcc0
571 ; CMOV-64: mov.d $f0, $f13
573 ; SEL-64: cmp.le.d $f0, $f12, $f13
574 ; SEL-64: sel.d $f0, $f13, $f12
575 %s = fcmp ole double %x, %y
576 %r = select i1 %s, double %x, double %y
580 define double @tst_select_fcmp_ogt_double(double %x, double %y) {
582 ; ALL-LABEL: tst_select_fcmp_ogt_double:
584 ; M2: c.ule.d $f12, $f14
585 ; M3: c.ule.d $f12, $f13
586 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
588 ; M2: mov.d $f12, $f14
589 ; M3: mov.d $f12, $f13
592 ; M2-M3: mov.d $f0, $f12
594 ; CMOV-32: c.ule.d $f12, $f14
595 ; CMOV-32: movf.d $f14, $f12, $fcc0
596 ; CMOV-32: mov.d $f0, $f14
598 ; SEL-32: cmp.lt.d $f0, $f14, $f12
599 ; SEL-32: sel.d $f0, $f14, $f12
601 ; CMOV-64: c.ule.d $f12, $f13
602 ; CMOV-64: movf.d $f13, $f12, $fcc0
603 ; CMOV-64: mov.d $f0, $f13
605 ; SEL-64: cmp.lt.d $f0, $f13, $f12
606 ; SEL-64: sel.d $f0, $f13, $f12
607 %s = fcmp ogt double %x, %y
608 %r = select i1 %s, double %x, double %y
612 define double @tst_select_fcmp_oge_double(double %x, double %y) {
614 ; ALL-LABEL: tst_select_fcmp_oge_double:
616 ; M2: c.ult.d $f12, $f14
617 ; M3: c.ult.d $f12, $f13
618 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
620 ; M2: mov.d $f12, $f14
621 ; M3: mov.d $f12, $f13
624 ; M2-M3: mov.d $f0, $f12
626 ; CMOV-32: c.ult.d $f12, $f14
627 ; CMOV-32: movf.d $f14, $f12, $fcc0
628 ; CMOV-32: mov.d $f0, $f14
630 ; SEL-32: cmp.le.d $f0, $f14, $f12
631 ; SEL-32: sel.d $f0, $f14, $f12
633 ; CMOV-64: c.ult.d $f12, $f13
634 ; CMOV-64: movf.d $f13, $f12, $fcc0
635 ; CMOV-64: mov.d $f0, $f13
637 ; SEL-64: cmp.le.d $f0, $f13, $f12
638 ; SEL-64: sel.d $f0, $f13, $f12
639 %s = fcmp oge double %x, %y
640 %r = select i1 %s, double %x, double %y
644 define double @tst_select_fcmp_oeq_double(double %x, double %y) {
646 ; ALL-LABEL: tst_select_fcmp_oeq_double:
648 ; M2: c.eq.d $f12, $f14
649 ; M3: c.eq.d $f12, $f13
650 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
652 ; M2: mov.d $f12, $f14
653 ; M3: mov.d $f12, $f13
656 ; M2-M3: mov.d $f0, $f12
658 ; CMOV-32: c.eq.d $f12, $f14
659 ; CMOV-32: movt.d $f14, $f12, $fcc0
660 ; CMOV-32: mov.d $f0, $f14
662 ; SEL-32: cmp.eq.d $f0, $f12, $f14
663 ; SEL-32: sel.d $f0, $f14, $f12
665 ; CMOV-64: c.eq.d $f12, $f13
666 ; CMOV-64: movt.d $f13, $f12, $fcc0
667 ; CMOV-64: mov.d $f0, $f13
669 ; SEL-64: cmp.eq.d $f0, $f12, $f13
670 ; SEL-64: sel.d $f0, $f13, $f12
671 %s = fcmp oeq double %x, %y
672 %r = select i1 %s, double %x, double %y
676 define double @tst_select_fcmp_one_double(double %x, double %y) {
678 ; ALL-LABEL: tst_select_fcmp_one_double:
680 ; M2: c.ueq.d $f12, $f14
681 ; M3: c.ueq.d $f12, $f13
682 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
684 ; M2: mov.d $f12, $f14
685 ; M3: mov.d $f12, $f13
688 ; M2-M3: mov.d $f0, $f12
690 ; CMOV-32: c.ueq.d $f12, $f14
691 ; CMOV-32: movf.d $f14, $f12, $fcc0
692 ; CMOV-32: mov.d $f0, $f14
694 ; SEL-32: cmp.ueq.d $f0, $f12, $f14
695 ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
696 ; SEL-32: not $[[T0]], $[[T0]]
697 ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
698 ; SEL-32: sel.d $f0, $f14, $f12
700 ; CMOV-64: c.ueq.d $f12, $f13
701 ; CMOV-64: movf.d $f13, $f12, $fcc0
702 ; CMOV-64: mov.d $f0, $f13
704 ; SEL-64: cmp.ueq.d $f0, $f12, $f13
705 ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0
706 ; SEL-64: not $[[T0]], $[[T0]]
707 ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
708 ; SEL-64: sel.d $f0, $f13, $f12
709 %s = fcmp one double %x, %y
710 %r = select i1 %s, double %x, double %y