1 ; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
2 ; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
3 ; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
4 ; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
5 ; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
6 ; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
7 ; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
8 ; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -mattr=micromips < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MICROMIPS
10 ; Keep one big-endian check so that we don't reduce testing, but don't add more
11 ; since endianness doesn't affect the body of the atomic operations.
12 ; RUN: llc -march=mips --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EB -check-prefix=NOT-MICROMIPS
14 @x = common global i32 0, align 4
16 define i32 @AtomicLoadAdd32(i32 signext %incr) nounwind {
18 %0 = atomicrmw add i32* @x, i32 %incr monotonic
21 ; ALL-LABEL: AtomicLoadAdd32:
23 ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
24 ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
26 ; ALL: $[[BB0:[A-Z_0-9]+]]:
27 ; ALL: ll $[[R1:[0-9]+]], 0($[[R0]])
28 ; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4
29 ; ALL: sc $[[R2]], 0($[[R0]])
30 ; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
31 ; MICROMIPS: beqzc $[[R2]], $[[BB0]]
34 define i32 @AtomicLoadNand32(i32 signext %incr) nounwind {
36 %0 = atomicrmw nand i32* @x, i32 %incr monotonic
39 ; ALL-LABEL: AtomicLoadNand32:
41 ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
42 ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
44 ; ALL: $[[BB0:[A-Z_0-9]+]]:
45 ; ALL: ll $[[R1:[0-9]+]], 0($[[R0]])
46 ; ALL: and $[[R3:[0-9]+]], $[[R1]], $4
47 ; ALL: nor $[[R2:[0-9]+]], $zero, $[[R3]]
48 ; ALL: sc $[[R2]], 0($[[R0]])
49 ; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
50 ; MICROMIPS: beqzc $[[R2]], $[[BB0]]
53 define i32 @AtomicSwap32(i32 signext %newval) nounwind {
55 %newval.addr = alloca i32, align 4
56 store i32 %newval, i32* %newval.addr, align 4
57 %tmp = load i32* %newval.addr, align 4
58 %0 = atomicrmw xchg i32* @x, i32 %tmp monotonic
61 ; ALL-LABEL: AtomicSwap32:
63 ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
64 ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)
66 ; ALL: $[[BB0:[A-Z_0-9]+]]:
67 ; ALL: ll ${{[0-9]+}}, 0($[[R0]])
68 ; ALL: sc $[[R2:[0-9]+]], 0($[[R0]])
69 ; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
70 ; MICROMIPS: beqzc $[[R2]], $[[BB0]]
73 define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind {
75 %newval.addr = alloca i32, align 4
76 store i32 %newval, i32* %newval.addr, align 4
77 %tmp = load i32* %newval.addr, align 4
78 %0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic monotonic
79 %1 = extractvalue { i32, i1 } %0, 0
82 ; ALL-LABEL: AtomicCmpSwap32:
84 ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
85 ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
87 ; ALL: $[[BB0:[A-Z_0-9]+]]:
88 ; ALL: ll $2, 0($[[R0]])
89 ; ALL: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
90 ; ALL: sc $[[R2:[0-9]+]], 0($[[R0]])
91 ; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
92 ; MICROMIPS: beqzc $[[R2]], $[[BB0]]
98 @y = common global i8 0, align 1
100 define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind {
102 %0 = atomicrmw add i8* @y, i8 %incr monotonic
105 ; ALL-LABEL: AtomicLoadAdd8:
107 ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(y)
108 ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(y)(
110 ; ALL: addiu $[[R1:[0-9]+]], $zero, -4
111 ; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
112 ; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
113 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
114 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
115 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
116 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
117 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
118 ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
119 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
121 ; ALL: $[[BB0:[A-Z_0-9]+]]:
122 ; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
123 ; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
124 ; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
125 ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
126 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
127 ; ALL: sc $[[R14]], 0($[[R2]])
128 ; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
129 ; MICROMIPS: beqzc $[[R14]], $[[BB0]]
131 ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
132 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
134 ; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24
135 ; NO-SEB-SEH: sra $2, $[[R17]], 24
137 ; HAS-SEB-SEH: seb $2, $[[R16]]
140 define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind {
142 %0 = atomicrmw sub i8* @y, i8 %incr monotonic
145 ; ALL-LABEL: AtomicLoadSub8:
147 ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(y)
148 ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(y)(
150 ; ALL: addiu $[[R1:[0-9]+]], $zero, -4
151 ; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
152 ; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
153 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
154 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
155 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
156 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
157 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
158 ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
159 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
161 ; ALL: $[[BB0:[A-Z_0-9]+]]:
162 ; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
163 ; ALL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
164 ; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
165 ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
166 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
167 ; ALL: sc $[[R14]], 0($[[R2]])
168 ; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
169 ; MICROMIPS: beqzc $[[R14]], $[[BB0]]
171 ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
172 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
174 ; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24
175 ; NO-SEB-SEH: sra $2, $[[R17]], 24
177 ; HAS-SEB-SEH:seb $2, $[[R16]]
180 define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind {
182 %0 = atomicrmw nand i8* @y, i8 %incr monotonic
185 ; ALL-LABEL: AtomicLoadNand8:
187 ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(y)
188 ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(y)(
190 ; ALL: addiu $[[R1:[0-9]+]], $zero, -4
191 ; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
192 ; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
193 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
194 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
195 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
196 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
197 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
198 ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
199 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
201 ; ALL: $[[BB0:[A-Z_0-9]+]]:
202 ; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
203 ; ALL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
204 ; ALL: nor $[[R11:[0-9]+]], $zero, $[[R18]]
205 ; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
206 ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
207 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
208 ; ALL: sc $[[R14]], 0($[[R2]])
209 ; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
210 ; MICROMIPS: beqzc $[[R14]], $[[BB0]]
212 ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
213 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
215 ; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24
216 ; NO-SEB-SEH: sra $2, $[[R17]], 24
218 ; HAS-SEB-SEH: seb $2, $[[R16]]
221 define signext i8 @AtomicSwap8(i8 signext %newval) nounwind {
223 %0 = atomicrmw xchg i8* @y, i8 %newval monotonic
226 ; ALL-LABEL: AtomicSwap8:
228 ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(y)
229 ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(y)(
231 ; ALL: addiu $[[R1:[0-9]+]], $zero, -4
232 ; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
233 ; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
234 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
235 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
236 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
237 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
238 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
239 ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
240 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
242 ; ALL: $[[BB0:[A-Z_0-9]+]]:
243 ; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
244 ; ALL: and $[[R18:[0-9]+]], $[[R9]], $[[R7]]
245 ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
246 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
247 ; ALL: sc $[[R14]], 0($[[R2]])
248 ; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
249 ; MICROMIPS: beqzc $[[R14]], $[[BB0]]
251 ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
252 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
254 ; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24
255 ; NO-SEB-SEH: sra $2, $[[R17]], 24
257 ; HAS-SEB-SEH: seb $2, $[[R16]]
261 define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
263 %pair0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic monotonic
264 %0 = extractvalue { i8, i1 } %pair0, 0
267 ; ALL-LABEL: AtomicCmpSwap8:
269 ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(y)
270 ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(y)(
272 ; ALL: addiu $[[R1:[0-9]+]], $zero, -4
273 ; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
274 ; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
275 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
276 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
277 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
278 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
279 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
280 ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
281 ; ALL: andi $[[R9:[0-9]+]], $4, 255
282 ; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]
283 ; ALL: andi $[[R11:[0-9]+]], $5, 255
284 ; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]
286 ; ALL: $[[BB0:[A-Z_0-9]+]]:
287 ; ALL: ll $[[R13:[0-9]+]], 0($[[R2]])
288 ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
289 ; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
291 ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
292 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
293 ; ALL: sc $[[R16]], 0($[[R2]])
294 ; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]]
295 ; MICROMIPS: beqzc $[[R16]], $[[BB0]]
298 ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
300 ; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24
301 ; NO-SEB-SEH: sra $2, $[[R18]], 24
303 ; HAS-SEB-SEH: seb $2, $[[R17]]
306 define i1 @AtomicCmpSwapRes8(i8* %ptr, i8 signext %oldval, i8 signext %newval) nounwind {
308 %0 = cmpxchg i8* %ptr, i8 %oldval, i8 %newval monotonic monotonic
309 %1 = extractvalue { i8, i1 } %0, 1
311 ; ALL-LABEL: AtomicCmpSwapRes8
313 ; ALL: addiu $[[R1:[0-9]+]], $zero, -4
314 ; ALL: and $[[R2:[0-9]+]], $4, $[[R1]]
315 ; ALL: andi $[[R3:[0-9]+]], $4, 3
316 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
317 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
318 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
319 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
320 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
321 ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
322 ; ALL: andi $[[R9:[0-9]+]], $5, 255
323 ; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]
324 ; ALL: andi $[[R11:[0-9]+]], $6, 255
325 ; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]
327 ; ALL: $[[BB0:[A-Z_0-9]+]]:
328 ; ALL: ll $[[R13:[0-9]+]], 0($[[R2]])
329 ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
330 ; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
332 ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
333 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
334 ; ALL: sc $[[R16]], 0($[[R2]])
335 ; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]]
336 ; MICROMIPS: beqzc $[[R16]], $[[BB0]]
339 ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
341 ; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24
342 ; NO-SEB-SEH: sra $[[R19:[0-9]+]], $[[R18]], 24
344 ; HAS-SEB-SEH: seb $[[R19:[0-9]+]], $[[R17]]
346 ; ALL: xor $[[R20:[0-9]+]], $[[R19]], $5
347 ; ALL: sltiu $2, $[[R20]], 1
350 ; Check one i16 so that we cover the seh sign extend
351 @z = common global i16 0, align 1
353 define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind {
355 %0 = atomicrmw add i16* @z, i16 %incr monotonic
358 ; ALL-LABEL: AtomicLoadAdd16:
360 ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(z)
361 ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(z)(
363 ; ALL: addiu $[[R1:[0-9]+]], $zero, -4
364 ; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
365 ; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
366 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 2
367 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
368 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
369 ; ALL: ori $[[R6:[0-9]+]], $zero, 65535
370 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
371 ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
372 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
374 ; ALL: $[[BB0:[A-Z_0-9]+]]:
375 ; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
376 ; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
377 ; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
378 ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
379 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
380 ; ALL: sc $[[R14]], 0($[[R2]])
381 ; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
382 ; MICROMIPS: beqzc $[[R14]], $[[BB0]]
384 ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
385 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
387 ; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 16
388 ; NO-SEB-SEH: sra $2, $[[R17]], 16
390 ; MIPS32R2: seh $2, $[[R16]]
394 @countsint = common global i32 0, align 4
396 define i32 @CheckSync(i32 signext %v) nounwind noinline {
398 %0 = atomicrmw add i32* @countsint, i32 %v seq_cst
401 ; ALL-LABEL: CheckSync:
410 ; make sure that this assertion in
411 ; TwoAddressInstructionPass::TryInstructionTransform does not fail:
413 ; line 1203: assert(TargetRegisterInfo::isVirtualRegister(regB) &&
415 ; it failed when MipsDAGToDAGISel::ReplaceUsesWithZeroReg replaced an
416 ; operand of an atomic instruction with register $zero.
417 @a = external global i32
419 define i32 @zeroreg() nounwind {
421 %pair0 = cmpxchg i32* @a, i32 1, i32 0 seq_cst seq_cst
422 %0 = extractvalue { i32, i1 } %pair0, 0
423 %1 = icmp eq i32 %0, 1
424 %conv = zext i1 %1 to i32
428 ; Check that MIPS32R6 has the correct offset range.
429 ; FIXME: At the moment, we don't seem to do addr+offset for any atomic load/store.
430 define i32 @AtomicLoadAdd32_OffGt9Bit(i32 signext %incr) nounwind {
432 %0 = atomicrmw add i32* getelementptr(i32* @x, i32 256), i32 %incr monotonic
435 ; ALL-LABEL: AtomicLoadAdd32_OffGt9Bit:
437 ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
438 ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
440 ; ALL: addiu $[[PTR:[0-9]+]], $[[R0]], 1024
441 ; ALL: $[[BB0:[A-Z_0-9]+]]:
442 ; ALL: ll $[[R1:[0-9]+]], 0($[[PTR]])
443 ; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4
444 ; ALL: sc $[[R2]], 0($[[PTR]])
445 ; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
446 ; MICROMIPS: beqzc $[[R2]], $[[BB0]]