1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
3 declare <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8>, <8 x i8>)
4 declare <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8>, <8 x i8>)
6 define <8 x i8> @test_uqshl_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
7 ; CHECK: test_uqshl_v8i8:
8 %tmp1 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
9 ; CHECK: ushl v0.8b, v0.8b, v1.8b
13 define <8 x i8> @test_sqshl_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
14 ; CHECK: test_sqshl_v8i8:
15 %tmp1 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
16 ; CHECK: sshl v0.8b, v0.8b, v1.8b
20 declare <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8>, <16 x i8>)
21 declare <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8>, <16 x i8>)
23 define <16 x i8> @test_ushl_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
24 ; CHECK: test_ushl_v16i8:
25 %tmp1 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
26 ; CHECK: ushl v0.16b, v0.16b, v1.16b
30 define <16 x i8> @test_sshl_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
31 ; CHECK: test_sshl_v16i8:
32 %tmp1 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
33 ; CHECK: sshl v0.16b, v0.16b, v1.16b
37 declare <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16>, <4 x i16>)
38 declare <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16>, <4 x i16>)
40 define <4 x i16> @test_ushl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
41 ; CHECK: test_ushl_v4i16:
42 %tmp1 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
43 ; CHECK: ushl v0.4h, v0.4h, v1.4h
47 define <4 x i16> @test_sshl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
48 ; CHECK: test_sshl_v4i16:
49 %tmp1 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
50 ; CHECK: sshl v0.4h, v0.4h, v1.4h
54 declare <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16>, <8 x i16>)
55 declare <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16>, <8 x i16>)
57 define <8 x i16> @test_ushl_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
58 ; CHECK: test_ushl_v8i16:
59 %tmp1 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
60 ; CHECK: ushl v0.8h, v0.8h, v1.8h
64 define <8 x i16> @test_sshl_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
65 ; CHECK: test_sshl_v8i16:
66 %tmp1 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
67 ; CHECK: sshl v0.8h, v0.8h, v1.8h
71 declare <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32>, <2 x i32>)
72 declare <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32>, <2 x i32>)
74 define <2 x i32> @test_ushl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
75 ; CHECK: test_ushl_v2i32:
76 %tmp1 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
77 ; CHECK: ushl v0.2s, v0.2s, v1.2s
81 define <2 x i32> @test_sshl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
82 ; CHECK: test_sshl_v2i32:
83 %tmp1 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
84 ; CHECK: sshl v0.2s, v0.2s, v1.2s
88 declare <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32>, <4 x i32>)
89 declare <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32>, <4 x i32>)
91 define <4 x i32> @test_ushl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
92 ; CHECK: test_ushl_v4i32:
93 %tmp1 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
94 ; CHECK: ushl v0.4s, v0.4s, v1.4s
98 define <4 x i32> @test_sshl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
99 ; CHECK: test_sshl_v4i32:
100 %tmp1 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
101 ; CHECK: sshl v0.4s, v0.4s, v1.4s
105 declare <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64>, <1 x i64>)
106 declare <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64>, <1 x i64>)
108 define <1 x i64> @test_ushl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
109 ; CHECK: test_ushl_v1i64:
110 %tmp1 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
111 ; CHECK: ushl d0, d0, d1
115 define <1 x i64> @test_sshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
116 ; CHECK: test_sshl_v1i64:
117 %tmp1 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
118 ; CHECK: sshl d0, d0, d1
122 declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>)
123 declare <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64>, <2 x i64>)
125 define <2 x i64> @test_ushl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
126 ; CHECK: test_ushl_v2i64:
127 %tmp1 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
128 ; CHECK: ushl v0.2d, v0.2d, v1.2d
132 define <2 x i64> @test_sshl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
133 ; CHECK: test_sshl_v2i64:
134 %tmp1 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
135 ; CHECK: sshl v0.2d, v0.2d, v1.2d
140 define <8 x i8> @test_shl_v8i8(<8 x i8> %a) {
141 ; CHECK: test_shl_v8i8:
142 ; CHECK: shl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #3
143 %tmp = shl <8 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
147 define <4 x i16> @test_shl_v4i16(<4 x i16> %a) {
148 ; CHECK: test_shl_v4i16:
149 ; CHECK: shl {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #3
150 %tmp = shl <4 x i16> %a, <i16 3, i16 3, i16 3, i16 3>
154 define <2 x i32> @test_shl_v2i32(<2 x i32> %a) {
155 ; CHECK: test_shl_v2i32:
156 ; CHECK: shl {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #3
157 %tmp = shl <2 x i32> %a, <i32 3, i32 3>
161 define <16 x i8> @test_shl_v16i8(<16 x i8> %a) {
162 ; CHECK: test_shl_v16i8:
163 ; CHECK: shl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #3
164 %tmp = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
168 define <8 x i16> @test_shl_v8i16(<8 x i16> %a) {
169 ; CHECK: test_shl_v8i16:
170 ; CHECK: shl {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #3
171 %tmp = shl <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
175 define <4 x i32> @test_shl_v4i32(<4 x i32> %a) {
176 ; CHECK: test_shl_v4i32:
177 ; CHECK: shl {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #3
178 %tmp = shl <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3>
182 define <2 x i64> @test_shl_v2i64(<2 x i64> %a) {
183 ; CHECK: test_shl_v2i64:
184 ; CHECK: shl {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #63
185 %tmp = shl <2 x i64> %a, <i64 63, i64 63>