1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 define float @test_vcvts_f32_s32(i32 %a) {
4 ; CHECK: test_vcvts_f32_s32
5 ; CHECK: scvtf {{s[0-9]+}}, {{s[0-9]+}}
7 %vcvtf.i = insertelement <1 x i32> undef, i32 %a, i32 0
8 %0 = call float @llvm.aarch64.neon.vcvtf32.s32(<1 x i32> %vcvtf.i)
12 declare float @llvm.aarch64.neon.vcvtf32.s32(<1 x i32>)
14 define double @test_vcvtd_f64_s64(i64 %a) {
15 ; CHECK: test_vcvtd_f64_s64
16 ; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
18 %vcvtf.i = insertelement <1 x i64> undef, i64 %a, i32 0
19 %0 = call double @llvm.aarch64.neon.vcvtf64.s64(<1 x i64> %vcvtf.i)
23 declare double @llvm.aarch64.neon.vcvtf64.s64(<1 x i64>)
25 define float @test_vcvts_f32_u32(i32 %a) {
26 ; CHECK: test_vcvts_f32_u32
27 ; CHECK: ucvtf {{s[0-9]+}}, {{s[0-9]+}}
29 %vcvtf.i = insertelement <1 x i32> undef, i32 %a, i32 0
30 %0 = call float @llvm.aarch64.neon.vcvtf32.u32(<1 x i32> %vcvtf.i)
34 declare float @llvm.aarch64.neon.vcvtf32.u32(<1 x i32>)
36 define double @test_vcvtd_f64_u64(i64 %a) {
37 ; CHECK: test_vcvtd_f64_u64
38 ; CHECK: ucvtf {{d[0-9]+}}, {{d[0-9]+}}
40 %vcvtf.i = insertelement <1 x i64> undef, i64 %a, i32 0
41 %0 = call double @llvm.aarch64.neon.vcvtf64.u64(<1 x i64> %vcvtf.i)
45 declare double @llvm.aarch64.neon.vcvtf64.u64(<1 x i64>)
47 define float @test_vcvts_n_f32_s32(i32 %a) {
48 ; CHECK: test_vcvts_n_f32_s32
49 ; CHECK: scvtf {{s[0-9]+}}, {{s[0-9]+}}, #1
51 %vcvtf = insertelement <1 x i32> undef, i32 %a, i32 0
52 %0 = call float @llvm.aarch64.neon.vcvtf32.n.s32(<1 x i32> %vcvtf, i32 1)
56 declare float @llvm.aarch64.neon.vcvtf32.n.s32(<1 x i32>, i32)
58 define double @test_vcvtd_n_f64_s64(i64 %a) {
59 ; CHECK: test_vcvtd_n_f64_s64
60 ; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}, #1
62 %vcvtf = insertelement <1 x i64> undef, i64 %a, i32 0
63 %0 = call double @llvm.aarch64.neon.vcvtf64.n.s64(<1 x i64> %vcvtf, i32 1)
67 declare double @llvm.aarch64.neon.vcvtf64.n.s64(<1 x i64>, i32)
69 define float @test_vcvts_n_f32_u32(i32 %a) {
70 ; CHECK: test_vcvts_n_f32_u32
71 ; CHECK: ucvtf {{s[0-9]+}}, {{s[0-9]+}}, #1
73 %vcvtf = insertelement <1 x i32> undef, i32 %a, i32 0
74 %0 = call float @llvm.aarch64.neon.vcvtf32.n.u32(<1 x i32> %vcvtf, i32 1)
78 declare float @llvm.aarch64.neon.vcvtf32.n.u32(<1 x i32>, i32)
80 define double @test_vcvtd_n_f64_u64(i64 %a) {
81 ; CHECK: test_vcvtd_n_f64_u64
82 ; CHECK: ucvtf {{d[0-9]+}}, {{d[0-9]+}}, #1
84 %vcvtf = insertelement <1 x i64> undef, i64 %a, i32 0
85 %0 = call double @llvm.aarch64.neon.vcvtf64.n.u64(<1 x i64> %vcvtf, i32 1)
89 declare double @llvm.aarch64.neon.vcvtf64.n.u64(<1 x i64>, i32)
91 define i32 @test_vcvts_n_s32_f32(float %a) {
92 ; CHECK: test_vcvts_n_s32_f32
93 ; CHECK: fcvtzs {{s[0-9]+}}, {{s[0-9]+}}, #0
95 %fcvtzs = insertelement <1 x float> undef, float %a, i32 0
96 %fcvtzs1 = call <1 x i32> @llvm.aarch64.neon.vcvts.n.s32.f32(<1 x float> %fcvtzs, i32 0)
97 %0 = extractelement <1 x i32> %fcvtzs1, i32 0
101 declare <1 x i32> @llvm.aarch64.neon.vcvts.n.s32.f32(<1 x float>, i32)
103 define i64 @test_vcvtd_n_s64_f64(double %a) {
104 ; CHECK: test_vcvtd_n_s64_f64
105 ; CHECK: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}, #0
107 %fcvtzs = insertelement <1 x double> undef, double %a, i32 0
108 %fcvtzs1 = call <1 x i64> @llvm.aarch64.neon.vcvtd.n.s64.f64(<1 x double> %fcvtzs, i32 0)
109 %0 = extractelement <1 x i64> %fcvtzs1, i32 0
113 declare <1 x i64> @llvm.aarch64.neon.vcvtd.n.s64.f64(<1 x double>, i32)
115 define i32 @test_vcvts_n_u32_f32(float %a) {
116 ; CHECK: test_vcvts_n_u32_f32
117 ; CHECK: fcvtzu {{s[0-9]+}}, {{s[0-9]+}}, #0
119 %fcvtzu = insertelement <1 x float> undef, float %a, i32 0
120 %fcvtzu1 = call <1 x i32> @llvm.aarch64.neon.vcvts.n.u32.f32(<1 x float> %fcvtzu, i32 0)
121 %0 = extractelement <1 x i32> %fcvtzu1, i32 0
125 declare <1 x i32> @llvm.aarch64.neon.vcvts.n.u32.f32(<1 x float>, i32)
127 define i64 @test_vcvtd_n_u64_f64(double %a) {
128 ; CHECK: test_vcvtd_n_u64_f64
129 ; CHECK: fcvtzu {{d[0-9]+}}, {{d[0-9]+}}, #0
131 %fcvtzu = insertelement <1 x double> undef, double %a, i32 0
132 %fcvtzu1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtd.n.u64.f64(<1 x double> %fcvtzu, i32 0)
133 %0 = extractelement <1 x i64> %fcvtzu1, i32 0
137 declare <1 x i64> @llvm.aarch64.neon.vcvtd.n.u64.f64(<1 x double>, i32)