1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
4 define <8 x i8> @mul8xi8(<8 x i8> %A, <8 x i8> %B) {
5 ;CHECK: mul {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
6 %tmp3 = mul <8 x i8> %A, %B;
10 define <16 x i8> @mul16xi8(<16 x i8> %A, <16 x i8> %B) {
11 ;CHECK: mul {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
12 %tmp3 = mul <16 x i8> %A, %B;
16 define <4 x i16> @mul4xi16(<4 x i16> %A, <4 x i16> %B) {
17 ;CHECK: mul {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
18 %tmp3 = mul <4 x i16> %A, %B;
22 define <8 x i16> @mul8xi16(<8 x i16> %A, <8 x i16> %B) {
23 ;CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
24 %tmp3 = mul <8 x i16> %A, %B;
28 define <2 x i32> @mul2xi32(<2 x i32> %A, <2 x i32> %B) {
29 ;CHECK: mul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
30 %tmp3 = mul <2 x i32> %A, %B;
34 define <4 x i32> @mul4x32(<4 x i32> %A, <4 x i32> %B) {
35 ;CHECK: mul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
36 %tmp3 = mul <4 x i32> %A, %B;
40 define <1 x i64> @mul1xi64(<1 x i64> %A, <1 x i64> %B) {
41 ;CHECK-LABEL: mul1xi64:
42 ;CHECK: mul x{{[0-9]+}}, x{{[0-9]+}}, x{{[0-9]+}}
43 %tmp3 = mul <1 x i64> %A, %B;
47 define <2 x i64> @mul2xi64(<2 x i64> %A, <2 x i64> %B) {
48 ;CHECK-LABEL: mul2xi64:
49 ;CHECK: mul x{{[0-9]+}}, x{{[0-9]+}}, x{{[0-9]+}}
50 ;CHECK: mul x{{[0-9]+}}, x{{[0-9]+}}, x{{[0-9]+}}
51 %tmp3 = mul <2 x i64> %A, %B;
55 define <2 x float> @mul2xfloat(<2 x float> %A, <2 x float> %B) {
56 ;CHECK: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
57 %tmp3 = fmul <2 x float> %A, %B;
61 define <4 x float> @mul4xfloat(<4 x float> %A, <4 x float> %B) {
62 ;CHECK: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
63 %tmp3 = fmul <4 x float> %A, %B;
66 define <2 x double> @mul2xdouble(<2 x double> %A, <2 x double> %B) {
67 ;CHECK: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
68 %tmp3 = fmul <2 x double> %A, %B;
69 ret <2 x double> %tmp3
73 define <2 x float> @div2xfloat(<2 x float> %A, <2 x float> %B) {
74 ;CHECK: fdiv {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
75 %tmp3 = fdiv <2 x float> %A, %B;
79 define <4 x float> @div4xfloat(<4 x float> %A, <4 x float> %B) {
80 ;CHECK: fdiv {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
81 %tmp3 = fdiv <4 x float> %A, %B;
84 define <2 x double> @div2xdouble(<2 x double> %A, <2 x double> %B) {
85 ;CHECK: fdiv {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
86 %tmp3 = fdiv <2 x double> %A, %B;
87 ret <2 x double> %tmp3
90 declare <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8>, <8 x i8>)
91 declare <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8>, <16 x i8>)
93 define <8 x i8> @poly_mulv8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
94 ; CHECK: poly_mulv8i8:
95 %prod = call <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
96 ; CHECK: pmul v0.8b, v0.8b, v1.8b
100 define <16 x i8> @poly_mulv16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
101 ; CHECK: poly_mulv16i8:
102 %prod = call <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
103 ; CHECK: pmul v0.16b, v0.16b, v1.16b
107 declare <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16>, <4 x i16>)
108 declare <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16>, <8 x i16>)
109 declare <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32>, <2 x i32>)
110 declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>)
112 define <4 x i16> @test_sqdmulh_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
113 ; CHECK: test_sqdmulh_v4i16:
114 %prod = call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
115 ; CHECK: sqdmulh v0.4h, v0.4h, v1.4h
119 define <8 x i16> @test_sqdmulh_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
120 ; CHECK: test_sqdmulh_v8i16:
121 %prod = call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
122 ; CHECK: sqdmulh v0.8h, v0.8h, v1.8h
126 define <2 x i32> @test_sqdmulh_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
127 ; CHECK: test_sqdmulh_v2i32:
128 %prod = call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
129 ; CHECK: sqdmulh v0.2s, v0.2s, v1.2s
133 define <4 x i32> @test_sqdmulh_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
134 ; CHECK: test_sqdmulh_v4i32:
135 %prod = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
136 ; CHECK: sqdmulh v0.4s, v0.4s, v1.4s
140 declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>)
141 declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>)
142 declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>)
143 declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>)
145 define <4 x i16> @test_sqrdmulh_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
146 ; CHECK: test_sqrdmulh_v4i16:
147 %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
148 ; CHECK: sqrdmulh v0.4h, v0.4h, v1.4h
152 define <8 x i16> @test_sqrdmulh_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
153 ; CHECK: test_sqrdmulh_v8i16:
154 %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
155 ; CHECK: sqrdmulh v0.8h, v0.8h, v1.8h
159 define <2 x i32> @test_sqrdmulh_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
160 ; CHECK: test_sqrdmulh_v2i32:
161 %prod = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
162 ; CHECK: sqrdmulh v0.2s, v0.2s, v1.2s
166 define <4 x i32> @test_sqrdmulh_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
167 ; CHECK: test_sqrdmulh_v4i32:
168 %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
169 ; CHECK: sqrdmulh v0.4s, v0.4s, v1.4s
173 declare <2 x float> @llvm.aarch64.neon.vmulx.v2f32(<2 x float>, <2 x float>)
174 declare <4 x float> @llvm.aarch64.neon.vmulx.v4f32(<4 x float>, <4 x float>)
175 declare <2 x double> @llvm.aarch64.neon.vmulx.v2f64(<2 x double>, <2 x double>)
177 define <2 x float> @fmulx_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
178 ; Using registers other than v0, v1 and v2 are possible, but would be odd.
179 ; CHECK: fmulx v0.2s, v0.2s, v1.2s
180 %val = call <2 x float> @llvm.aarch64.neon.vmulx.v2f32(<2 x float> %lhs, <2 x float> %rhs)
184 define <4 x float> @fmulx_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
185 ; Using registers other than v0, v1 and v2 are possible, but would be odd.
186 ; CHECK: fmulx v0.4s, v0.4s, v1.4s
187 %val = call <4 x float> @llvm.aarch64.neon.vmulx.v4f32(<4 x float> %lhs, <4 x float> %rhs)
191 define <2 x double> @fmulx_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
192 ; Using registers other than v0, v1 and v2 are possible, but would be odd.
193 ; CHECK: fmulx v0.2d, v0.2d, v1.2d
194 %val = call <2 x double> @llvm.aarch64.neon.vmulx.v2f64(<2 x double> %lhs, <2 x double> %rhs)
195 ret <2 x double> %val