1 ; RUN: llc -fast-isel -fast-isel-abort -mtriple=arm64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
4 ; CHECK: and [[REG1:w[0-9]+]], w1, #0xff
5 ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]]
6 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG2]], #0xff
7 define zeroext i8 @lslv_i8(i8 %a, i8 %b) {
13 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
14 define zeroext i8 @lsl_i8(i8 %a) {
19 ; CHECK-LABEL: lslv_i16
20 ; CHECK: and [[REG1:w[0-9]+]], w1, #0xffff
21 ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]]
22 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG2]], #0xffff
23 define zeroext i16 @lslv_i16(i16 %a, i16 %b) {
28 ; CHECK-LABEL: lsl_i16
29 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
30 define zeroext i16 @lsl_i16(i16 %a) {
35 ; CHECK-LABEL: lslv_i32
36 ; CHECK: lsl {{w[0-9]*}}, w0, w1
37 define zeroext i32 @lslv_i32(i32 %a, i32 %b) {
42 ; CHECK-LABEL: lsl_i32
43 ; CHECK: lsl {{w[0-9]*}}, {{w[0-9]*}}, #16
44 define zeroext i32 @lsl_i32(i32 %a) {
49 ; CHECK-LABEL: lslv_i64
50 ; CHECK: lsl {{x[0-9]*}}, x0, x1
51 define i64 @lslv_i64(i64 %a, i64 %b) {
56 ; FIXME: This shouldn't use the variable shift version.
57 ; CHECK-LABEL: lsl_i64
58 ; CHECK: lsl {{x[0-9]*}}, {{x[0-9]*}}, {{x[0-9]*}}
59 define i64 @lsl_i64(i64 %a) {
64 ; CHECK-LABEL: lsrv_i8
65 ; CHECK: and [[REG1:w[0-9]+]], w0, #0xff
66 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xff
67 ; CHECK-NEXT: lsr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
68 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xff
69 define zeroext i8 @lsrv_i8(i8 %a, i8 %b) {
75 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
76 define zeroext i8 @lsr_i8(i8 %a) {
81 ; CHECK-LABEL: lsrv_i16
82 ; CHECK: and [[REG1:w[0-9]+]], w0, #0xffff
83 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xffff
84 ; CHECK-NEXT: lsr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
85 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xffff
86 define zeroext i16 @lsrv_i16(i16 %a, i16 %b) {
91 ; CHECK-LABEL: lsr_i16
92 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
93 define zeroext i16 @lsr_i16(i16 %a) {
98 ; CHECK-LABEL: lsrv_i32
99 ; CHECK: lsr {{w[0-9]*}}, w0, w1
100 define zeroext i32 @lsrv_i32(i32 %a, i32 %b) {
105 ; CHECK-LABEL: lsr_i32
106 ; CHECK: lsr {{w[0-9]*}}, {{w[0-9]*}}, #16
107 define zeroext i32 @lsr_i32(i32 %a) {
112 ; CHECK-LABEL: lsrv_i64
113 ; CHECK: lsr {{x[0-9]*}}, x0, x1
114 define i64 @lsrv_i64(i64 %a, i64 %b) {
119 ; FIXME: This shouldn't use the variable shift version.
120 ; CHECK-LABEL: lsr_i64
121 ; CHECK: lsr {{x[0-9]*}}, {{x[0-9]*}}, {{x[0-9]*}}
122 define i64 @lsr_i64(i64 %a) {
127 ; CHECK-LABEL: asrv_i8
128 ; CHECK: sxtb [[REG1:w[0-9]+]], w0
129 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xff
130 ; CHECK-NEXT: asr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
131 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xff
132 define zeroext i8 @asrv_i8(i8 %a, i8 %b) {
137 ; CHECK-LABEL: asr_i8
138 ; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
139 define zeroext i8 @asr_i8(i8 %a) {
144 ; CHECK-LABEL: asrv_i16
145 ; CHECK: sxth [[REG1:w[0-9]+]], w0
146 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xffff
147 ; CHECK-NEXT: asr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
148 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xffff
149 define zeroext i16 @asrv_i16(i16 %a, i16 %b) {
154 ; CHECK-LABEL: asr_i16
155 ; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
156 define zeroext i16 @asr_i16(i16 %a) {
161 ; CHECK-LABEL: asrv_i32
162 ; CHECK: asr {{w[0-9]*}}, w0, w1
163 define zeroext i32 @asrv_i32(i32 %a, i32 %b) {
168 ; CHECK-LABEL: asr_i32
169 ; CHECK: asr {{w[0-9]*}}, {{w[0-9]*}}, #16
170 define zeroext i32 @asr_i32(i32 %a) {
175 ; CHECK-LABEL: asrv_i64
176 ; CHECK: asr {{x[0-9]*}}, x0, x1
177 define i64 @asrv_i64(i64 %a, i64 %b) {
182 ; FIXME: This shouldn't use the variable shift version.
183 ; CHECK-LABEL: asr_i64
184 ; CHECK: asr {{x[0-9]*}}, {{x[0-9]*}}, {{x[0-9]*}}
185 define i64 @asr_i64(i64 %a) {
190 ; CHECK-LABEL: shift_test1
191 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
192 ; CHECK-NEXT: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
193 define i32 @shift_test1(i8 %a) {
196 %3 = sext i8 %2 to i32