1 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefix=CHECK-AARCH64
2 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-none-apple-ios7.0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-ARM64
4 ; Check trunc i64 operation is translated as a subregister access
5 ; eliminating an i32 induction varible.
6 ; CHECK-AARCH64: add {{x[0-9]+}}, {{x[0-9]+}}, #1
7 ; CHECK-AARCH64-NOT: add {{w[0-9]+}}, {{w[0-9]+}}, #1
8 ; CHECK-AARCH64-NEXT: cmp {{w[0-9]+}}, {{w[0-9]+}}, uxtw
10 ; CHECK-ARM64-NOT: add {{x[0-9]+}}, {{x[0-9]+}}, #1
11 ; CHECK-ARM64: add {{w[0-9]+}}, {{w[0-9]+}}, #1
12 ; CHECK-ARM64-NEXT: cmp {{w[0-9]+}}, {{w[0-9]+}}
13 define void @test1_signed([8 x i8]* nocapture %a, i8* nocapture readonly %box, i8 %limit) minsize {
15 %conv = zext i8 %limit to i32
16 %cmp223 = icmp eq i8 %limit, 0
17 br i1 %cmp223, label %for.end15, label %for.body4.lr.ph.us
20 %indvars.iv = phi i64 [ 0, %for.body4.lr.ph.us ], [ %indvars.iv.next, %for.body4.us ]
21 %arrayidx6.us = getelementptr inbounds [8 x i8]* %a, i64 %indvars.iv26, i64 %indvars.iv
22 %0 = load i8* %arrayidx6.us, align 1
23 %idxprom7.us = zext i8 %0 to i64
24 %arrayidx8.us = getelementptr inbounds i8* %box, i64 %idxprom7.us
25 %1 = load i8* %arrayidx8.us, align 1
26 store i8 %1, i8* %arrayidx6.us, align 1
27 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
28 %2 = trunc i64 %indvars.iv.next to i32
29 %cmp2.us = icmp slt i32 %2, %conv
30 br i1 %cmp2.us, label %for.body4.us, label %for.cond1.for.inc13_crit_edge.us
33 %indvars.iv26 = phi i64 [ %indvars.iv.next27, %for.cond1.for.inc13_crit_edge.us ], [ 0, %entry ]
34 br label %for.body4.us
36 for.cond1.for.inc13_crit_edge.us:
37 %indvars.iv.next27 = add nuw nsw i64 %indvars.iv26, 1
38 %exitcond28 = icmp eq i64 %indvars.iv26, 3
39 br i1 %exitcond28, label %for.end15, label %for.body4.lr.ph.us