sound/sparc/cs4231.c

   1 /*
   2  * Driver for CS4231 sound chips found on Sparcs.
   3  * Copyright (C) 2002 David S. Miller <davem@redhat.com>
   4  *
   5  * Based entirely upon drivers/sbus/audio/cs4231.c which is:
   6  * Copyright (C) 1996, 1997, 1998, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
   7  * and also sound/isa/cs423x/cs4231_lib.c which is:
   8  * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/slab.h>
  15 #include <linux/delay.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/moduleparam.h>
  19
  20 #include <sound/driver.h>
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/info.h>
  24 #include <sound/control.h>
  25 #include <sound/timer.h>
  26 #include <sound/initval.h>
  27 #include <sound/pcm_params.h>
  28
  29 #include <asm/io.h>
  30 #include <asm/irq.h>
  31
  32 #ifdef CONFIG_SBUS
  33 #define SBUS_SUPPORT
  34 #endif
  35
  36 #ifdef SBUS_SUPPORT
  37 #include <asm/sbus.h>
  38 #endif
  39
  40 #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
  41 #define EBUS_SUPPORT
  42 #endif
  43
  44 #ifdef EBUS_SUPPORT
  45 #include <linux/pci.h>
  46 #include <asm/ebus.h>
  47 #endif
  48
  49 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  50 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  51 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  52
  53 module_param_array(index, int, NULL, 0444);
  54 MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
  55 module_param_array(id, charp, NULL, 0444);
  56 MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
  57 module_param_array(enable, bool, NULL, 0444);
  58 MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
  59 MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
  60 MODULE_DESCRIPTION("Sun CS4231");
  61 MODULE_LICENSE("GPL");
  62 MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
  63
  64 #ifdef SBUS_SUPPORT
  65 struct sbus_dma_info {
  66        spinlock_t      lock;
  67        int             dir;
  68        void __iomem    *regs;
  69 };
  70 #endif
  71
  72 typedef struct snd_cs4231 {
  73         spinlock_t              lock;
  74         void __iomem            *port;
  75 #ifdef EBUS_SUPPORT
  76         struct ebus_dma_info    eb2c;
  77         struct ebus_dma_info    eb2p;
  78 #endif
  79
  80 #ifdef SBUS_SUPPORT
  81         struct sbus_dma_info    sb2c;
  82         struct sbus_dma_info    sb2p;
  83 #endif
  84
  85         u32                     flags;
  86 #define CS4231_FLAG_EBUS        0x00000001
  87 #define CS4231_FLAG_PLAYBACK    0x00000002
  88 #define CS4231_FLAG_CAPTURE     0x00000004
  89
  90         snd_card_t              *card;
  91         snd_pcm_t               *pcm;
  92         snd_pcm_substream_t     *playback_substream;
  93         unsigned int            p_periods_sent;
  94         snd_pcm_substream_t     *capture_substream;
  95         unsigned int            c_periods_sent;
  96         snd_timer_t             *timer;
  97
  98         unsigned short mode;
  99 #define CS4231_MODE_NONE        0x0000
 100 #define CS4231_MODE_PLAY        0x0001
 101 #define CS4231_MODE_RECORD      0x0002
 102 #define CS4231_MODE_TIMER       0x0004
 103 #define CS4231_MODE_OPEN        (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER)
 104
 105         unsigned char           image[32];      /* registers image */
 106         int                     mce_bit;
 107         int                     calibrate_mute;
 108         struct semaphore        mce_mutex;
 109         struct semaphore        open_mutex;
 110
 111         union {
 112 #ifdef SBUS_SUPPORT
 113                 struct sbus_dev         *sdev;
 114 #endif
 115 #ifdef EBUS_SUPPORT
 116                 struct pci_dev          *pdev;
 117 #endif
 118         } dev_u;
 119         unsigned int            irq[2];
 120         unsigned int            regs_size;
 121         struct snd_cs4231       *next;
 122 } cs4231_t;
 123
 124 static cs4231_t *cs4231_list;
 125
 126 /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
 127  * now....  -DaveM
 128  */
 129
 130 /* IO ports */
 131
 132 #define CS4231P(chip, x)        ((chip)->port + c_d_c_CS4231##x)
 133
 134 /* XXX offsets are different than PC ISA chips... */
 135 #define c_d_c_CS4231REGSEL      0x0
 136 #define c_d_c_CS4231REG         0x4
 137 #define c_d_c_CS4231STATUS      0x8
 138 #define c_d_c_CS4231PIO         0xc
 139
 140 /* codec registers */
 141
 142 #define CS4231_LEFT_INPUT       0x00    /* left input control */
 143 #define CS4231_RIGHT_INPUT      0x01    /* right input control */
 144 #define CS4231_AUX1_LEFT_INPUT  0x02    /* left AUX1 input control */
 145 #define CS4231_AUX1_RIGHT_INPUT 0x03    /* right AUX1 input control */
 146 #define CS4231_AUX2_LEFT_INPUT  0x04    /* left AUX2 input control */
 147 #define CS4231_AUX2_RIGHT_INPUT 0x05    /* right AUX2 input control */
 148 #define CS4231_LEFT_OUTPUT      0x06    /* left output control register */
 149 #define CS4231_RIGHT_OUTPUT     0x07    /* right output control register */
 150 #define CS4231_PLAYBK_FORMAT    0x08    /* clock and data format - playback - bits 7-0 MCE */
 151 #define CS4231_IFACE_CTRL       0x09    /* interface control - bits 7-2 MCE */
 152 #define CS4231_PIN_CTRL         0x0a    /* pin control */
 153 #define CS4231_TEST_INIT        0x0b    /* test and initialization */
 154 #define CS4231_MISC_INFO        0x0c    /* miscellaneaous information */
 155 #define CS4231_LOOPBACK         0x0d    /* loopback control */
 156 #define CS4231_PLY_UPR_CNT      0x0e    /* playback upper base count */
 157 #define CS4231_PLY_LWR_CNT      0x0f    /* playback lower base count */
 158 #define CS4231_ALT_FEATURE_1    0x10    /* alternate #1 feature enable */
 159 #define CS4231_ALT_FEATURE_2    0x11    /* alternate #2 feature enable */
 160 #define CS4231_LEFT_LINE_IN     0x12    /* left line input control */
 161 #define CS4231_RIGHT_LINE_IN    0x13    /* right line input control */
 162 #define CS4231_TIMER_LOW        0x14    /* timer low byte */
 163 #define CS4231_TIMER_HIGH       0x15    /* timer high byte */
 164 #define CS4231_LEFT_MIC_INPUT   0x16    /* left MIC input control register (InterWave only) */
 165 #define CS4231_RIGHT_MIC_INPUT  0x17    /* right MIC input control register (InterWave only) */
 166 #define CS4236_EXT_REG          0x17    /* extended register access */
 167 #define CS4231_IRQ_STATUS       0x18    /* irq status register */
 168 #define CS4231_LINE_LEFT_OUTPUT 0x19    /* left line output control register (InterWave only) */
 169 #define CS4231_VERSION          0x19    /* CS4231(A) - version values */
 170 #define CS4231_MONO_CTRL        0x1a    /* mono input/output control */
 171 #define CS4231_LINE_RIGHT_OUTPUT 0x1b   /* right line output control register (InterWave only) */
 172 #define CS4235_LEFT_MASTER      0x1b    /* left master output control */
 173 #define CS4231_REC_FORMAT       0x1c    /* clock and data format - record - bits 7-0 MCE */
 174 #define CS4231_PLY_VAR_FREQ     0x1d    /* playback variable frequency */
 175 #define CS4235_RIGHT_MASTER     0x1d    /* right master output control */
 176 #define CS4231_REC_UPR_CNT      0x1e    /* record upper count */
 177 #define CS4231_REC_LWR_CNT      0x1f    /* record lower count */
 178
 179 /* definitions for codec register select port - CODECP( REGSEL ) */
 180
 181 #define CS4231_INIT             0x80    /* CODEC is initializing */
 182 #define CS4231_MCE              0x40    /* mode change enable */
 183 #define CS4231_TRD              0x20    /* transfer request disable */
 184
 185 /* definitions for codec status register - CODECP( STATUS ) */
 186
 187 #define CS4231_GLOBALIRQ        0x01    /* IRQ is active */
 188
 189 /* definitions for codec irq status - CS4231_IRQ_STATUS */
 190
 191 #define CS4231_PLAYBACK_IRQ     0x10
 192 #define CS4231_RECORD_IRQ       0x20
 193 #define CS4231_TIMER_IRQ        0x40
 194 #define CS4231_ALL_IRQS         0x70
 195 #define CS4231_REC_UNDERRUN     0x08
 196 #define CS4231_REC_OVERRUN      0x04
 197 #define CS4231_PLY_OVERRUN      0x02
 198 #define CS4231_PLY_UNDERRUN     0x01
 199
 200 /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
 201
 202 #define CS4231_ENABLE_MIC_GAIN  0x20
 203
 204 #define CS4231_MIXS_LINE        0x00
 205 #define CS4231_MIXS_AUX1        0x40
 206 #define CS4231_MIXS_MIC         0x80
 207 #define CS4231_MIXS_ALL         0xc0
 208
 209 /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
 210
 211 #define CS4231_LINEAR_8         0x00    /* 8-bit unsigned data */
 212 #define CS4231_ALAW_8           0x60    /* 8-bit A-law companded */
 213 #define CS4231_ULAW_8           0x20    /* 8-bit U-law companded */
 214 #define CS4231_LINEAR_16        0x40    /* 16-bit twos complement data - little endian */
 215 #define CS4231_LINEAR_16_BIG    0xc0    /* 16-bit twos complement data - big endian */
 216 #define CS4231_ADPCM_16         0xa0    /* 16-bit ADPCM */
 217 #define CS4231_STEREO           0x10    /* stereo mode */
 218 /* bits 3-1 define frequency divisor */
 219 #define CS4231_XTAL1            0x00    /* 24.576 crystal */
 220 #define CS4231_XTAL2            0x01    /* 16.9344 crystal */
 221
 222 /* definitions for interface control register - CS4231_IFACE_CTRL */
 223
 224 #define CS4231_RECORD_PIO       0x80    /* record PIO enable */
 225 #define CS4231_PLAYBACK_PIO     0x40    /* playback PIO enable */
 226 #define CS4231_CALIB_MODE       0x18    /* calibration mode bits */
 227 #define CS4231_AUTOCALIB        0x08    /* auto calibrate */
 228 #define CS4231_SINGLE_DMA       0x04    /* use single DMA channel */
 229 #define CS4231_RECORD_ENABLE    0x02    /* record enable */
 230 #define CS4231_PLAYBACK_ENABLE  0x01    /* playback enable */
 231
 232 /* definitions for pin control register - CS4231_PIN_CTRL */
 233
 234 #define CS4231_IRQ_ENABLE       0x02    /* enable IRQ */
 235 #define CS4231_XCTL1            0x40    /* external control #1 */
 236 #define CS4231_XCTL0            0x80    /* external control #0 */
 237
 238 /* definitions for test and init register - CS4231_TEST_INIT */
 239
 240 #define CS4231_CALIB_IN_PROGRESS 0x20   /* auto calibrate in progress */
 241 #define CS4231_DMA_REQUEST      0x10    /* DMA request in progress */
 242
 243 /* definitions for misc control register - CS4231_MISC_INFO */
 244
 245 #define CS4231_MODE2            0x40    /* MODE 2 */
 246 #define CS4231_IW_MODE3         0x6c    /* MODE 3 - InterWave enhanced mode */
 247 #define CS4231_4236_MODE3       0xe0    /* MODE 3 - CS4236+ enhanced mode */
 248
 249 /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
 250
 251 #define CS4231_DACZ             0x01    /* zero DAC when underrun */
 252 #define CS4231_TIMER_ENABLE     0x40    /* codec timer enable */
 253 #define CS4231_OLB              0x80    /* output level bit */
 254
 255 /* SBUS DMA register defines.  */
 256
 257 #define APCCSR  0x10UL  /* APC DMA CSR */
 258 #define APCCVA  0x20UL  /* APC Capture DMA Address */
 259 #define APCCC   0x24UL  /* APC Capture Count */
 260 #define APCCNVA 0x28UL  /* APC Capture DMA Next Address */
 261 #define APCCNC  0x2cUL  /* APC Capture Next Count */
 262 #define APCPVA  0x30UL  /* APC Play DMA Address */
 263 #define APCPC   0x34UL  /* APC Play Count */
 264 #define APCPNVA 0x38UL  /* APC Play DMA Next Address */
 265 #define APCPNC  0x3cUL  /* APC Play Next Count */
 266
 267 /* Defines for SBUS DMA-routines */
 268
 269 #define APCVA  0x0UL    /* APC DMA Address */
 270 #define APCC   0x4UL    /* APC Count */
 271 #define APCNVA 0x8UL    /* APC DMA Next Address */
 272 #define APCNC  0xcUL    /* APC Next Count */
 273 #define APC_PLAY 0x30UL /* Play registers start at 0x30 */
 274 #define APC_RECORD 0x20UL /* Record registers start at 0x20 */
 275
 276 /* APCCSR bits */
 277
 278 #define APC_INT_PENDING 0x800000 /* Interrupt Pending */
 279 #define APC_PLAY_INT    0x400000 /* Playback interrupt */
 280 #define APC_CAPT_INT    0x200000 /* Capture interrupt */
 281 #define APC_GENL_INT    0x100000 /* General interrupt */
 282 #define APC_XINT_ENA    0x80000  /* General ext int. enable */
 283 #define APC_XINT_PLAY   0x40000  /* Playback ext intr */
 284 #define APC_XINT_CAPT   0x20000  /* Capture ext intr */
 285 #define APC_XINT_GENL   0x10000  /* Error ext intr */
 286 #define APC_XINT_EMPT   0x8000   /* Pipe empty interrupt (0 write to pva) */
 287 #define APC_XINT_PEMP   0x4000   /* Play pipe empty (pva and pnva not set) */
 288 #define APC_XINT_PNVA   0x2000   /* Playback NVA dirty */
 289 #define APC_XINT_PENA   0x1000   /* play pipe empty Int enable */
 290 #define APC_XINT_COVF   0x800    /* Cap data dropped on floor */
 291 #define APC_XINT_CNVA   0x400    /* Capture NVA dirty */
 292 #define APC_XINT_CEMP   0x200    /* Capture pipe empty (cva and cnva not set) */
 293 #define APC_XINT_CENA   0x100    /* Cap. pipe empty int enable */
 294 #define APC_PPAUSE      0x80     /* Pause the play DMA */
 295 #define APC_CPAUSE      0x40     /* Pause the capture DMA */
 296 #define APC_CDC_RESET   0x20     /* CODEC RESET */
 297 #define APC_PDMA_READY  0x08     /* Play DMA Go */
 298 #define APC_CDMA_READY  0x04     /* Capture DMA Go */
 299 #define APC_CHIP_RESET  0x01     /* Reset the chip */
 300
 301 /* EBUS DMA register offsets  */
 302
 303 #define EBDMA_CSR       0x00UL  /* Control/Status */
 304 #define EBDMA_ADDR      0x04UL  /* DMA Address */
 305 #define EBDMA_COUNT     0x08UL  /* DMA Count */
 306
 307 /*
 308  *  Some variables
 309  */
 310
 311 static unsigned char freq_bits[14] = {
 312         /* 5510 */      0x00 | CS4231_XTAL2,
 313         /* 6620 */      0x0E | CS4231_XTAL2,
 314         /* 8000 */      0x00 | CS4231_XTAL1,
 315         /* 9600 */      0x0E | CS4231_XTAL1,
 316         /* 11025 */     0x02 | CS4231_XTAL2,
 317         /* 16000 */     0x02 | CS4231_XTAL1,
 318         /* 18900 */     0x04 | CS4231_XTAL2,
 319         /* 22050 */     0x06 | CS4231_XTAL2,
 320         /* 27042 */     0x04 | CS4231_XTAL1,
 321         /* 32000 */     0x06 | CS4231_XTAL1,
 322         /* 33075 */     0x0C | CS4231_XTAL2,
 323         /* 37800 */     0x08 | CS4231_XTAL2,
 324         /* 44100 */     0x0A | CS4231_XTAL2,
 325         /* 48000 */     0x0C | CS4231_XTAL1
 326 };
 327
 328 static unsigned int rates[14] = {
 329         5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
 330         27042, 32000, 33075, 37800, 44100, 48000
 331 };
 332
 333 static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
 334         .count  = 14,
 335         .list   = rates,
 336 };
 337
 338 static int snd_cs4231_xrate(snd_pcm_runtime_t *runtime)
 339 {
 340         return snd_pcm_hw_constraint_list(runtime, 0,
 341                                           SNDRV_PCM_HW_PARAM_RATE,
 342                                           &hw_constraints_rates);
 343 }
 344
 345 static unsigned char snd_cs4231_original_image[32] =
 346 {
 347         0x00,                   /* 00/00 - lic */
 348         0x00,                   /* 01/01 - ric */
 349         0x9f,                   /* 02/02 - la1ic */
 350         0x9f,                   /* 03/03 - ra1ic */
 351         0x9f,                   /* 04/04 - la2ic */
 352         0x9f,                   /* 05/05 - ra2ic */
 353         0xbf,                   /* 06/06 - loc */
 354         0xbf,                   /* 07/07 - roc */
 355         0x20,                   /* 08/08 - pdfr */
 356         CS4231_AUTOCALIB,       /* 09/09 - ic */
 357         0x00,                   /* 0a/10 - pc */
 358         0x00,                   /* 0b/11 - ti */
 359         CS4231_MODE2,           /* 0c/12 - mi */
 360         0x00,                   /* 0d/13 - lbc */
 361         0x00,                   /* 0e/14 - pbru */
 362         0x00,                   /* 0f/15 - pbrl */
 363         0x80,                   /* 10/16 - afei */
 364         0x01,                   /* 11/17 - afeii */
 365         0x9f,                   /* 12/18 - llic */
 366         0x9f,                   /* 13/19 - rlic */
 367         0x00,                   /* 14/20 - tlb */
 368         0x00,                   /* 15/21 - thb */
 369         0x00,                   /* 16/22 - la3mic/reserved */
 370         0x00,                   /* 17/23 - ra3mic/reserved */
 371         0x00,                   /* 18/24 - afs */
 372         0x00,                   /* 19/25 - lamoc/version */
 373         0x00,                   /* 1a/26 - mioc */
 374         0x00,                   /* 1b/27 - ramoc/reserved */
 375         0x20,                   /* 1c/28 - cdfr */
 376         0x00,                   /* 1d/29 - res4 */
 377         0x00,                   /* 1e/30 - cbru */
 378         0x00,                   /* 1f/31 - cbrl */
 379 };
 380
 381 static u8 __cs4231_readb(cs4231_t *cp, void __iomem *reg_addr)
 382 {
 383 #ifdef EBUS_SUPPORT
 384         if (cp->flags & CS4231_FLAG_EBUS) {
 385                 return readb(reg_addr);
 386         } else {
 387 #endif
 388 #ifdef SBUS_SUPPORT
 389                 return sbus_readb(reg_addr);
 390 #endif
 391 #ifdef EBUS_SUPPORT
 392         }
 393 #endif
 394 }
 395
 396 static void __cs4231_writeb(cs4231_t *cp, u8 val, void __iomem *reg_addr)
 397 {
 398 #ifdef EBUS_SUPPORT
 399         if (cp->flags & CS4231_FLAG_EBUS) {
 400                 return writeb(val, reg_addr);
 401         } else {
 402 #endif
 403 #ifdef SBUS_SUPPORT
 404                 return sbus_writeb(val, reg_addr);
 405 #endif
 406 #ifdef EBUS_SUPPORT
 407         }
 408 #endif
 409 }
 410
 411 /*
 412  *  Basic I/O functions
 413  */
 414
 415 static void snd_cs4231_outm(cs4231_t *chip, unsigned char reg,
 416                      unsigned char mask, unsigned char value)
 417 {
 418         int timeout;
 419         unsigned char tmp;
 420
 421         for (timeout = 250;
 422              timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
 423              timeout--)
 424                 udelay(100);
 425 #ifdef CONFIG_SND_DEBUG
 426         if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
 427                 snd_printdd("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
 428 #endif
 429         if (chip->calibrate_mute) {
 430                 chip->image[reg] &= mask;
 431                 chip->image[reg] |= value;
 432         } else {
 433                 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
 434                 mb();
 435                 tmp = (chip->image[reg] & mask) | value;
 436                 __cs4231_writeb(chip, tmp, CS4231P(chip, REG));
 437                 chip->image[reg] = tmp;
 438                 mb();
 439         }
 440 }
 441
 442 static void snd_cs4231_dout(cs4231_t *chip, unsigned char reg, unsigned char value)
 443 {
 444         int timeout;
 445
 446         for (timeout = 250;
 447              timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
 448              timeout--)
 449                 udelay(100);
 450 #ifdef CONFIG_SND_DEBUG
 451         if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
 452                 snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
 453 #endif
 454         __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
 455         __cs4231_writeb(chip, value, CS4231P(chip, REG));
 456         mb();
 457 }
 458
 459 static void snd_cs4231_out(cs4231_t *chip, unsigned char reg, unsigned char value)
 460 {
 461         int timeout;
 462
 463         for (timeout = 250;
 464              timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
 465              timeout--)
 466                 udelay(100);
 467 #ifdef CONFIG_SND_DEBUG
 468         if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
 469                 snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
 470 #endif
 471         __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
 472         __cs4231_writeb(chip, value, CS4231P(chip, REG));
 473         chip->image[reg] = value;
 474         mb();
 475 }
 476
 477 static unsigned char snd_cs4231_in(cs4231_t *chip, unsigned char reg)
 478 {
 479         int timeout;
 480         unsigned char ret;
 481
 482         for (timeout = 250;
 483              timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
 484              timeout--)
 485                 udelay(100);
 486 #ifdef CONFIG_SND_DEBUG
 487         if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
 488                 snd_printdd("in: auto calibration time out - reg = 0x%x\n", reg);
 489 #endif
 490         __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
 491         mb();
 492         ret = __cs4231_readb(chip, CS4231P(chip, REG));
 493         return ret;
 494 }
 495
 496 /*
 497  * SBUS DMA routines
 498  */
 499 #ifdef SBUS_SUPPORT
 500
 501 int sbus_dma_request(struct sbus_dma_info *base, dma_addr_t bus_addr, size_t len)
 502 {
 503         unsigned long flags;
 504         u32 test, csr;
 505         int err;
 506
 507         if (len >= (1 << 24))
 508                 return -EINVAL;
 509         spin_lock_irqsave(&base->lock, flags);
 510         csr = sbus_readl(base->regs + APCCSR);
 511         err = -EINVAL;
 512         test = APC_CDMA_READY;
 513         if ( base->dir == APC_PLAY )
 514                 test = APC_PDMA_READY;
 515         if (!(csr & test))
 516                 goto out;
 517         err = -EBUSY;
 518         csr = sbus_readl(base->regs + APCCSR);
 519         test = APC_XINT_CNVA;
 520         if ( base->dir == APC_PLAY )
 521                 test = APC_XINT_PNVA;
 522         if (!(csr & test))
 523                 goto out;
 524         err = 0;
 525         sbus_writel(bus_addr, base->regs + base->dir + APCNVA);
 526         sbus_writel(len, base->regs + base->dir + APCNC);
 527 out:
 528         spin_unlock_irqrestore(&base->lock, flags);
 529         return err;
 530 }
 531
 532 void sbus_dma_prepare(struct sbus_dma_info *base)
 533 {
 534         unsigned long flags;
 535         u32 csr, test;
 536
 537         spin_lock_irqsave(&base->lock, flags);
 538         csr = sbus_readl(base->regs + APCCSR);
 539         test =  APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
 540                 APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL |
 541                  APC_XINT_PENA;
 542         if ( base->dir == APC_RECORD )
 543                 test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
 544                         APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL;
 545         csr |= test;
 546         sbus_writel(csr, base->regs + APCCSR);
 547         spin_unlock_irqrestore(&base->lock, flags);
 548 }
 549
 550 void sbus_dma_enable(struct sbus_dma_info *base, int on)
 551 {
 552         unsigned long flags;
 553         u32 csr, shift;
 554
 555         spin_lock_irqsave(&base->lock, flags);
 556         if (!on) {
 557                 if (base->dir == APC_PLAY) {
 558                         sbus_writel(0, base->regs + base->dir + APCNVA);
 559                         sbus_writel(1, base->regs + base->dir + APCC);
 560                 }
 561                 else
 562                 {
 563                         sbus_writel(0, base->regs + base->dir + APCNC);
 564                         sbus_writel(0, base->regs + base->dir + APCVA);
 565                 }
 566         }
 567         udelay(500);
 568         csr = sbus_readl(base->regs + APCCSR);
 569         shift = 0;
 570         if ( base->dir == APC_PLAY )
 571                 shift = 1;
 572         if (on)
 573                 csr &= ~(APC_CPAUSE << shift);
 574         else
 575                 csr |= (APC_CPAUSE << shift);
 576         sbus_writel(csr, base->regs + APCCSR);
 577         if (on)
 578                 csr |= (APC_CDMA_READY << shift);
 579         else
 580                 csr &= ~(APC_CDMA_READY << shift);
 581         sbus_writel(csr, base->regs + APCCSR);
 582
 583         spin_unlock_irqrestore(&base->lock, flags);
 584 }
 585
 586 unsigned int sbus_dma_addr(struct sbus_dma_info *base)
 587 {
 588         return sbus_readl(base->regs + base->dir + APCVA);
 589 }
 590
 591 #endif
 592
 593 /*
 594  *  CS4231 detection / MCE routines
 595  */
 596
 597 static void snd_cs4231_busy_wait(cs4231_t *chip)
 598 {
 599         int timeout;
 600
 601         /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
 602         for (timeout = 5; timeout > 0; timeout--)
 603                 __cs4231_readb(chip, CS4231P(chip, REGSEL));
 604
 605         /* end of cleanup sequence */
 606         for (timeout = 500;
 607              timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
 608              timeout--)
 609                 udelay(1000);
 610 }
 611
 612 static void snd_cs4231_mce_up(cs4231_t *chip)
 613 {
 614         unsigned long flags;
 615         int timeout;
 616
 617         spin_lock_irqsave(&chip->lock, flags);
 618         for (timeout = 250; timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); timeout--)
 619                 udelay(100);
 620 #ifdef CONFIG_SND_DEBUG
 621         if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
 622                 snd_printdd("mce_up - auto calibration time out (0)\n");
 623 #endif
 624         chip->mce_bit |= CS4231_MCE;
 625         timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
 626         if (timeout == 0x80)
 627                 snd_printdd("mce_up [%p]: serious init problem - codec still busy\n", chip->port);
 628         if (!(timeout & CS4231_MCE))
 629                 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
 630         spin_unlock_irqrestore(&chip->lock, flags);
 631 }
 632
 633 static void snd_cs4231_mce_down(cs4231_t *chip)
 634 {
 635         unsigned long flags;
 636         int timeout;
 637
 638         spin_lock_irqsave(&chip->lock, flags);
 639         snd_cs4231_busy_wait(chip);
 640 #ifdef CONFIG_SND_DEBUG
 641         if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
 642                 snd_printdd("mce_down [%p] - auto calibration time out (0)\n", CS4231P(chip, REGSEL));
 643 #endif
 644         chip->mce_bit &= ~CS4231_MCE;
 645         timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
 646         __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
 647         if (timeout == 0x80)
 648                 snd_printdd("mce_down [%p]: serious init problem - codec still busy\n", chip->port);
 649         if ((timeout & CS4231_MCE) == 0) {
 650                 spin_unlock_irqrestore(&chip->lock, flags);
 651                 return;
 652         }
 653         snd_cs4231_busy_wait(chip);
 654
 655         /* calibration process */
 656
 657         for (timeout = 500; timeout > 0 && (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0; timeout--)
 658                 udelay(100);
 659         if ((snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0) {
 660                 snd_printd("cs4231_mce_down - auto calibration time out (1)\n");
 661                 spin_unlock_irqrestore(&chip->lock, flags);
 662                 return;
 663         }
 664
 665         /* in 10ms increments, check condition, up to 250ms */
 666         timeout = 25;
 667         while (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) {
 668                 spin_unlock_irqrestore(&chip->lock, flags);
 669                 if (--timeout < 0) {
 670                         snd_printk("mce_down - auto calibration time out (2)\n");
 671                         return;
 672                 }
 673                 msleep(10);
 674                 spin_lock_irqsave(&chip->lock, flags);
 675         }
 676
 677         /* in 10ms increments, check condition, up to 100ms */
 678         timeout = 10;
 679         while (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) {
 680                 spin_unlock_irqrestore(&chip->lock, flags);
 681                 if (--timeout < 0) {
 682                         snd_printk("mce_down - auto calibration time out (3)\n");
 683                         return;
 684                 }
 685                 msleep(10);
 686                 spin_lock_irqsave(&chip->lock, flags);
 687         }
 688         spin_unlock_irqrestore(&chip->lock, flags);
 689 }
 690
 691 #ifdef EBUS_SUPPORT
 692 static void snd_cs4231_ebus_advance_dma(struct ebus_dma_info *p, snd_pcm_substream_t *substream, unsigned int *periods_sent)
 693 {
 694         snd_pcm_runtime_t *runtime = substream->runtime;
 695
 696         while (1) {
 697                 unsigned int period_size = snd_pcm_lib_period_bytes(substream);
 698                 unsigned int offset = period_size * (*periods_sent);
 699
 700                 if (period_size >= (1 << 24))
 701                         BUG();
 702
 703                 if (ebus_dma_request(p, runtime->dma_addr + offset, period_size))
 704                         return;
 705                 (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
 706         }
 707 }
 708 #endif
 709
 710 #ifdef SBUS_SUPPORT
 711 static void snd_cs4231_sbus_advance_dma(struct sbus_dma_info *p, snd_pcm_substream_t *substream, unsigned int *periods_sent)
 712 {
 713         snd_pcm_runtime_t *runtime = substream->runtime;
 714
 715          while (1) {
 716                 unsigned int period_size = snd_pcm_lib_period_bytes(substream);
 717                 unsigned int offset = period_size * (*periods_sent);
 718
 719                 if (period_size > 0xffff + 1)
 720                         BUG();
 721
 722                 if (sbus_dma_request(p, runtime->dma_addr + offset, period_size))
 723                         return;
 724                 (*periods_sent) = (*periods_sent + 1) % runtime->periods;
 725         }
 726 }
 727 #endif
 728
 729 static void cs4231_dma_trigger(snd_pcm_substream_t *substream, unsigned int what, int on)
 730 {
 731         cs4231_t *chip = snd_pcm_substream_chip(substream);
 732
 733 #ifdef EBUS_SUPPORT
 734         if (chip->flags & CS4231_FLAG_EBUS) {
 735                 if (what & CS4231_PLAYBACK_ENABLE) {
 736                         if (on) {
 737                                 ebus_dma_prepare(&chip->eb2p, 0);
 738                                 ebus_dma_enable(&chip->eb2p, 1);
 739                                 snd_cs4231_ebus_advance_dma(&chip->eb2p,
 740                                         chip->playback_substream,
 741                                         &chip->p_periods_sent);
 742                         } else {
 743                                 ebus_dma_enable(&chip->eb2p, 0);
 744                         }
 745                 }
 746                 if (what & CS4231_RECORD_ENABLE) {
 747                         if (on) {
 748                                 ebus_dma_prepare(&chip->eb2c, 1);
 749                                 ebus_dma_enable(&chip->eb2c, 1);
 750                                 snd_cs4231_ebus_advance_dma(&chip->eb2c,
 751                                         chip->capture_substream,
 752                                         &chip->c_periods_sent);
 753                         } else {
 754                                 ebus_dma_enable(&chip->eb2c, 0);
 755                         }
 756                 }
 757         } else {
 758 #endif
 759 #ifdef SBUS_SUPPORT
 760         if (what & CS4231_PLAYBACK_ENABLE) {
 761                 if (on) {
 762                         sbus_dma_prepare(&chip->sb2p);
 763                         sbus_dma_enable(&chip->sb2p, 1);
 764                         snd_cs4231_sbus_advance_dma(&chip->sb2p,
 765                                 chip->playback_substream,
 766                                 &chip->p_periods_sent);
 767                 } else {
 768                         sbus_dma_enable(&chip->sb2p, 0);
 769                 }
 770         }
 771         if (what & CS4231_RECORD_ENABLE) {
 772                 if (on) {
 773                         sbus_dma_prepare(&chip->sb2c);
 774                         sbus_dma_enable(&chip->sb2c, 1);
 775                         snd_cs4231_sbus_advance_dma(&chip->sb2c,
 776                                 chip->capture_substream,
 777                                 &chip->c_periods_sent);
 778                 } else {
 779                         sbus_dma_enable(&chip->sb2c, 0);
 780                 }
 781         }
 782 #endif
 783 #ifdef EBUS_SUPPORT
 784         }
 785 #endif
 786 }
 787
 788 static int snd_cs4231_trigger(snd_pcm_substream_t *substream, int cmd)
 789 {
 790         cs4231_t *chip = snd_pcm_substream_chip(substream);
 791         int result = 0;
 792
 793         switch (cmd) {
 794         case SNDRV_PCM_TRIGGER_START:
 795         case SNDRV_PCM_TRIGGER_STOP:
 796         {
 797                 unsigned int what = 0;
 798                 snd_pcm_substream_t *s;
 799                 struct list_head *pos;
 800                 unsigned long flags;
 801
 802                 snd_pcm_group_for_each(pos, substream) {
 803                         s = snd_pcm_group_substream_entry(pos);
 804                         if (s == chip->playback_substream) {
 805                                 what |= CS4231_PLAYBACK_ENABLE;
 806                                 snd_pcm_trigger_done(s, substream);
 807                         } else if (s == chip->capture_substream) {
 808                                 what |= CS4231_RECORD_ENABLE;
 809                                 snd_pcm_trigger_done(s, substream);
 810                         }
 811                 }
 812
 813                 spin_lock_irqsave(&chip->lock, flags);
 814                 if (cmd == SNDRV_PCM_TRIGGER_START) {
 815                         cs4231_dma_trigger(substream, what, 1);
 816                         chip->image[CS4231_IFACE_CTRL] |= what;
 817                 } else {
 818                         cs4231_dma_trigger(substream, what, 0);
 819                         chip->image[CS4231_IFACE_CTRL] &= ~what;
 820                 }
 821                 snd_cs4231_out(chip, CS4231_IFACE_CTRL,
 822                                chip->image[CS4231_IFACE_CTRL]);
 823                 spin_unlock_irqrestore(&chip->lock, flags);
 824                 break;
 825         }
 826         default:
 827                 result = -EINVAL;
 828                 break;
 829         }
 830
 831         return result;
 832 }
 833
 834 /*
 835  *  CODEC I/O
 836  */
 837
 838 static unsigned char snd_cs4231_get_rate(unsigned int rate)
 839 {
 840         int i;
 841
 842         for (i = 0; i < 14; i++)
 843                 if (rate == rates[i])
 844                         return freq_bits[i];
 845         // snd_BUG();
 846         return freq_bits[13];
 847 }
 848
 849 static unsigned char snd_cs4231_get_format(cs4231_t *chip, int format, int channels)
 850 {
 851         unsigned char rformat;
 852
 853         rformat = CS4231_LINEAR_8;
 854         switch (format) {
 855         case SNDRV_PCM_FORMAT_MU_LAW:   rformat = CS4231_ULAW_8; break;
 856         case SNDRV_PCM_FORMAT_A_LAW:    rformat = CS4231_ALAW_8; break;
 857         case SNDRV_PCM_FORMAT_S16_LE:   rformat = CS4231_LINEAR_16; break;
 858         case SNDRV_PCM_FORMAT_S16_BE:   rformat = CS4231_LINEAR_16_BIG; break;
 859         case SNDRV_PCM_FORMAT_IMA_ADPCM:        rformat = CS4231_ADPCM_16; break;
 860         }
 861         if (channels > 1)
 862                 rformat |= CS4231_STEREO;
 863         return rformat;
 864 }
 865
 866 static void snd_cs4231_calibrate_mute(cs4231_t *chip, int mute)
 867 {
 868         unsigned long flags;
 869
 870         mute = mute ? 1 : 0;
 871         spin_lock_irqsave(&chip->lock, flags);
 872         if (chip->calibrate_mute == mute) {
 873                 spin_unlock_irqrestore(&chip->lock, flags);
 874                 return;
 875         }
 876         if (!mute) {
 877                 snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
 878                                 chip->image[CS4231_LEFT_INPUT]);
 879                 snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
 880                                 chip->image[CS4231_RIGHT_INPUT]);
 881                 snd_cs4231_dout(chip, CS4231_LOOPBACK,
 882                                 chip->image[CS4231_LOOPBACK]);
 883         }
 884         snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
 885                         mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
 886         snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
 887                         mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
 888         snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
 889                         mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
 890         snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
 891                         mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
 892         snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
 893                         mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
 894         snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
 895                         mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
 896         snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
 897                         mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
 898         snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
 899                         mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
 900         snd_cs4231_dout(chip, CS4231_MONO_CTRL,
 901                         mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
 902         chip->calibrate_mute = mute;
 903         spin_unlock_irqrestore(&chip->lock, flags);
 904 }
 905
 906 static void snd_cs4231_playback_format(cs4231_t *chip, snd_pcm_hw_params_t *params,
 907                                        unsigned char pdfr)
 908 {
 909         unsigned long flags;
 910
 911         down(&chip->mce_mutex);
 912         snd_cs4231_calibrate_mute(chip, 1);
 913
 914         snd_cs4231_mce_up(chip);
 915
 916         spin_lock_irqsave(&chip->lock, flags);
 917         snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
 918                        (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
 919                        (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
 920                        pdfr);
 921         spin_unlock_irqrestore(&chip->lock, flags);
 922
 923         snd_cs4231_mce_down(chip);
 924
 925         snd_cs4231_calibrate_mute(chip, 0);
 926         up(&chip->mce_mutex);
 927 }
 928
 929 static void snd_cs4231_capture_format(cs4231_t *chip, snd_pcm_hw_params_t *params,
 930                                       unsigned char cdfr)
 931 {
 932         unsigned long flags;
 933
 934         down(&chip->mce_mutex);
 935         snd_cs4231_calibrate_mute(chip, 1);
 936
 937         snd_cs4231_mce_up(chip);
 938
 939         spin_lock_irqsave(&chip->lock, flags);
 940         if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
 941                 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
 942                                ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
 943                                (cdfr & 0x0f));
 944                 spin_unlock_irqrestore(&chip->lock, flags);
 945                 snd_cs4231_mce_down(chip);
 946                 snd_cs4231_mce_up(chip);
 947                 spin_lock_irqsave(&chip->lock, flags);
 948         }
 949         snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
 950         spin_unlock_irqrestore(&chip->lock, flags);
 951
 952         snd_cs4231_mce_down(chip);
 953
 954         snd_cs4231_calibrate_mute(chip, 0);
 955         up(&chip->mce_mutex);
 956 }
 957
 958 /*
 959  *  Timer interface
 960  */
 961
 962 static unsigned long snd_cs4231_timer_resolution(snd_timer_t *timer)
 963 {
 964         cs4231_t *chip = snd_timer_chip(timer);
 965
 966         return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
 967 }
 968
 969 static int snd_cs4231_timer_start(snd_timer_t *timer)
 970 {
 971         unsigned long flags;
 972         unsigned int ticks;
 973         cs4231_t *chip = snd_timer_chip(timer);
 974
 975         spin_lock_irqsave(&chip->lock, flags);
 976         ticks = timer->sticks;
 977         if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
 978             (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
 979             (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
 980                 snd_cs4231_out(chip, CS4231_TIMER_HIGH,
 981                                chip->image[CS4231_TIMER_HIGH] =
 982                                (unsigned char) (ticks >> 8));
 983                 snd_cs4231_out(chip, CS4231_TIMER_LOW,
 984                                chip->image[CS4231_TIMER_LOW] =
 985                                (unsigned char) ticks);
 986                 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
 987                                chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE);
 988         }
 989         spin_unlock_irqrestore(&chip->lock, flags);
 990
 991         return 0;
 992 }
 993
 994 static int snd_cs4231_timer_stop(snd_timer_t *timer)
 995 {
 996         unsigned long flags;
 997         cs4231_t *chip = snd_timer_chip(timer);
 998
 999         spin_lock_irqsave(&chip->lock, flags);
1000         snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
1001                        chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE);
1002         spin_unlock_irqrestore(&chip->lock, flags);
1003
1004         return 0;
1005 }
1006
1007 static void snd_cs4231_init(cs4231_t *chip)
1008 {
1009         unsigned long flags;
1010
1011         snd_cs4231_mce_down(chip);
1012
1013 #ifdef SNDRV_DEBUG_MCE
1014         snd_printdd("init: (1)\n");
1015 #endif
1016         snd_cs4231_mce_up(chip);
1017         spin_lock_irqsave(&chip->lock, flags);
1018         chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
1019                                             CS4231_RECORD_ENABLE | CS4231_RECORD_PIO |
1020                                             CS4231_CALIB_MODE);
1021         chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
1022         snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
1023         spin_unlock_irqrestore(&chip->lock, flags);
1024         snd_cs4231_mce_down(chip);
1025
1026 #ifdef SNDRV_DEBUG_MCE
1027         snd_printdd("init: (2)\n");
1028 #endif
1029
1030         snd_cs4231_mce_up(chip);
1031         spin_lock_irqsave(&chip->lock, flags);
1032         snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
1033         spin_unlock_irqrestore(&chip->lock, flags);
1034         snd_cs4231_mce_down(chip);
1035
1036 #ifdef SNDRV_DEBUG_MCE
1037         snd_printdd("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
1038 #endif
1039
1040         spin_lock_irqsave(&chip->lock, flags);
1041         snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]);
1042         spin_unlock_irqrestore(&chip->lock, flags);
1043
1044         snd_cs4231_mce_up(chip);
1045         spin_lock_irqsave(&chip->lock, flags);
1046         snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]);
1047         spin_unlock_irqrestore(&chip->lock, flags);
1048         snd_cs4231_mce_down(chip);
1049
1050 #ifdef SNDRV_DEBUG_MCE
1051         snd_printdd("init: (4)\n");
1052 #endif
1053
1054         snd_cs4231_mce_up(chip);
1055         spin_lock_irqsave(&chip->lock, flags);
1056         snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
1057         spin_unlock_irqrestore(&chip->lock, flags);
1058         snd_cs4231_mce_down(chip);
1059
1060 #ifdef SNDRV_DEBUG_MCE
1061         snd_printdd("init: (5)\n");
1062 #endif
1063 }
1064
1065 static int snd_cs4231_open(cs4231_t *chip, unsigned int mode)
1066 {
1067         unsigned long flags;
1068
1069         down(&chip->open_mutex);
1070         if ((chip->mode & mode)) {
1071                 up(&chip->open_mutex);
1072                 return -EAGAIN;
1073         }
1074         if (chip->mode & CS4231_MODE_OPEN) {
1075                 chip->mode |= mode;
1076                 up(&chip->open_mutex);
1077                 return 0;
1078         }
1079         /* ok. now enable and ack CODEC IRQ */
1080         spin_lock_irqsave(&chip->lock, flags);
1081         snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
1082                        CS4231_RECORD_IRQ |
1083                        CS4231_TIMER_IRQ);
1084         snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
1085         __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));        /* clear IRQ */
1086         __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));        /* clear IRQ */
1087
1088         snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
1089                        CS4231_RECORD_IRQ |
1090                        CS4231_TIMER_IRQ);
1091         snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
1092
1093         spin_unlock_irqrestore(&chip->lock, flags);
1094
1095         chip->mode = mode;
1096         up(&chip->open_mutex);
1097         return 0;
1098 }
1099
1100 static void snd_cs4231_close(cs4231_t *chip, unsigned int mode)
1101 {
1102         unsigned long flags;
1103
1104         down(&chip->open_mutex);
1105         chip->mode &= ~mode;
1106         if (chip->mode & CS4231_MODE_OPEN) {
1107                 up(&chip->open_mutex);
1108                 return;
1109         }
1110         snd_cs4231_calibrate_mute(chip, 1);
1111
1112         /* disable IRQ */
1113         spin_lock_irqsave(&chip->lock, flags);
1114         snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
1115         __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));        /* clear IRQ */
1116         __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));        /* clear IRQ */
1117
1118         /* now disable record & playback */
1119
1120         if (chip->image[CS4231_IFACE_CTRL] &
1121             (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
1122              CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
1123                 spin_unlock_irqrestore(&chip->lock, flags);
1124                 snd_cs4231_mce_up(chip);
1125                 spin_lock_irqsave(&chip->lock, flags);
1126                 chip->image[CS4231_IFACE_CTRL] &=
1127                         ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
1128                           CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
1129                 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
1130                 spin_unlock_irqrestore(&chip->lock, flags);
1131                 snd_cs4231_mce_down(chip);
1132                 spin_lock_irqsave(&chip->lock, flags);
1133         }
1134
1135         /* clear IRQ again */
1136         snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
1137         __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));        /* clear IRQ */
1138         __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));        /* clear IRQ */
1139         spin_unlock_irqrestore(&chip->lock, flags);
1140
1141         snd_cs4231_calibrate_mute(chip, 0);
1142
1143         chip->mode = 0;
1144         up(&chip->open_mutex);
1145 }
1146
1147 /*
1148  *  timer open/close
1149  */
1150
1151 static int snd_cs4231_timer_open(snd_timer_t *timer)
1152 {
1153         cs4231_t *chip = snd_timer_chip(timer);
1154         snd_cs4231_open(chip, CS4231_MODE_TIMER);
1155         return 0;
1156 }
1157
1158 static int snd_cs4231_timer_close(snd_timer_t * timer)
1159 {
1160         cs4231_t *chip = snd_timer_chip(timer);
1161         snd_cs4231_close(chip, CS4231_MODE_TIMER);
1162         return 0;
1163 }
1164
1165 static struct _snd_timer_hardware snd_cs4231_timer_table =
1166 {
1167         .flags          =       SNDRV_TIMER_HW_AUTO,
1168         .resolution     =       9945,
1169         .ticks          =       65535,
1170         .open           =       snd_cs4231_timer_open,
1171         .close          =       snd_cs4231_timer_close,
1172         .c_resolution   =       snd_cs4231_timer_resolution,
1173         .start          =       snd_cs4231_timer_start,
1174         .stop           =       snd_cs4231_timer_stop,
1175 };
1176
1177 /*
1178  *  ok.. exported functions..
1179  */
1180
1181 static int snd_cs4231_playback_hw_params(snd_pcm_substream_t *substream,
1182                                          snd_pcm_hw_params_t *hw_params)
1183 {
1184         cs4231_t *chip = snd_pcm_substream_chip(substream);
1185         unsigned char new_pdfr;
1186         int err;
1187
1188         if ((err = snd_pcm_lib_malloc_pages(substream,
1189                                             params_buffer_bytes(hw_params))) < 0)
1190                 return err;
1191         new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
1192                                          params_channels(hw_params)) |
1193                 snd_cs4231_get_rate(params_rate(hw_params));
1194         snd_cs4231_playback_format(chip, hw_params, new_pdfr);
1195
1196         return 0;
1197 }
1198
1199 static int snd_cs4231_playback_hw_free(snd_pcm_substream_t *substream)
1200 {
1201         return snd_pcm_lib_free_pages(substream);
1202 }
1203
1204 static int snd_cs4231_playback_prepare(snd_pcm_substream_t *substream)
1205 {
1206         cs4231_t *chip = snd_pcm_substream_chip(substream);
1207         snd_pcm_runtime_t *runtime = substream->runtime;
1208         unsigned long flags;
1209
1210         spin_lock_irqsave(&chip->lock, flags);
1211
1212         chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
1213                                             CS4231_PLAYBACK_PIO);
1214
1215         if (runtime->period_size > 0xffff + 1)
1216                 BUG();
1217
1218         chip->p_periods_sent = 0;
1219         spin_unlock_irqrestore(&chip->lock, flags);
1220
1221         return 0;
1222 }
1223
1224 static int snd_cs4231_capture_hw_params(snd_pcm_substream_t *substream,
1225                                         snd_pcm_hw_params_t *hw_params)
1226 {
1227         cs4231_t *chip = snd_pcm_substream_chip(substream);
1228         unsigned char new_cdfr;
1229         int err;
1230
1231         if ((err = snd_pcm_lib_malloc_pages(substream,
1232                                             params_buffer_bytes(hw_params))) < 0)
1233                 return err;
1234         new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
1235                                          params_channels(hw_params)) |
1236                 snd_cs4231_get_rate(params_rate(hw_params));
1237         snd_cs4231_capture_format(chip, hw_params, new_cdfr);
1238
1239         return 0;
1240 }
1241
1242 static int snd_cs4231_capture_hw_free(snd_pcm_substream_t *substream)
1243 {
1244         return snd_pcm_lib_free_pages(substream);
1245 }
1246
1247 static int snd_cs4231_capture_prepare(snd_pcm_substream_t *substream)
1248 {
1249         cs4231_t *chip = snd_pcm_substream_chip(substream);
1250         unsigned long flags;
1251
1252         spin_lock_irqsave(&chip->lock, flags);
1253         chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
1254                                             CS4231_RECORD_PIO);
1255
1256
1257         chip->c_periods_sent = 0;
1258         spin_unlock_irqrestore(&chip->lock, flags);
1259
1260         return 0;
1261 }
1262
1263 static void snd_cs4231_overrange(cs4231_t *chip)
1264 {
1265         unsigned long flags;
1266         unsigned char res;
1267
1268         spin_lock_irqsave(&chip->lock, flags);
1269         res = snd_cs4231_in(chip, CS4231_TEST_INIT);
1270         spin_unlock_irqrestore(&chip->lock, flags);
1271
1272         if (res & (0x08 | 0x02))        /* detect overrange only above 0dB; may be user selectable? */
1273                 chip->capture_substream->runtime->overrange++;
1274 }
1275
1276 #ifdef SBUS_SUPPORT
1277 static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1278 {
1279         unsigned long flags;
1280         unsigned char status;
1281         u32 csr;
1282         cs4231_t *chip = dev_id;
1283
1284         /*This is IRQ is not raised by the cs4231*/
1285         if (!(__cs4231_readb(chip, CS4231P(chip, STATUS)) & CS4231_GLOBALIRQ))
1286                 return IRQ_NONE;
1287
1288         /* ACK the APC interrupt. */
1289         csr = sbus_readl(chip->port + APCCSR);
1290
1291         sbus_writel(csr, chip->port + APCCSR);
1292
1293         if ((chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) &&
1294             (csr & APC_PLAY_INT) &&
1295             (csr & APC_XINT_PNVA) &&
1296             !(csr & APC_XINT_EMPT)) {
1297                 snd_pcm_period_elapsed(chip->playback_substream);
1298                 snd_cs4231_sbus_advance_dma(&chip->sb2p, chip->playback_substream,
1299                                             &chip->p_periods_sent);
1300         }
1301
1302         if ((chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) &&
1303             (csr & APC_CAPT_INT) &&
1304             (csr & APC_XINT_CNVA) &&
1305             !(csr & APC_XINT_EMPT)) {
1306                 snd_pcm_period_elapsed(chip->capture_substream);
1307                 snd_cs4231_sbus_advance_dma(&chip->sb2c,chip->capture_substream,
1308                                             &chip->c_periods_sent);
1309         }
1310
1311         status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
1312
1313         if (status & CS4231_TIMER_IRQ) {
1314                 if (chip->timer)
1315                         snd_timer_interrupt(chip->timer, chip->timer->sticks);
1316         }
1317
1318         if (status & CS4231_RECORD_IRQ)
1319                 snd_cs4231_overrange(chip);
1320
1321         /* ACK the CS4231 interrupt. */
1322         spin_lock_irqsave(&chip->lock, flags);
1323         snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
1324         spin_unlock_irqrestore(&chip->lock, flags);
1325
1326         return 0;
1327 }
1328 #endif
1329
1330 #ifdef EBUS_SUPPORT
1331 static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event, void *cookie)
1332 {
1333         cs4231_t *chip = cookie;
1334
1335         if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
1336                 snd_pcm_period_elapsed(chip->playback_substream);
1337                 snd_cs4231_ebus_advance_dma(p, chip->playback_substream,
1338                                             &chip->p_periods_sent);
1339         }
1340 }
1341
1342 static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p, int event, void *cookie)
1343 {
1344         cs4231_t *chip = cookie;
1345
1346         if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
1347                 snd_pcm_period_elapsed(chip->capture_substream);
1348                 snd_cs4231_ebus_advance_dma(p, chip->capture_substream,
1349                                             &chip->c_periods_sent);
1350         }
1351 }
1352 #endif
1353
1354 static snd_pcm_uframes_t snd_cs4231_playback_pointer(snd_pcm_substream_t *substream)
1355 {
1356         cs4231_t *chip = snd_pcm_substream_chip(substream);
1357         size_t ptr;
1358 #ifdef EBUS_SUPPORT
1359         size_t residue, period_bytes;
1360 #endif
1361
1362         if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
1363                 return 0;
1364 #ifdef EBUS_SUPPORT
1365         period_bytes = snd_pcm_lib_period_bytes(substream);
1366         ptr = period_bytes * chip->p_periods_sent;
1367         if (chip->flags & CS4231_FLAG_EBUS) {
1368                 residue = ebus_dma_residue(&chip->eb2p);
1369                 ptr += period_bytes - residue;
1370         } else {
1371 #endif
1372 #ifdef SBUS_SUPPORT
1373                 ptr = sbus_dma_addr(&chip->sb2p);
1374                 if (ptr != 0)
1375                         ptr -= substream->runtime->dma_addr;
1376 #endif
1377 #ifdef EBUS_SUPPORT
1378         }
1379 #endif
1380
1381         return bytes_to_frames(substream->runtime, ptr);
1382 }
1383
1384 static snd_pcm_uframes_t snd_cs4231_capture_pointer(snd_pcm_substream_t * substream)
1385 {
1386         cs4231_t *chip = snd_pcm_substream_chip(substream);
1387         size_t ptr;
1388 #ifdef EBUS_SUPPORT
1389         size_t residue, period_bytes;
1390 #endif
1391
1392         if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
1393                 return 0;
1394 #ifdef EBUS_SUPPORT
1395         period_bytes = snd_pcm_lib_period_bytes(substream);
1396         ptr = period_bytes * chip->c_periods_sent;
1397         if (chip->flags & CS4231_FLAG_EBUS) {
1398                 residue = ebus_dma_residue(&chip->eb2c);
1399                 ptr += period_bytes - residue;
1400         } else {
1401 #endif
1402 #ifdef SBUS_SUPPORT
1403                 ptr = sbus_dma_addr(&chip->sb2c);
1404                 if (ptr != 0)
1405                         ptr -= substream->runtime->dma_addr;
1406 #endif
1407 #ifdef EBUS_SUPPORT
1408         }
1409 #endif
1410         return bytes_to_frames(substream->runtime, ptr);
1411 }
1412
1413 /*
1414
1415  */
1416
1417 static int snd_cs4231_probe(cs4231_t *chip)
1418 {
1419         unsigned long flags;
1420         int i, id, vers;
1421         unsigned char *ptr;
1422
1423         id = vers = 0;
1424         for (i = 0; i < 50; i++) {
1425                 mb();
1426                 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
1427                         udelay(2000);
1428                 else {
1429                         spin_lock_irqsave(&chip->lock, flags);
1430                         snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
1431                         id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
1432                         vers = snd_cs4231_in(chip, CS4231_VERSION);
1433                         spin_unlock_irqrestore(&chip->lock, flags);
1434                         if (id == 0x0a)
1435                                 break;  /* this is valid value */
1436                 }
1437         }
1438         snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id);
1439         if (id != 0x0a)
1440                 return -ENODEV; /* no valid device found */
1441
1442         spin_lock_irqsave(&chip->lock, flags);
1443
1444
1445         /* Reset DMA engine.  */
1446 #ifdef EBUS_SUPPORT
1447         if (chip->flags & CS4231_FLAG_EBUS) {
1448                 /* Done by ebus_dma_register */
1449         } else {
1450 #endif
1451 #ifdef SBUS_SUPPORT
1452                 sbus_writel(APC_CHIP_RESET, chip->port + APCCSR);
1453                 sbus_writel(0x00, chip->port + APCCSR);
1454                 sbus_writel(sbus_readl(chip->port + APCCSR) | APC_CDC_RESET,
1455                             chip->port + APCCSR);
1456
1457                 udelay(20);
1458
1459                 sbus_writel(sbus_readl(chip->port + APCCSR) & ~APC_CDC_RESET,
1460                             chip->port + APCCSR);
1461                 sbus_writel(sbus_readl(chip->port + APCCSR) | (APC_XINT_ENA |
1462                                                                APC_XINT_PENA |
1463                                                                APC_XINT_CENA),
1464                             chip->port + APCCSR);
1465 #endif
1466 #ifdef EBUS_SUPPORT
1467         }
1468 #endif
1469
1470         __cs4231_readb(chip, CS4231P(chip, STATUS));    /* clear any pendings IRQ */
1471         __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));
1472         mb();
1473
1474         spin_unlock_irqrestore(&chip->lock, flags);
1475
1476         chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
1477         chip->image[CS4231_IFACE_CTRL] =
1478                 chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
1479         chip->image[CS4231_ALT_FEATURE_1] = 0x80;
1480         chip->image[CS4231_ALT_FEATURE_2] = 0x01;
1481         if (vers & 0x20)
1482                 chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
1483
1484         ptr = (unsigned char *) &chip->image;
1485
1486         snd_cs4231_mce_down(chip);
1487
1488         spin_lock_irqsave(&chip->lock, flags);
1489
1490         for (i = 0; i < 32; i++)        /* ok.. fill all CS4231 registers */
1491                 snd_cs4231_out(chip, i, *ptr++);
1492
1493         spin_unlock_irqrestore(&chip->lock, flags);
1494
1495         snd_cs4231_mce_up(chip);
1496
1497         snd_cs4231_mce_down(chip);
1498
1499         mdelay(2);
1500
1501         return 0;               /* all things are ok.. */
1502 }
1503
1504 static snd_pcm_hardware_t snd_cs4231_playback =
1505 {
1506         .info                   = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1507                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1508         .formats                = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
1509                                  SNDRV_PCM_FMTBIT_IMA_ADPCM |
1510                                  SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
1511                                  SNDRV_PCM_FMTBIT_S16_BE),
1512         .rates                  = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1513         .rate_min               = 5510,
1514         .rate_max               = 48000,
1515         .channels_min           = 1,
1516         .channels_max           = 2,
1517         .buffer_bytes_max       = (32*1024),
1518         .period_bytes_min       = 4096,
1519         .period_bytes_max       = (32*1024),
1520         .periods_min            = 1,
1521         .periods_max            = 1024,
1522 };
1523
1524 static snd_pcm_hardware_t snd_cs4231_capture =
1525 {
1526         .info                   = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1527                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1528         .formats                = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
1529                                  SNDRV_PCM_FMTBIT_IMA_ADPCM |
1530                                  SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
1531                                  SNDRV_PCM_FMTBIT_S16_BE),
1532         .rates                  = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1533         .rate_min               = 5510,
1534         .rate_max               = 48000,
1535         .channels_min           = 1,
1536         .channels_max           = 2,
1537         .buffer_bytes_max       = (32*1024),
1538         .period_bytes_min       = 4096,
1539         .period_bytes_max       = (32*1024),
1540         .periods_min            = 1,
1541         .periods_max            = 1024,
1542 };
1543
1544 static int snd_cs4231_playback_open(snd_pcm_substream_t *substream)
1545 {
1546         cs4231_t *chip = snd_pcm_substream_chip(substream);
1547         snd_pcm_runtime_t *runtime = substream->runtime;
1548         int err;
1549
1550         runtime->hw = snd_cs4231_playback;
1551
1552         if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) {
1553                 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1554                 return err;
1555         }
1556         chip->playback_substream = substream;
1557         chip->p_periods_sent = 0;
1558         snd_pcm_set_sync(substream);
1559         snd_cs4231_xrate(runtime);
1560
1561         return 0;
1562 }
1563
1564 static int snd_cs4231_capture_open(snd_pcm_substream_t *substream)
1565 {
1566         cs4231_t *chip = snd_pcm_substream_chip(substream);
1567         snd_pcm_runtime_t *runtime = substream->runtime;
1568         int err;
1569
1570         runtime->hw = snd_cs4231_capture;
1571
1572         if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) {
1573                 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1574                 return err;
1575         }
1576         chip->capture_substream = substream;
1577         chip->c_periods_sent = 0;
1578         snd_pcm_set_sync(substream);
1579         snd_cs4231_xrate(runtime);
1580
1581         return 0;
1582 }
1583
1584 static int snd_cs4231_playback_close(snd_pcm_substream_t *substream)
1585 {
1586         cs4231_t *chip = snd_pcm_substream_chip(substream);
1587
1588         chip->playback_substream = NULL;
1589         snd_cs4231_close(chip, CS4231_MODE_PLAY);
1590
1591         return 0;
1592 }
1593
1594 static int snd_cs4231_capture_close(snd_pcm_substream_t *substream)
1595 {
1596         cs4231_t *chip = snd_pcm_substream_chip(substream);
1597
1598         chip->capture_substream = NULL;
1599         snd_cs4231_close(chip, CS4231_MODE_RECORD);
1600
1601         return 0;
1602 }
1603
1604 /* XXX We can do some power-management, in particular on EBUS using
1605  * XXX the audio AUXIO register...
1606  */
1607
1608 static snd_pcm_ops_t snd_cs4231_playback_ops = {
1609         .open           =       snd_cs4231_playback_open,
1610         .close          =       snd_cs4231_playback_close,
1611         .ioctl          =       snd_pcm_lib_ioctl,
1612         .hw_params      =       snd_cs4231_playback_hw_params,
1613         .hw_free        =       snd_cs4231_playback_hw_free,
1614         .prepare        =       snd_cs4231_playback_prepare,
1615         .trigger        =       snd_cs4231_trigger,
1616         .pointer        =       snd_cs4231_playback_pointer,
1617 };
1618
1619 static snd_pcm_ops_t snd_cs4231_capture_ops = {
1620         .open           =       snd_cs4231_capture_open,
1621         .close          =       snd_cs4231_capture_close,
1622         .ioctl          =       snd_pcm_lib_ioctl,
1623         .hw_params      =       snd_cs4231_capture_hw_params,
1624         .hw_free        =       snd_cs4231_capture_hw_free,
1625         .prepare        =       snd_cs4231_capture_prepare,
1626         .trigger        =       snd_cs4231_trigger,
1627         .pointer        =       snd_cs4231_capture_pointer,
1628 };
1629
1630 static void snd_cs4231_pcm_free(snd_pcm_t *pcm)
1631 {
1632         cs4231_t *chip = pcm->private_data;
1633         chip->pcm = NULL;
1634         snd_pcm_lib_preallocate_free_for_all(pcm);
1635 }
1636
1637 int snd_cs4231_pcm(cs4231_t *chip)
1638 {
1639         snd_pcm_t *pcm;
1640         int err;
1641
1642         if ((err = snd_pcm_new(chip->card, "CS4231", 0, 1, 1, &pcm)) < 0)
1643                 return err;
1644
1645         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops);
1646         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops);
1647
1648         /* global setup */
1649         pcm->private_data = chip;
1650         pcm->private_free = snd_cs4231_pcm_free;
1651         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1652         strcpy(pcm->name, "CS4231");
1653
1654 #ifdef EBUS_SUPPORT
1655         if (chip->flags & CS4231_FLAG_EBUS) {
1656                 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1657                                                       snd_dma_pci_data(chip->dev_u.pdev),
1658                                                       64*1024, 128*1024);
1659         } else {
1660 #endif
1661 #ifdef SBUS_SUPPORT
1662                 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_SBUS,
1663                                                       snd_dma_sbus_data(chip->dev_u.sdev),
1664                                                       64*1024, 128*1024);
1665 #endif
1666 #ifdef EBUS_SUPPORT
1667         }
1668 #endif
1669
1670         chip->pcm = pcm;
1671
1672         return 0;
1673 }
1674
1675 static void snd_cs4231_timer_free(snd_timer_t *timer)
1676 {
1677         cs4231_t *chip = timer->private_data;
1678         chip->timer = NULL;
1679 }
1680
1681 int snd_cs4231_timer(cs4231_t *chip)
1682 {
1683         snd_timer_t *timer;
1684         snd_timer_id_t tid;
1685         int err;
1686
1687         /* Timer initialization */
1688         tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1689         tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
1690         tid.card = chip->card->number;
1691         tid.device = 0;
1692         tid.subdevice = 0;
1693         if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
1694                 return err;
1695         strcpy(timer->name, "CS4231");
1696         timer->private_data = chip;
1697         timer->private_free = snd_cs4231_timer_free;
1698         timer->hw = snd_cs4231_timer_table;
1699         chip->timer = timer;
1700
1701         return 0;
1702 }
1703
1704 /*
1705  *  MIXER part
1706  */
1707
1708 static int snd_cs4231_info_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1709 {
1710         static char *texts[4] = {
1711                 "Line", "CD", "Mic", "Mix"
1712         };
1713         cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1714
1715         snd_assert(chip->card != NULL, return -EINVAL);
1716         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1717         uinfo->count = 2;
1718         uinfo->value.enumerated.items = 4;
1719         if (uinfo->value.enumerated.item > 3)
1720                 uinfo->value.enumerated.item = 3;
1721         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1722
1723         return 0;
1724 }
1725
1726 static int snd_cs4231_get_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1727 {
1728         cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1729         unsigned long flags;
1730
1731         spin_lock_irqsave(&chip->lock, flags);
1732         ucontrol->value.enumerated.item[0] =
1733                 (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
1734         ucontrol->value.enumerated.item[1] =
1735                 (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
1736         spin_unlock_irqrestore(&chip->lock, flags);
1737
1738         return 0;
1739 }
1740
1741 static int snd_cs4231_put_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1742 {
1743         cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1744         unsigned long flags;
1745         unsigned short left, right;
1746         int change;
1747
1748         if (ucontrol->value.enumerated.item[0] > 3 ||
1749             ucontrol->value.enumerated.item[1] > 3)
1750                 return -EINVAL;
1751         left = ucontrol->value.enumerated.item[0] << 6;
1752         right = ucontrol->value.enumerated.item[1] << 6;
1753
1754         spin_lock_irqsave(&chip->lock, flags);
1755
1756         left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
1757         right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
1758         change = left != chip->image[CS4231_LEFT_INPUT] ||
1759                  right != chip->image[CS4231_RIGHT_INPUT];
1760         snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
1761         snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
1762
1763         spin_unlock_irqrestore(&chip->lock, flags);
1764
1765         return change;
1766 }
1767
1768 int snd_cs4231_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1769 {
1770         int mask = (kcontrol->private_value >> 16) & 0xff;
1771
1772         uinfo->type = (mask == 1) ?
1773                 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1774         uinfo->count = 1;
1775         uinfo->value.integer.min = 0;
1776         uinfo->value.integer.max = mask;
1777
1778         return 0;
1779 }
1780
1781 int snd_cs4231_get_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1782 {
1783         cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1784         unsigned long flags;
1785         int reg = kcontrol->private_value & 0xff;
1786         int shift = (kcontrol->private_value >> 8) & 0xff;
1787         int mask = (kcontrol->private_value >> 16) & 0xff;
1788         int invert = (kcontrol->private_value >> 24) & 0xff;
1789
1790         spin_lock_irqsave(&chip->lock, flags);
1791
1792         ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
1793
1794         spin_unlock_irqrestore(&chip->lock, flags);
1795
1796         if (invert)
1797                 ucontrol->value.integer.value[0] =
1798                         (mask - ucontrol->value.integer.value[0]);
1799
1800         return 0;
1801 }
1802
1803 int snd_cs4231_put_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1804 {
1805         cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1806         unsigned long flags;
1807         int reg = kcontrol->private_value & 0xff;
1808         int shift = (kcontrol->private_value >> 8) & 0xff;
1809         int mask = (kcontrol->private_value >> 16) & 0xff;
1810         int invert = (kcontrol->private_value >> 24) & 0xff;
1811         int change;
1812         unsigned short val;
1813
1814         val = (ucontrol->value.integer.value[0] & mask);
1815         if (invert)
1816                 val = mask - val;
1817         val <<= shift;
1818
1819         spin_lock_irqsave(&chip->lock, flags);
1820
1821         val = (chip->image[reg] & ~(mask << shift)) | val;
1822         change = val != chip->image[reg];
1823         snd_cs4231_out(chip, reg, val);
1824
1825         spin_unlock_irqrestore(&chip->lock, flags);
1826
1827         return change;
1828 }
1829
1830 int snd_cs4231_info_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1831 {
1832         int mask = (kcontrol->private_value >> 24) & 0xff;
1833
1834         uinfo->type = mask == 1 ?
1835                 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1836         uinfo->count = 2;
1837         uinfo->value.integer.min = 0;
1838         uinfo->value.integer.max = mask;
1839
1840         return 0;
1841 }
1842
1843 int snd_cs4231_get_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1844 {
1845         cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1846         unsigned long flags;
1847         int left_reg = kcontrol->private_value & 0xff;
1848         int right_reg = (kcontrol->private_value >> 8) & 0xff;
1849         int shift_left = (kcontrol->private_value >> 16) & 0x07;
1850         int shift_right = (kcontrol->private_value >> 19) & 0x07;
1851         int mask = (kcontrol->private_value >> 24) & 0xff;
1852         int invert = (kcontrol->private_value >> 22) & 1;
1853
1854         spin_lock_irqsave(&chip->lock, flags);
1855
1856         ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
1857         ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
1858
1859         spin_unlock_irqrestore(&chip->lock, flags);
1860
1861         if (invert) {
1862                 ucontrol->value.integer.value[0] =
1863                         (mask - ucontrol->value.integer.value[0]);
1864                 ucontrol->value.integer.value[1] =
1865                         (mask - ucontrol->value.integer.value[1]);
1866         }
1867
1868         return 0;
1869 }
1870
1871 int snd_cs4231_put_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1872 {
1873         cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1874         unsigned long flags;
1875         int left_reg = kcontrol->private_value & 0xff;
1876         int right_reg = (kcontrol->private_value >> 8) & 0xff;
1877         int shift_left = (kcontrol->private_value >> 16) & 0x07;
1878         int shift_right = (kcontrol->private_value >> 19) & 0x07;
1879         int mask = (kcontrol->private_value >> 24) & 0xff;
1880         int invert = (kcontrol->private_value >> 22) & 1;
1881         int change;
1882         unsigned short val1, val2;
1883
1884         val1 = ucontrol->value.integer.value[0] & mask;
1885         val2 = ucontrol->value.integer.value[1] & mask;
1886         if (invert) {
1887                 val1 = mask - val1;
1888                 val2 = mask - val2;
1889         }
1890         val1 <<= shift_left;
1891         val2 <<= shift_right;
1892
1893         spin_lock_irqsave(&chip->lock, flags);
1894
1895         val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
1896         val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
1897         change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
1898         snd_cs4231_out(chip, left_reg, val1);
1899         snd_cs4231_out(chip, right_reg, val2);
1900
1901         spin_unlock_irqrestore(&chip->lock, flags);
1902
1903         return change;
1904 }
1905
1906 #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
1907 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1908   .info = snd_cs4231_info_single, \
1909   .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
1910   .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
1911
1912 #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
1913 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1914   .info = snd_cs4231_info_double, \
1915   .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
1916   .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
1917
1918 static snd_kcontrol_new_t snd_cs4231_controls[] = {
1919 CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
1920 CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
1921 CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
1922 CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
1923 CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
1924 CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
1925 CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
1926 CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
1927 CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
1928 CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
1929 CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
1930 CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
1931 CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
1932 {
1933         .iface  = SNDRV_CTL_ELEM_IFACE_MIXER,
1934         .name   = "Capture Source",
1935         .info   = snd_cs4231_info_mux,
1936         .get    = snd_cs4231_get_mux,
1937         .put    = snd_cs4231_put_mux,
1938 },
1939 CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
1940 CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
1941 CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
1942 /* SPARC specific uses of XCTL{0,1} general purpose outputs.  */
1943 CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
1944 CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
1945 };
1946
1947 int snd_cs4231_mixer(cs4231_t *chip)
1948 {
1949         snd_card_t *card;
1950         int err, idx;
1951
1952         snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
1953
1954         card = chip->card;
1955
1956         strcpy(card->mixername, chip->pcm->name);
1957
1958         for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
1959                 if ((err = snd_ctl_add(card,
1960                                        snd_ctl_new1(&snd_cs4231_controls[idx],
1961                                                     chip))) < 0)
1962                         return err;
1963         }
1964         return 0;
1965 }
1966
1967 static int dev;
1968
1969 static int cs4231_attach_begin(snd_card_t **rcard)
1970 {
1971         snd_card_t *card;
1972
1973         *rcard = NULL;
1974
1975         if (dev >= SNDRV_CARDS)
1976                 return -ENODEV;
1977
1978         if (!enable[dev]) {
1979                 dev++;
1980                 return -ENOENT;
1981         }
1982
1983         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1984         if (card == NULL)
1985                 return -ENOMEM;
1986
1987         strcpy(card->driver, "CS4231");
1988         strcpy(card->shortname, "Sun CS4231");
1989
1990         *rcard = card;
1991         return 0;
1992 }
1993
1994 static int cs4231_attach_finish(snd_card_t *card, cs4231_t *chip)
1995 {
1996         int err;
1997
1998         if ((err = snd_cs4231_pcm(chip)) < 0)
1999                 goto out_err;
2000
2001         if ((err = snd_cs4231_mixer(chip)) < 0)
2002                 goto out_err;
2003
2004         if ((err = snd_cs4231_timer(chip)) < 0)
2005                 goto out_err;
2006
2007         if ((err = snd_card_set_generic_dev(card)) < 0)
2008                 goto out_err;
2009
2010         if ((err = snd_card_register(card)) < 0)
2011                 goto out_err;
2012
2013         chip->next = cs4231_list;
2014         cs4231_list = chip;
2015
2016         dev++;
2017         return 0;
2018
2019 out_err:
2020         snd_card_free(card);
2021         return err;
2022 }
2023
2024 #ifdef SBUS_SUPPORT
2025 static int snd_cs4231_sbus_free(cs4231_t *chip)
2026 {
2027         if (chip->irq[0])
2028                 free_irq(chip->irq[0], chip);
2029
2030         if (chip->port)
2031                 sbus_iounmap(chip->port, chip->regs_size);
2032
2033         if (chip->timer)
2034                 snd_device_free(chip->card, chip->timer);
2035
2036         kfree(chip);
2037
2038         return 0;
2039 }
2040
2041 static int snd_cs4231_sbus_dev_free(snd_device_t *device)
2042 {
2043         cs4231_t *cp = device->device_data;
2044
2045         return snd_cs4231_sbus_free(cp);
2046 }
2047
2048 static snd_device_ops_t snd_cs4231_sbus_dev_ops = {
2049         .dev_free       =       snd_cs4231_sbus_dev_free,
2050 };
2051
2052 static int __init snd_cs4231_sbus_create(snd_card_t *card,
2053                                          struct sbus_dev *sdev,
2054                                          int dev,
2055                                          cs4231_t **rchip)
2056 {
2057         cs4231_t *chip;
2058         int err;
2059
2060         *rchip = NULL;
2061         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2062         if (chip == NULL)
2063                 return -ENOMEM;
2064
2065         spin_lock_init(&chip->lock);
2066         spin_lock_init(&chip->sb2c.lock);
2067         spin_lock_init(&chip->sb2p.lock);
2068         init_MUTEX(&chip->mce_mutex);
2069         init_MUTEX(&chip->open_mutex);
2070         chip->card = card;
2071         chip->dev_u.sdev = sdev;
2072         chip->regs_size = sdev->reg_addrs[0].reg_size;
2073         memcpy(&chip->image, &snd_cs4231_original_image,
2074                sizeof(snd_cs4231_original_image));
2075
2076         chip->port = sbus_ioremap(&sdev->resource[0], 0,
2077                                   chip->regs_size, "cs4231");
2078         if (!chip->port) {
2079                 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
2080                 return -EIO;
2081         }
2082
2083         chip->sb2c.regs = chip->port;
2084         chip->sb2p.regs = chip->port;
2085         chip->sb2c.dir = APC_RECORD;
2086         chip->sb2p.dir = APC_PLAY;
2087
2088         if (request_irq(sdev->irqs[0], snd_cs4231_sbus_interrupt,
2089                         SA_SHIRQ, "cs4231", chip)) {
2090                 snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %s\n",
2091                            dev,
2092                            __irq_itoa(sdev->irqs[0]));
2093                 snd_cs4231_sbus_free(chip);
2094                 return -EBUSY;
2095         }
2096         chip->irq[0] = sdev->irqs[0];
2097
2098         if (snd_cs4231_probe(chip) < 0) {
2099                 snd_cs4231_sbus_free(chip);
2100                 return -ENODEV;
2101         }
2102         snd_cs4231_init(chip);
2103
2104         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
2105                                   chip, &snd_cs4231_sbus_dev_ops)) < 0) {
2106                 snd_cs4231_sbus_free(chip);
2107                 return err;
2108         }
2109
2110         *rchip = chip;
2111         return 0;
2112 }
2113
2114 static int cs4231_sbus_attach(struct sbus_dev *sdev)
2115 {
2116         struct resource *rp = &sdev->resource[0];
2117         cs4231_t *cp;
2118         snd_card_t *card;
2119         int err;
2120
2121         err = cs4231_attach_begin(&card);
2122         if (err)
2123                 return err;
2124
2125         sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %s",
2126                 card->shortname,
2127                 rp->flags & 0xffL,
2128                 rp->start,
2129                 __irq_itoa(sdev->irqs[0]));
2130
2131         if ((err = snd_cs4231_sbus_create(card, sdev, dev, &cp)) < 0) {
2132                 snd_card_free(card);
2133                 return err;
2134         }
2135
2136         return cs4231_attach_finish(card, cp);
2137 }
2138 #endif
2139
2140 #ifdef EBUS_SUPPORT
2141 static int snd_cs4231_ebus_free(cs4231_t *chip)
2142 {
2143         if (chip->eb2c.regs) {
2144                 ebus_dma_unregister(&chip->eb2c);
2145                 iounmap(chip->eb2c.regs);
2146         }
2147         if (chip->eb2p.regs) {
2148                 ebus_dma_unregister(&chip->eb2p);
2149                 iounmap(chip->eb2p.regs);
2150         }
2151
2152         if (chip->port)
2153                 iounmap(chip->port);
2154         if (chip->timer)
2155                 snd_device_free(chip->card, chip->timer);
2156
2157         kfree(chip);
2158
2159         return 0;
2160 }
2161
2162 static int snd_cs4231_ebus_dev_free(snd_device_t *device)
2163 {
2164         cs4231_t *cp = device->device_data;
2165
2166         return snd_cs4231_ebus_free(cp);
2167 }
2168
2169 static snd_device_ops_t snd_cs4231_ebus_dev_ops = {
2170         .dev_free       =       snd_cs4231_ebus_dev_free,
2171 };
2172
2173 static int __init snd_cs4231_ebus_create(snd_card_t *card,
2174                                          struct linux_ebus_device *edev,
2175                                          int dev,
2176                                          cs4231_t **rchip)
2177 {
2178         cs4231_t *chip;
2179         int err;
2180
2181         *rchip = NULL;
2182         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2183         if (chip == NULL)
2184                 return -ENOMEM;
2185
2186         spin_lock_init(&chip->lock);
2187         spin_lock_init(&chip->eb2c.lock);
2188         spin_lock_init(&chip->eb2p.lock);
2189         init_MUTEX(&chip->mce_mutex);
2190         init_MUTEX(&chip->open_mutex);
2191         chip->flags |= CS4231_FLAG_EBUS;
2192         chip->card = card;
2193         chip->dev_u.pdev = edev->bus->self;
2194         memcpy(&chip->image, &snd_cs4231_original_image,
2195                sizeof(snd_cs4231_original_image));
2196         strcpy(chip->eb2c.name, "cs4231(capture)");
2197         chip->eb2c.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
2198         chip->eb2c.callback = snd_cs4231_ebus_capture_callback;
2199         chip->eb2c.client_cookie = chip;
2200         chip->eb2c.irq = edev->irqs[0];
2201         strcpy(chip->eb2p.name, "cs4231(play)");
2202         chip->eb2p.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
2203         chip->eb2p.callback = snd_cs4231_ebus_play_callback;
2204         chip->eb2p.client_cookie = chip;
2205         chip->eb2p.irq = edev->irqs[1];
2206
2207         chip->port = ioremap(edev->resource[0].start, 0x10);
2208         chip->eb2p.regs = ioremap(edev->resource[1].start, 0x10);
2209         chip->eb2c.regs = ioremap(edev->resource[2].start, 0x10);
2210         if (!chip->port || !chip->eb2p.regs || !chip->eb2c.regs) {
2211                 snd_cs4231_ebus_free(chip);
2212                 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
2213                 return -EIO;
2214         }
2215
2216         if (ebus_dma_register(&chip->eb2c)) {
2217                 snd_cs4231_ebus_free(chip);
2218                 snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n", dev);
2219                 return -EBUSY;
2220         }
2221         if (ebus_dma_irq_enable(&chip->eb2c, 1)) {
2222                 snd_cs4231_ebus_free(chip);
2223                 snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n", dev);
2224                 return -EBUSY;
2225         }
2226
2227         if (ebus_dma_register(&chip->eb2p)) {
2228                 snd_cs4231_ebus_free(chip);
2229                 snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n", dev);
2230                 return -EBUSY;
2231         }
2232         if (ebus_dma_irq_enable(&chip->eb2p, 1)) {
2233                 snd_cs4231_ebus_free(chip);
2234                 snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
2235                 return -EBUSY;
2236         }
2237
2238         if (snd_cs4231_probe(chip) < 0) {
2239                 snd_cs4231_ebus_free(chip);
2240                 return -ENODEV;
2241         }
2242         snd_cs4231_init(chip);
2243
2244         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
2245                                   chip, &snd_cs4231_ebus_dev_ops)) < 0) {
2246                 snd_cs4231_ebus_free(chip);
2247                 return err;
2248         }
2249
2250         *rchip = chip;
2251         return 0;
2252 }
2253
2254 static int cs4231_ebus_attach(struct linux_ebus_device *edev)
2255 {
2256         snd_card_t *card;
2257         cs4231_t *chip;
2258         int err;
2259
2260         err = cs4231_attach_begin(&card);
2261         if (err)
2262                 return err;
2263
2264         sprintf(card->longname, "%s at 0x%lx, irq %s",
2265                 card->shortname,
2266                 edev->resource[0].start,
2267                 __irq_itoa(edev->irqs[0]));
2268
2269         if ((err = snd_cs4231_ebus_create(card, edev, dev, &chip)) < 0) {
2270                 snd_card_free(card);
2271                 return err;
2272         }
2273
2274         return cs4231_attach_finish(card, chip);
2275 }
2276 #endif
2277
2278 static int __init cs4231_init(void)
2279 {
2280 #ifdef SBUS_SUPPORT
2281         struct sbus_bus *sbus;
2282         struct sbus_dev *sdev;
2283 #endif
2284 #ifdef EBUS_SUPPORT
2285         struct linux_ebus *ebus;
2286         struct linux_ebus_device *edev;
2287 #endif
2288         int found;
2289
2290         found = 0;
2291
2292 #ifdef SBUS_SUPPORT
2293         for_all_sbusdev(sdev, sbus) {
2294                 if (!strcmp(sdev->prom_name, "SUNW,CS4231")) {
2295                         if (cs4231_sbus_attach(sdev) == 0)
2296                                 found++;
2297                 }
2298         }
2299 #endif
2300 #ifdef EBUS_SUPPORT
2301         for_each_ebus(ebus) {
2302                 for_each_ebusdev(edev, ebus) {
2303                         int match = 0;
2304
2305                         if (!strcmp(edev->prom_name, "SUNW,CS4231")) {
2306                                 match = 1;
2307                         } else if (!strcmp(edev->prom_name, "audio")) {
2308                                 char compat[16];
2309
2310                                 prom_getstring(edev->prom_node, "compatible",
2311                                                compat, sizeof(compat));
2312                                 compat[15] = '\0';
2313                                 if (!strcmp(compat, "SUNW,CS4231"))
2314                                         match = 1;
2315                         }
2316
2317                         if (match &&
2318                             cs4231_ebus_attach(edev) == 0)
2319                                 found++;
2320                 }
2321         }
2322 #endif
2323
2324
2325         return (found > 0) ? 0 : -EIO;
2326 }
2327
2328 static void __exit cs4231_exit(void)
2329 {
2330         cs4231_t *p = cs4231_list;
2331
2332         while (p != NULL) {
2333                 cs4231_t *next = p->next;
2334
2335                 snd_card_free(p->card);
2336
2337                 p = next;
2338         }
2339
2340         cs4231_list = NULL;
2341 }
2342
2343 module_init(cs4231_init);
2344 module_exit(cs4231_exit);