2 * Helper routines for R-Car sound ADG.
4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/clk-provider.h>
25 #define BRRx_MASK(x) (0x3FF & x)
27 static struct rsnd_mod_ops adg_ops = {
32 struct clk *clk[CLKMAX];
33 struct clk *clkout[CLKOUTMAX];
34 struct clk_onecell_data onecell;
37 int rbga_rate_for_441khz; /* RBGA */
38 int rbgb_rate_for_48khz; /* RBGB */
41 #define for_each_rsnd_clk(pos, adg, i) \
44 ((pos) = adg->clk[i]); \
46 #define for_each_rsnd_clkout(pos, adg, i) \
49 ((pos) = adg->clkout[i]); \
51 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
53 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
60 for (i = 3; i >= 0; i--) {
62 if (0 == (div % ratio))
63 return (u32)((i << 8) | ((div / ratio) - 1));
69 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
71 struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io);
72 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
73 int id = rsnd_mod_id(mod);
76 if (rsnd_ssi_is_pin_sharing(rsnd_ssi_mod_get(priv, id))) {
91 return (0x6 + ws) << 8;
94 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *mod,
95 struct rsnd_dai_stream *io)
97 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
98 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
99 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
100 int id = rsnd_mod_id(mod);
101 int shift = (id % 2) ? 16 : 0;
104 val = rsnd_adg_ssi_ws_timing_gen2(io);
107 mask = 0xffff << shift;
109 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
114 static int rsnd_adg_set_src_timsel_gen2(struct rsnd_mod *src_mod,
115 struct rsnd_dai_stream *io,
118 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
119 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
120 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
121 int is_play = rsnd_io_is_play(io);
122 int id = rsnd_mod_id(src_mod);
123 int shift = (id % 2) ? 16 : 0;
127 rsnd_mod_confirm_src(src_mod);
129 ws = rsnd_adg_ssi_ws_timing_gen2(io);
131 in = (is_play) ? timsel : ws;
132 out = (is_play) ? ws : timsel;
136 mask = 0xffff << shift;
140 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in);
141 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
144 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in);
145 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
148 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in);
149 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
152 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in);
153 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
156 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in);
157 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
164 int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *src_mod,
165 struct rsnd_dai_stream *io,
166 unsigned int src_rate,
167 unsigned int dst_rate)
169 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
170 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
171 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
172 struct device *dev = rsnd_priv_to_dev(priv);
173 int idx, sel, div, step, ret;
175 unsigned int min, diff;
176 unsigned int sel_rate [] = {
177 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
178 clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
179 clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
180 adg->rbga_rate_for_441khz, /* 0011: RBGA */
181 adg->rbgb_rate_for_48khz, /* 0100: RBGB */
184 rsnd_mod_confirm_src(src_mod);
189 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
196 for (div = 2; div <= 98304; div += step) {
197 diff = abs(src_rate - sel_rate[sel] / div);
199 val = (sel << 8) | idx;
201 en = 1 << (sel + 1); /* fixme */
205 * step of 0_0000 / 0_0001 / 0_1101
208 if ((idx > 2) && (idx % 2))
219 dev_err(dev, "no Input clock\n");
223 ret = rsnd_adg_set_src_timsel_gen2(src_mod, io, val);
225 dev_err(dev, "timsel error\n");
229 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
231 dev_dbg(dev, "convert rate %d <-> %d\n", src_rate, dst_rate);
236 int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *src_mod,
237 struct rsnd_dai_stream *io)
239 u32 val = rsnd_adg_ssi_ws_timing_gen2(io);
241 rsnd_mod_confirm_src(src_mod);
243 return rsnd_adg_set_src_timsel_gen2(src_mod, io, val);
246 int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
247 struct rsnd_mod *mod,
248 unsigned int src_rate,
249 unsigned int dst_rate)
251 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
252 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
253 struct device *dev = rsnd_priv_to_dev(priv);
254 int idx, sel, div, shift;
256 int id = rsnd_mod_id(mod);
257 unsigned int sel_rate [] = {
258 clk_get_rate(adg->clk[CLKA]), /* 000: CLKA */
259 clk_get_rate(adg->clk[CLKB]), /* 001: CLKB */
260 clk_get_rate(adg->clk[CLKC]), /* 010: CLKC */
261 0, /* 011: MLBCLK (not used) */
262 adg->rbga_rate_for_441khz, /* 100: RBGA */
263 adg->rbgb_rate_for_48khz, /* 101: RBGB */
266 /* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */
267 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
268 for (div = 128, idx = 0;
271 if (src_rate == sel_rate[sel] / div) {
272 val = (idx << 4) | sel;
277 dev_err(dev, "can't find convert src clk\n");
281 shift = (id % 4) * 8;
282 mask = 0xFF << shift;
285 dev_dbg(dev, "adg convert src clk = %02x\n", val);
289 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL3, mask, val);
292 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL4, mask, val);
295 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL5, mask, val);
300 * Gen1 doesn't need dst_rate settings,
301 * since it uses SSI WS pin.
302 * see also rsnd_src_set_route_if_gen1()
308 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
310 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
311 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
312 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
313 int id = rsnd_mod_id(ssi_mod);
314 int shift = (id % 4) * 8;
315 u32 mask = 0xFF << shift;
317 rsnd_mod_confirm_ssi(ssi_mod);
322 * SSI 8 is not connected to ADG.
323 * it works with SSI 7
330 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
333 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
336 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
341 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
344 * "mod" = "ssi" here.
345 * we can get "ssi id" from mod
347 rsnd_adg_set_ssi_clk(mod, 0);
352 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
354 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
355 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
356 struct device *dev = rsnd_priv_to_dev(priv);
367 dev_dbg(dev, "request clock = %d\n", rate);
370 * find suitable clock from
371 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
374 for_each_rsnd_clk(clk, adg, i) {
375 if (rate == clk_get_rate(clk)) {
382 * find divided clock from BRGA/BRGB
384 if (rate == adg->rbga_rate_for_441khz) {
389 if (rate == adg->rbgb_rate_for_48khz) {
399 * This "mod" = "ssi" here.
400 * we can get "ssi id" from mod
402 rsnd_adg_set_ssi_clk(mod, data);
404 dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
405 rsnd_mod_name(mod), rsnd_mod_id(mod),
411 static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
412 struct rsnd_adg *adg)
414 struct device *dev = rsnd_priv_to_dev(priv);
416 static const char * const clk_name[] = {
424 for (i = 0; i < CLKMAX; i++) {
425 clk = devm_clk_get(dev, clk_name[i]);
426 adg->clk[i] = IS_ERR(clk) ? NULL : clk;
429 for_each_rsnd_clk(clk, adg, i)
430 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
433 static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
434 struct rsnd_adg *adg)
437 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
438 struct device *dev = rsnd_priv_to_dev(priv);
439 struct device_node *np = dev->of_node;
440 u32 ckr, rbgx, rbga, rbgb;
441 u32 rate, req_rate, div;
443 unsigned long req_48kHz_rate, req_441kHz_rate;
445 const char *parent_clk_name = NULL;
446 static const char * const clkout_name[] = {
447 [CLKOUT] = "audio_clkout",
448 [CLKOUT1] = "audio_clkout1",
449 [CLKOUT2] = "audio_clkout2",
450 [CLKOUT3] = "audio_clkout3",
459 of_property_read_u32(np, "#clock-cells", &count);
462 * ADG supports BRRA/BRRB output only
463 * this means all clkout0/1/2/3 will be same rate
465 of_property_read_u32(np, "clock-frequency", &req_rate);
468 if (0 == (req_rate % 44100))
469 req_441kHz_rate = req_rate;
470 if (0 == (req_rate % 48000))
471 req_48kHz_rate = req_rate;
474 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
475 * have 44.1kHz or 48kHz base clocks for now.
477 * SSI itself can divide parent clock by 1/1 - 1/16
479 * rsnd_adg_ssi_clk_try_start()
480 * rsnd_ssi_master_clk_start()
483 rbga = 2; /* default 1/6 */
484 rbgb = 2; /* default 1/6 */
485 adg->rbga_rate_for_441khz = 0;
486 adg->rbgb_rate_for_48khz = 0;
487 for_each_rsnd_clk(clk, adg, i) {
488 rate = clk_get_rate(clk);
490 if (0 == rate) /* not used */
494 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
497 div = rate / req_441kHz_rate;
498 rbgx = rsnd_adg_calculate_rbgx(div);
499 if (BRRx_MASK(rbgx) == rbgx) {
501 adg->rbga_rate_for_441khz = rate / div;
502 ckr |= brg_table[i] << 20;
504 parent_clk_name = __clk_get_name(clk);
509 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
512 div = rate / req_48kHz_rate;
513 rbgx = rsnd_adg_calculate_rbgx(div);
514 if (BRRx_MASK(rbgx) == rbgx) {
516 adg->rbgb_rate_for_48khz = rate / div;
517 ckr |= brg_table[i] << 16;
518 if (req_48kHz_rate) {
519 parent_clk_name = __clk_get_name(clk);
527 * ADG supports BRRA/BRRB output only.
528 * this means all clkout0/1/2/3 will be * same rate
535 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
538 0 : CLK_IS_ROOT, req_rate);
540 adg->clkout[CLKOUT] = clk;
541 of_clk_add_provider(np, of_clk_src_simple_get, clk);
548 for (i = 0; i < CLKOUTMAX; i++) {
549 clk = clk_register_fixed_rate(dev, clkout_name[i],
555 adg->onecell.clks = adg->clkout;
556 adg->onecell.clk_num = CLKOUTMAX;
558 adg->clkout[i] = clk;
560 of_clk_add_provider(np, of_clk_src_onecell_get,
566 rsnd_mod_bset(adg_mod, SSICKR, 0x00FF0000, ckr);
567 rsnd_mod_write(adg_mod, BRRA, rbga);
568 rsnd_mod_write(adg_mod, BRRB, rbgb);
570 for_each_rsnd_clkout(clk, adg, i)
571 dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
572 dev_dbg(dev, "SSICKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
576 int rsnd_adg_probe(struct platform_device *pdev,
577 const struct rsnd_of_data *of_data,
578 struct rsnd_priv *priv)
580 struct rsnd_adg *adg;
581 struct device *dev = rsnd_priv_to_dev(priv);
583 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
585 dev_err(dev, "ADG allocate failed\n");
590 * ADG is special module.
591 * Use ADG mod without rsnd_mod_init() to make debug easy
592 * for rsnd_write/rsnd_read
594 adg->mod.ops = &adg_ops;
595 adg->mod.priv = priv;
597 rsnd_adg_get_clkin(priv, adg);
598 rsnd_adg_get_clkout(priv, adg);