2 * Helper routines for R-Car sound ADG.
4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/sh_clk.h>
20 struct clk *clk[CLKMAX];
22 int rbga_rate_for_441khz_div_6; /* RBGA */
23 int rbgb_rate_for_48khz_div_6; /* RBGB */
27 #define for_each_rsnd_clk(pos, adg, i) \
30 ((pos) = adg->clk[i]); \
32 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
35 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
37 struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io);
38 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
39 int id = rsnd_mod_id(mod);
42 if (rsnd_ssi_is_pin_sharing(rsnd_ssi_mod_get(priv, id))) {
57 return (0x6 + ws) << 8;
60 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *mod,
61 struct rsnd_dai_stream *io)
63 int id = rsnd_mod_id(mod);
64 int shift = (id % 2) ? 16 : 0;
67 val = rsnd_adg_ssi_ws_timing_gen2(io);
70 mask = 0xffff << shift;
72 rsnd_mod_bset(mod, CMDOUT_TIMSEL, mask, val);
77 static int rsnd_adg_set_src_timsel_gen2(struct rsnd_mod *mod,
78 struct rsnd_dai_stream *io,
81 int is_play = rsnd_io_is_play(io);
82 int id = rsnd_mod_id(mod);
83 int shift = (id % 2) ? 16 : 0;
87 ws = rsnd_adg_ssi_ws_timing_gen2(io);
89 in = (is_play) ? timsel : ws;
90 out = (is_play) ? ws : timsel;
94 mask = 0xffff << shift;
98 rsnd_mod_bset(mod, SRCIN_TIMSEL0, mask, in);
99 rsnd_mod_bset(mod, SRCOUT_TIMSEL0, mask, out);
102 rsnd_mod_bset(mod, SRCIN_TIMSEL1, mask, in);
103 rsnd_mod_bset(mod, SRCOUT_TIMSEL1, mask, out);
106 rsnd_mod_bset(mod, SRCIN_TIMSEL2, mask, in);
107 rsnd_mod_bset(mod, SRCOUT_TIMSEL2, mask, out);
110 rsnd_mod_bset(mod, SRCIN_TIMSEL3, mask, in);
111 rsnd_mod_bset(mod, SRCOUT_TIMSEL3, mask, out);
114 rsnd_mod_bset(mod, SRCIN_TIMSEL4, mask, in);
115 rsnd_mod_bset(mod, SRCOUT_TIMSEL4, mask, out);
122 int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
123 struct rsnd_dai_stream *io,
124 unsigned int src_rate,
125 unsigned int dst_rate)
127 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
128 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
129 struct device *dev = rsnd_priv_to_dev(priv);
130 int idx, sel, div, step, ret;
132 unsigned int min, diff;
133 unsigned int sel_rate [] = {
134 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
135 clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
136 clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
137 adg->rbga_rate_for_441khz_div_6,/* 0011: RBGA */
138 adg->rbgb_rate_for_48khz_div_6, /* 0100: RBGB */
144 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
151 for (div = 2; div <= 98304; div += step) {
152 diff = abs(src_rate - sel_rate[sel] / div);
154 val = (sel << 8) | idx;
156 en = 1 << (sel + 1); /* fixme */
160 * step of 0_0000 / 0_0001 / 0_1101
163 if ((idx > 2) && (idx % 2))
174 dev_err(dev, "no Input clock\n");
178 ret = rsnd_adg_set_src_timsel_gen2(mod, io, val);
180 dev_err(dev, "timsel error\n");
184 rsnd_mod_bset(mod, DIV_EN, en, en);
189 int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *mod,
190 struct rsnd_dai_stream *io)
192 u32 val = rsnd_adg_ssi_ws_timing_gen2(io);
194 return rsnd_adg_set_src_timsel_gen2(mod, io, val);
197 int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
198 struct rsnd_mod *mod,
199 unsigned int src_rate,
200 unsigned int dst_rate)
202 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
203 struct device *dev = rsnd_priv_to_dev(priv);
204 int idx, sel, div, shift;
206 int id = rsnd_mod_id(mod);
207 unsigned int sel_rate [] = {
208 clk_get_rate(adg->clk[CLKA]), /* 000: CLKA */
209 clk_get_rate(adg->clk[CLKB]), /* 001: CLKB */
210 clk_get_rate(adg->clk[CLKC]), /* 010: CLKC */
211 0, /* 011: MLBCLK (not used) */
212 adg->rbga_rate_for_441khz_div_6,/* 100: RBGA */
213 adg->rbgb_rate_for_48khz_div_6, /* 101: RBGB */
216 /* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */
217 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
218 for (div = 128, idx = 0;
221 if (src_rate == sel_rate[sel] / div) {
222 val = (idx << 4) | sel;
227 dev_err(dev, "can't find convert src clk\n");
231 shift = (id % 4) * 8;
232 mask = 0xFF << shift;
235 dev_dbg(dev, "adg convert src clk = %02x\n", val);
239 rsnd_mod_bset(mod, AUDIO_CLK_SEL3, mask, val);
242 rsnd_mod_bset(mod, AUDIO_CLK_SEL4, mask, val);
245 rsnd_mod_bset(mod, AUDIO_CLK_SEL5, mask, val);
250 * Gen1 doesn't need dst_rate settings,
251 * since it uses SSI WS pin.
252 * see also rsnd_src_set_route_if_gen1()
258 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *mod, u32 val)
260 int id = rsnd_mod_id(mod);
261 int shift = (id % 4) * 8;
262 u32 mask = 0xFF << shift;
267 * SSI 8 is not connected to ADG.
268 * it works with SSI 7
275 rsnd_mod_bset(mod, AUDIO_CLK_SEL0, mask, val);
278 rsnd_mod_bset(mod, AUDIO_CLK_SEL1, mask, val);
281 rsnd_mod_bset(mod, AUDIO_CLK_SEL2, mask, val);
286 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
289 * "mod" = "ssi" here.
290 * we can get "ssi id" from mod
292 rsnd_adg_set_ssi_clk(mod, 0);
297 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
299 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
300 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
301 struct device *dev = rsnd_priv_to_dev(priv);
312 dev_dbg(dev, "request clock = %d\n", rate);
315 * find suitable clock from
316 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
319 for_each_rsnd_clk(clk, adg, i) {
320 if (rate == clk_get_rate(clk)) {
327 * find 1/6 clock from BRGA/BRGB
329 if (rate == adg->rbga_rate_for_441khz_div_6) {
334 if (rate == adg->rbgb_rate_for_48khz_div_6) {
343 /* see rsnd_adg_ssi_clk_init() */
344 rsnd_mod_bset(mod, SSICKR, 0x00FF0000, adg->ckr);
345 rsnd_mod_write(mod, BRRA, 0x00000002); /* 1/6 */
346 rsnd_mod_write(mod, BRRB, 0x00000002); /* 1/6 */
349 * This "mod" = "ssi" here.
350 * we can get "ssi id" from mod
352 rsnd_adg_set_ssi_clk(mod, data);
354 dev_dbg(dev, "ADG: ssi%d selects clk%d = %d",
355 rsnd_mod_id(mod), i, rate);
360 static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
374 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
375 * have 44.1kHz or 48kHz base clocks for now.
377 * SSI itself can divide parent clock by 1/1 - 1/16
378 * So, BRGA outputs 44.1kHz base parent clock 1/32,
379 * and, BRGB outputs 48.0kHz base parent clock 1/32 here.
381 * rsnd_adg_ssi_clk_try_start()
384 adg->rbga_rate_for_441khz_div_6 = 0;
385 adg->rbgb_rate_for_48khz_div_6 = 0;
386 for_each_rsnd_clk(clk, adg, i) {
387 rate = clk_get_rate(clk);
389 if (0 == rate) /* not used */
393 if (!adg->rbga_rate_for_441khz_div_6 && (0 == rate % 44100)) {
394 adg->rbga_rate_for_441khz_div_6 = rate / 6;
395 ckr |= brg_table[i] << 20;
399 if (!adg->rbgb_rate_for_48khz_div_6 && (0 == rate % 48000)) {
400 adg->rbgb_rate_for_48khz_div_6 = rate / 6;
401 ckr |= brg_table[i] << 16;
408 int rsnd_adg_probe(struct platform_device *pdev,
409 const struct rsnd_of_data *of_data,
410 struct rsnd_priv *priv)
412 struct rsnd_adg *adg;
413 struct device *dev = rsnd_priv_to_dev(priv);
417 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
419 dev_err(dev, "ADG allocate failed\n");
423 adg->clk[CLKA] = devm_clk_get(dev, "clk_a");
424 adg->clk[CLKB] = devm_clk_get(dev, "clk_b");
425 adg->clk[CLKC] = devm_clk_get(dev, "clk_c");
426 adg->clk[CLKI] = devm_clk_get(dev, "clk_i");
428 for_each_rsnd_clk(clk, adg, i)
429 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
431 rsnd_adg_ssi_clk_init(priv, adg);
435 dev_dbg(dev, "adg probed\n");