1 /* sound/soc/rockchip/rockchip_i2s.c
3 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
5 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
6 * Author: Jianqun <jay.xu@rock-chips.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/delay.h>
15 #include <linux/of_gpio.h>
16 #include <linux/clk.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regmap.h>
19 #include <sound/pcm_params.h>
20 #include <sound/dmaengine_pcm.h>
22 #include "rockchip_i2s.h"
24 #define DRV_NAME "rockchip-i2s"
32 struct snd_dmaengine_dai_dma_data capture_dma_data;
33 struct snd_dmaengine_dai_dma_data playback_dma_data;
35 struct regmap *regmap;
38 * Used to indicate the tx/rx status.
39 * I2S controller hopes to start the tx and rx together,
40 * also to stop them when they are both try to stop.
46 static int i2s_runtime_suspend(struct device *dev)
48 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
50 clk_disable_unprepare(i2s->mclk);
55 static int i2s_runtime_resume(struct device *dev)
57 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
60 ret = clk_prepare_enable(i2s->mclk);
62 dev_err(i2s->dev, "clock enable failed %d\n", ret);
69 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
71 return snd_soc_dai_get_drvdata(dai);
74 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
80 regmap_update_bits(i2s->regmap, I2S_DMACR,
81 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
83 regmap_update_bits(i2s->regmap, I2S_XFER,
84 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
85 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
89 i2s->tx_start = false;
91 regmap_update_bits(i2s->regmap, I2S_DMACR,
92 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
95 regmap_update_bits(i2s->regmap, I2S_XFER,
101 regmap_update_bits(i2s->regmap, I2S_CLR,
102 I2S_CLR_TXC | I2S_CLR_RXC,
103 I2S_CLR_TXC | I2S_CLR_RXC);
105 regmap_read(i2s->regmap, I2S_CLR, &val);
107 /* Should wait for clear operation to finish */
109 regmap_read(i2s->regmap, I2S_CLR, &val);
112 dev_warn(i2s->dev, "fail to clear\n");
120 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
122 unsigned int val = 0;
126 regmap_update_bits(i2s->regmap, I2S_DMACR,
127 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
129 regmap_update_bits(i2s->regmap, I2S_XFER,
130 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
131 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
133 i2s->rx_start = true;
135 i2s->rx_start = false;
137 regmap_update_bits(i2s->regmap, I2S_DMACR,
138 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
140 if (!i2s->tx_start) {
141 regmap_update_bits(i2s->regmap, I2S_XFER,
147 regmap_update_bits(i2s->regmap, I2S_CLR,
148 I2S_CLR_TXC | I2S_CLR_RXC,
149 I2S_CLR_TXC | I2S_CLR_RXC);
151 regmap_read(i2s->regmap, I2S_CLR, &val);
153 /* Should wait for clear operation to finish */
155 regmap_read(i2s->regmap, I2S_CLR, &val);
158 dev_warn(i2s->dev, "fail to clear\n");
166 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
169 struct rk_i2s_dev *i2s = to_info(cpu_dai);
170 unsigned int mask = 0, val = 0;
172 mask = I2S_CKR_MSS_MASK;
173 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
174 case SND_SOC_DAIFMT_CBS_CFS:
175 /* Set source clock in Master mode */
176 val = I2S_CKR_MSS_MASTER;
178 case SND_SOC_DAIFMT_CBM_CFM:
179 val = I2S_CKR_MSS_SLAVE;
185 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
187 mask = I2S_TXCR_IBM_MASK;
188 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
189 case SND_SOC_DAIFMT_RIGHT_J:
190 val = I2S_TXCR_IBM_RSJM;
192 case SND_SOC_DAIFMT_LEFT_J:
193 val = I2S_TXCR_IBM_LSJM;
195 case SND_SOC_DAIFMT_I2S:
196 val = I2S_TXCR_IBM_NORMAL;
202 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
204 mask = I2S_RXCR_IBM_MASK;
205 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
206 case SND_SOC_DAIFMT_RIGHT_J:
207 val = I2S_RXCR_IBM_RSJM;
209 case SND_SOC_DAIFMT_LEFT_J:
210 val = I2S_RXCR_IBM_LSJM;
212 case SND_SOC_DAIFMT_I2S:
213 val = I2S_RXCR_IBM_NORMAL;
219 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
224 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
225 struct snd_pcm_hw_params *params,
226 struct snd_soc_dai *dai)
228 struct rk_i2s_dev *i2s = to_info(dai);
229 unsigned int val = 0;
231 switch (params_format(params)) {
232 case SNDRV_PCM_FORMAT_S8:
233 val |= I2S_TXCR_VDW(8);
235 case SNDRV_PCM_FORMAT_S16_LE:
236 val |= I2S_TXCR_VDW(16);
238 case SNDRV_PCM_FORMAT_S20_3LE:
239 val |= I2S_TXCR_VDW(20);
241 case SNDRV_PCM_FORMAT_S24_LE:
242 val |= I2S_TXCR_VDW(24);
248 switch (params_channels(params)) {
262 dev_err(i2s->dev, "invalid channel: %d\n",
263 params_channels(params));
267 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
268 regmap_update_bits(i2s->regmap, I2S_RXCR,
269 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
272 regmap_update_bits(i2s->regmap, I2S_TXCR,
273 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
276 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
278 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
284 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
285 int cmd, struct snd_soc_dai *dai)
287 struct rk_i2s_dev *i2s = to_info(dai);
291 case SNDRV_PCM_TRIGGER_START:
292 case SNDRV_PCM_TRIGGER_RESUME:
293 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
294 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
295 rockchip_snd_rxctrl(i2s, 1);
297 rockchip_snd_txctrl(i2s, 1);
299 case SNDRV_PCM_TRIGGER_SUSPEND:
300 case SNDRV_PCM_TRIGGER_STOP:
301 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
302 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
303 rockchip_snd_rxctrl(i2s, 0);
305 rockchip_snd_txctrl(i2s, 0);
315 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
316 unsigned int freq, int dir)
318 struct rk_i2s_dev *i2s = to_info(cpu_dai);
321 ret = clk_set_rate(i2s->mclk, freq);
323 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
328 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
330 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
332 dai->capture_dma_data = &i2s->capture_dma_data;
333 dai->playback_dma_data = &i2s->playback_dma_data;
338 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
339 .hw_params = rockchip_i2s_hw_params,
340 .set_sysclk = rockchip_i2s_set_sysclk,
341 .set_fmt = rockchip_i2s_set_fmt,
342 .trigger = rockchip_i2s_trigger,
345 static struct snd_soc_dai_driver rockchip_i2s_dai = {
346 .probe = rockchip_i2s_dai_probe,
348 .stream_name = "Playback",
351 .rates = SNDRV_PCM_RATE_8000_192000,
352 .formats = (SNDRV_PCM_FMTBIT_S8 |
353 SNDRV_PCM_FMTBIT_S16_LE |
354 SNDRV_PCM_FMTBIT_S20_3LE |
355 SNDRV_PCM_FMTBIT_S24_LE),
358 .stream_name = "Capture",
361 .rates = SNDRV_PCM_RATE_8000_192000,
362 .formats = (SNDRV_PCM_FMTBIT_S8 |
363 SNDRV_PCM_FMTBIT_S16_LE |
364 SNDRV_PCM_FMTBIT_S20_3LE |
365 SNDRV_PCM_FMTBIT_S24_LE),
367 .ops = &rockchip_i2s_dai_ops,
368 .symmetric_rates = 1,
371 static const struct snd_soc_component_driver rockchip_i2s_component = {
375 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
392 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
411 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
422 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
430 static const struct regmap_config rockchip_i2s_regmap_config = {
434 .max_register = I2S_RXDR,
435 .writeable_reg = rockchip_i2s_wr_reg,
436 .readable_reg = rockchip_i2s_rd_reg,
437 .volatile_reg = rockchip_i2s_volatile_reg,
438 .precious_reg = rockchip_i2s_precious_reg,
439 .cache_type = REGCACHE_FLAT,
442 static int rockchip_i2s_probe(struct platform_device *pdev)
444 struct device_node *node = pdev->dev.of_node;
445 struct rk_i2s_dev *i2s;
446 struct resource *res;
451 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
453 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
457 /* try to prepare related clocks */
458 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
459 if (IS_ERR(i2s->hclk)) {
460 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
461 return PTR_ERR(i2s->hclk);
463 ret = clk_prepare_enable(i2s->hclk);
465 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
469 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
470 if (IS_ERR(i2s->mclk)) {
471 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
472 return PTR_ERR(i2s->mclk);
475 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
476 regs = devm_ioremap_resource(&pdev->dev, res);
478 return PTR_ERR(regs);
480 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
481 &rockchip_i2s_regmap_config);
482 if (IS_ERR(i2s->regmap)) {
484 "Failed to initialise managed register map\n");
485 return PTR_ERR(i2s->regmap);
488 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
489 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
490 i2s->playback_dma_data.maxburst = 4;
492 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
493 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
494 i2s->capture_dma_data.maxburst = 4;
496 i2s->dev = &pdev->dev;
497 dev_set_drvdata(&pdev->dev, i2s);
499 pm_runtime_enable(&pdev->dev);
500 if (!pm_runtime_enabled(&pdev->dev)) {
501 ret = i2s_runtime_resume(&pdev->dev);
506 /* refine capture channels */
507 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
508 if (val >= 2 && val <= 8)
509 rockchip_i2s_dai.capture.channels_max = val;
511 rockchip_i2s_dai.capture.channels_max = 2;
514 ret = devm_snd_soc_register_component(&pdev->dev,
515 &rockchip_i2s_component,
516 &rockchip_i2s_dai, 1);
518 dev_err(&pdev->dev, "Could not register DAI\n");
522 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
524 dev_err(&pdev->dev, "Could not register PCM\n");
531 if (!pm_runtime_status_suspended(&pdev->dev))
532 i2s_runtime_suspend(&pdev->dev);
534 pm_runtime_disable(&pdev->dev);
539 static int rockchip_i2s_remove(struct platform_device *pdev)
541 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
543 pm_runtime_disable(&pdev->dev);
544 if (!pm_runtime_status_suspended(&pdev->dev))
545 i2s_runtime_suspend(&pdev->dev);
547 clk_disable_unprepare(i2s->mclk);
548 clk_disable_unprepare(i2s->hclk);
553 static const struct of_device_id rockchip_i2s_match[] = {
554 { .compatible = "rockchip,rk3066-i2s", },
558 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
559 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
563 static struct platform_driver rockchip_i2s_driver = {
564 .probe = rockchip_i2s_probe,
565 .remove = rockchip_i2s_remove,
568 .of_match_table = of_match_ptr(rockchip_i2s_match),
569 .pm = &rockchip_i2s_pm_ops,
572 module_platform_driver(rockchip_i2s_driver);
574 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
575 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
576 MODULE_LICENSE("GPL v2");
577 MODULE_ALIAS("platform:" DRV_NAME);
578 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);