2 * Rockchip I2S ALSA SoC Digital Audio Interface(DAI) driver
4 * Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/clk.h>
23 #include <linux/version.h>
25 #include <linux/of_gpio.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/regmap.h>
30 #include <linux/rockchip/cpu.h>
31 #include <linux/rockchip/cru.h>
32 #include <linux/rockchip/grf.h>
33 #include <linux/slab.h>
35 #include <sound/core.h>
36 #include <sound/pcm.h>
37 #include <sound/pcm_params.h>
38 #include <sound/initval.h>
39 #include <sound/soc.h>
40 #include <sound/dmaengine_pcm.h>
41 #include <linux/spinlock.h>
42 #include <linux/workqueue.h>
48 #define I2S_DEFAULT_FREQ (11289600)
49 #define I2S_DMA_BURST_SIZE (16) /* size * width: 16*4 = 64 bytes */
50 static DEFINE_SPINLOCK(lock);
52 #if defined(CONFIG_RK_HDMI) && defined(CONFIG_SND_RK_SOC_HDMI_I2S)
53 extern int snd_config_hdmi_audio(struct snd_pcm_hw_params *params);
58 struct clk *clk; /* bclk */
59 struct clk *mclk; /*mclk output only */
60 struct clk *hclk; /*ahb clk */
61 struct snd_dmaengine_dai_dma_data capture_dma_data;
62 struct snd_dmaengine_dai_dma_data playback_dma_data;
63 struct regmap *regmap;
67 struct delayed_work clk_delayed_work;
71 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
73 return snd_soc_dai_get_drvdata(dai);
76 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
82 spin_lock_irqsave(&lock, flags);
84 dev_dbg(i2s->dev, "%s: %d: on: %d\n", __func__, __LINE__, on);
87 regmap_update_bits(i2s->regmap, I2S_DMACR,
88 I2S_DMACR_TDE_MASK, I2S_DMACR_TDE_ENABLE);
90 regmap_update_bits(i2s->regmap, I2S_XFER,
91 I2S_XFER_TXS_MASK | I2S_XFER_RXS_MASK,
92 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
96 i2s->tx_start = false;
98 regmap_update_bits(i2s->regmap, I2S_DMACR,
99 I2S_DMACR_TDE_MASK, I2S_DMACR_TDE_DISABLE);
102 if (!i2s->rx_start) {
103 regmap_update_bits(i2s->regmap, I2S_XFER,
109 regmap_update_bits(i2s->regmap, I2S_CLR,
110 I2S_CLR_TXC_MASK | I2S_CLR_RXC_MASK,
111 I2S_CLR_TXC | I2S_CLR_RXC);
113 regmap_read(i2s->regmap, I2S_CLR, &val);
115 /* Should wait for clear operation to finish */
117 regmap_read(i2s->regmap, I2S_CLR, &val);
120 dev_warn(i2s->dev, "fail to clear\n");
124 dev_dbg(i2s->dev, "%s: %d: stop xfer\n",
129 spin_unlock_irqrestore(&lock, flags);
132 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
135 unsigned int val = 0;
138 spin_lock_irqsave(&lock, flags);
140 dev_dbg(i2s->dev, "%s: %d: on: %d\n", __func__, __LINE__, on);
143 regmap_update_bits(i2s->regmap, I2S_DMACR,
144 I2S_DMACR_RDE_MASK, I2S_DMACR_RDE_ENABLE);
146 regmap_update_bits(i2s->regmap, I2S_XFER,
147 I2S_XFER_TXS_MASK | I2S_XFER_RXS_MASK,
148 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
150 i2s->rx_start = true;
152 i2s->rx_start = false;
154 regmap_update_bits(i2s->regmap, I2S_DMACR,
155 I2S_DMACR_RDE_MASK, I2S_DMACR_RDE_DISABLE);
157 if (!i2s->tx_start) {
158 regmap_update_bits(i2s->regmap, I2S_XFER,
164 regmap_update_bits(i2s->regmap, I2S_CLR,
165 I2S_CLR_TXC_MASK | I2S_CLR_RXC_MASK,
166 I2S_CLR_TXC | I2S_CLR_RXC);
168 regmap_read(i2s->regmap, I2S_CLR, &val);
170 /* Should wait for clear operation to finish */
172 regmap_read(i2s->regmap, I2S_CLR, &val);
175 dev_warn(i2s->dev, "fail to clear\n");
179 dev_dbg(i2s->dev, "%s: %d: stop xfer\n",
184 spin_unlock_irqrestore(&lock, flags);
187 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
190 struct rk_i2s_dev *i2s = to_info(cpu_dai);
191 unsigned int mask = 0, val = 0;
195 spin_lock_irqsave(&lock, flags);
197 mask = I2S_CKR_MSS_MASK;
198 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
199 case SND_SOC_DAIFMT_CBS_CFS:
200 /* Codec is slave, so set cpu master */
201 val = I2S_CKR_MSS_MASTER;
203 case SND_SOC_DAIFMT_CBM_CFM:
204 /* Codec is master, so set cpu slave */
205 val = I2S_CKR_MSS_SLAVE;
212 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
214 mask = I2S_TXCR_IBM_MASK;
215 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
216 case SND_SOC_DAIFMT_RIGHT_J:
217 val = I2S_TXCR_IBM_RSJM;
219 case SND_SOC_DAIFMT_LEFT_J:
220 val = I2S_TXCR_IBM_LSJM;
222 case SND_SOC_DAIFMT_I2S:
223 val = I2S_TXCR_IBM_NORMAL;
230 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
232 mask = I2S_RXCR_IBM_MASK;
233 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
234 case SND_SOC_DAIFMT_RIGHT_J:
235 val = I2S_RXCR_IBM_RSJM;
237 case SND_SOC_DAIFMT_LEFT_J:
238 val = I2S_RXCR_IBM_LSJM;
240 case SND_SOC_DAIFMT_I2S:
241 val = I2S_RXCR_IBM_NORMAL;
248 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
252 spin_unlock_irqrestore(&lock, flags);
256 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
257 struct snd_pcm_hw_params *params,
258 struct snd_soc_dai *dai)
260 struct rk_i2s_dev *i2s = to_info(dai);
261 unsigned int val = 0;
264 spin_lock_irqsave(&lock, flags);
266 dev_dbg(i2s->dev, "%s: %d\n", __func__, __LINE__);
268 switch (params_format(params)) {
269 case SNDRV_PCM_FORMAT_S8:
270 val |= I2S_TXCR_VDW(8);
272 case SNDRV_PCM_FORMAT_S16_LE:
273 val |= I2S_TXCR_VDW(16);
275 case SNDRV_PCM_FORMAT_S20_3LE:
276 val |= I2S_TXCR_VDW(20);
278 case SNDRV_PCM_FORMAT_S24_LE:
279 case SNDRV_PCM_FORMAT_S24_3LE:
280 val |= I2S_TXCR_VDW(24);
282 case SNDRV_PCM_FORMAT_S32_LE:
283 val |= I2S_TXCR_VDW(32);
286 dev_err(i2s->dev, "invalid fmt: %d\n", params_format(params));
287 spin_unlock_irqrestore(&lock, flags);
291 switch (params_channels(params)) {
293 val |= I2S_TXCR_CHN_8;
296 val |= I2S_TXCR_CHN_6;
299 val |= I2S_TXCR_CHN_4;
302 val |= I2S_TXCR_CHN_2;
305 dev_err(i2s->dev, "invalid channel: %d\n",
306 params_channels(params));
307 spin_unlock_irqrestore(&lock, flags);
311 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
312 regmap_update_bits(i2s->regmap, I2S_TXCR,
317 regmap_update_bits(i2s->regmap, I2S_RXCR,
318 I2S_RXCR_VDW_MASK, val);
321 regmap_update_bits(i2s->regmap, I2S_DMACR,
322 I2S_DMACR_TDL_MASK | I2S_DMACR_RDL_MASK,
323 I2S_DMACR_TDL(16) | I2S_DMACR_RDL(16));
325 #if defined(CONFIG_RK_HDMI) && defined(CONFIG_SND_RK_SOC_HDMI_I2S)
326 snd_config_hdmi_audio(params);
328 spin_unlock_irqrestore(&lock, flags);
333 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
334 struct snd_soc_dai *dai)
336 struct rk_i2s_dev *i2s = to_info(dai);
340 case SNDRV_PCM_TRIGGER_START:
341 case SNDRV_PCM_TRIGGER_RESUME:
342 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
343 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
344 rockchip_snd_rxctrl(i2s, 1);
346 rockchip_snd_txctrl(i2s, 1);
348 case SNDRV_PCM_TRIGGER_SUSPEND:
349 case SNDRV_PCM_TRIGGER_STOP:
350 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
351 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
352 rockchip_snd_rxctrl(i2s, 0);
354 rockchip_snd_txctrl(i2s, 0);
364 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
365 int clk_id, unsigned int freq, int dir)
367 struct rk_i2s_dev *i2s = to_info(cpu_dai);
370 ret = clk_set_rate(i2s->clk, freq);
372 dev_err(i2s->dev, "fail set clk: freq: %d\n", freq);
377 static int rockchip_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
380 struct rk_i2s_dev *i2s = to_info(cpu_dai);
381 unsigned int val = 0;
384 spin_lock_irqsave(&lock, flags);
386 dev_dbg(i2s->dev, "%s: div_id=%d, div=%d\n", __func__, div_id, div);
389 case ROCKCHIP_DIV_BCLK:
390 val |= I2S_CKR_TSD(div);
391 val |= I2S_CKR_RSD(div);
392 regmap_update_bits(i2s->regmap, I2S_CKR,
393 I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
396 case ROCKCHIP_DIV_MCLK:
397 val |= I2S_CKR_MDIV(div);
398 regmap_update_bits(i2s->regmap, I2S_CKR,
399 I2S_CKR_MDIV_MASK, val);
402 spin_unlock_irqrestore(&lock, flags);
406 spin_unlock_irqrestore(&lock, flags);
411 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
413 struct rk_i2s_dev *i2s = to_info(dai);
415 dai->capture_dma_data = &i2s->capture_dma_data;
416 dai->playback_dma_data = &i2s->playback_dma_data;
421 static struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
422 .trigger = rockchip_i2s_trigger,
423 .hw_params = rockchip_i2s_hw_params,
424 .set_fmt = rockchip_i2s_set_fmt,
425 .set_clkdiv = rockchip_i2s_set_clkdiv,
426 .set_sysclk = rockchip_i2s_set_sysclk,
429 #define ROCKCHIP_I2S_RATES SNDRV_PCM_RATE_8000_192000
430 #define ROCKCHIP_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
431 SNDRV_PCM_FMTBIT_S20_3LE | \
432 SNDRV_PCM_FMTBIT_S24_LE | \
433 SNDRV_PCM_FORMAT_S32_LE)
435 struct snd_soc_dai_driver rockchip_i2s_dai[] = {
437 .probe = rockchip_i2s_dai_probe,
438 .name = "rockchip-i2s.0",
443 .rates = ROCKCHIP_I2S_RATES,
444 .formats = ROCKCHIP_I2S_FORMATS,
449 .rates = ROCKCHIP_I2S_RATES,
450 .formats = ROCKCHIP_I2S_FORMATS,
452 .ops = &rockchip_i2s_dai_ops,
453 .symmetric_rates = 1,
456 .probe = rockchip_i2s_dai_probe,
457 .name = "rockchip-i2s.1",
462 .rates = ROCKCHIP_I2S_RATES,
463 .formats = ROCKCHIP_I2S_FORMATS,
468 .rates = ROCKCHIP_I2S_RATES,
469 .formats = ROCKCHIP_I2S_FORMATS,
471 .ops = &rockchip_i2s_dai_ops,
472 .symmetric_rates = 1,
476 static const struct snd_soc_component_driver rockchip_i2s_component = {
477 .name = "rockchip-i2s",
481 static int i2s_runtime_suspend(struct device *dev)
483 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
485 dev_dbg(i2s->dev, "%s\n", __func__);
486 return pinctrl_pm_select_sleep_state(dev);
489 static int i2s_runtime_resume(struct device *dev)
491 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
493 dev_dbg(i2s->dev, "%s\n", __func__);
494 return pinctrl_pm_select_default_state(dev);
497 #define i2s_runtime_suspend NULL
498 #define i2s_runtime_resume NULL
502 static void set_clk_later_work(struct work_struct *work)
504 struct rk_i2s_dev *i2s = container_of(work, struct rk_i2s_dev,
505 clk_delayed_work.work);
507 clk_set_rate(i2s->clk, I2S_DEFAULT_FREQ);
508 if (!IS_ERR(i2s->mclk))
509 clk_set_rate(i2s->mclk, I2S_DEFAULT_FREQ);
513 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
530 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
549 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
560 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
568 static const struct regmap_config rockchip_i2s_regmap_config = {
572 .max_register = I2S_RXDR,
573 .writeable_reg = rockchip_i2s_wr_reg,
574 .readable_reg = rockchip_i2s_rd_reg,
575 .volatile_reg = rockchip_i2s_volatile_reg,
576 .precious_reg = rockchip_i2s_precious_reg,
577 .cache_type = REGCACHE_FLAT,
580 static int rockchip_i2s_probe(struct platform_device *pdev)
582 struct device_node *node = pdev->dev.of_node;
583 struct rk_i2s_dev *i2s;
584 struct resource *res;
588 ret = of_property_read_u32(node, "i2s-id", &pdev->id);
590 dev_err(&pdev->dev, "Property 'i2s-id' missing or invalid\n");
595 if (soc_is_rk3126b()) {
598 /* rk3126b has no i2s1 controller(i2s_8ch) */
600 pr_info("rk3126b has no i2s1 controller\n");
605 ret = of_property_read_u32(node, "sdi_source",
614 val = readl_relaxed(RK_GRF_VIRT + 0x0140);
615 val = val | 0x04000400;
616 writel_relaxed(val, RK_GRF_VIRT + 0x0140);
620 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
622 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
627 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
628 if (IS_ERR(i2s->hclk)) {
629 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
630 ret = PTR_ERR(i2s->hclk);
633 clk_prepare_enable(i2s->hclk);
636 i2s->clk = devm_clk_get(&pdev->dev, "i2s_clk");
637 if (IS_ERR(i2s->clk)) {
638 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
639 ret = PTR_ERR(i2s->clk);
643 INIT_DELAYED_WORK(&i2s->clk_delayed_work, set_clk_later_work);
644 schedule_delayed_work(&i2s->clk_delayed_work, msecs_to_jiffies(10));
646 clk_set_rate(i2s->clk, I2S_DEFAULT_FREQ);
648 clk_prepare_enable(i2s->clk);
650 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_mclk");
651 if (IS_ERR(i2s->mclk)) {
652 dev_info(&pdev->dev, "i2s%d has no mclk\n", pdev->id);
654 #ifndef CLK_SET_LATER
655 clk_set_rate(i2s->mclk, I2S_DEFAULT_FREQ);
657 clk_prepare_enable(i2s->mclk);
660 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
661 regs = devm_ioremap_resource(&pdev->dev, res);
667 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
668 &rockchip_i2s_regmap_config);
669 if (IS_ERR(i2s->regmap)) {
671 "Failed to initialise managed register map\n");
672 ret = PTR_ERR(i2s->regmap);
676 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
677 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
678 i2s->playback_dma_data.maxburst = I2S_DMA_BURST_SIZE;
680 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
681 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
682 i2s->capture_dma_data.maxburst = I2S_DMA_BURST_SIZE;
684 i2s->tx_start = false;
685 i2s->rx_start = false;
687 i2s->dev = &pdev->dev;
688 dev_set_drvdata(&pdev->dev, i2s);
690 pm_runtime_enable(&pdev->dev);
691 if (!pm_runtime_enabled(&pdev->dev)) {
692 ret = i2s_runtime_resume(&pdev->dev);
697 ret = snd_soc_register_component(&pdev->dev, &rockchip_i2s_component,
698 &rockchip_i2s_dai[pdev->id], 1);
701 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
706 ret = rockchip_pcm_platform_register(&pdev->dev);
708 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
709 goto err_unregister_component;
712 rockchip_snd_txctrl(i2s, 0);
713 rockchip_snd_rxctrl(i2s, 0);
717 err_unregister_component:
718 snd_soc_unregister_component(&pdev->dev);
720 if (!pm_runtime_status_suspended(&pdev->dev))
721 i2s_runtime_suspend(&pdev->dev);
723 pm_runtime_disable(&pdev->dev);
728 static int rockchip_i2s_remove(struct platform_device *pdev)
730 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
732 pm_runtime_disable(&pdev->dev);
733 if (!pm_runtime_status_suspended(&pdev->dev))
734 i2s_runtime_suspend(&pdev->dev);
736 if (!IS_ERR(i2s->mclk))
737 clk_disable_unprepare(i2s->mclk);
739 clk_disable_unprepare(i2s->clk);
740 clk_disable_unprepare(i2s->hclk);
741 rockchip_pcm_platform_unregister(&pdev->dev);
742 snd_soc_unregister_component(&pdev->dev);
748 static const struct of_device_id rockchip_i2s_match[] = {
749 { .compatible = "rockchip-i2s", },
752 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
755 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
756 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
760 static struct platform_driver rockchip_i2s_driver = {
761 .probe = rockchip_i2s_probe,
762 .remove = rockchip_i2s_remove,
764 .name = "rockchip-i2s",
765 .owner = THIS_MODULE,
766 .of_match_table = of_match_ptr(rockchip_i2s_match),
767 .pm = &rockchip_i2s_pm_ops,
771 static int __init rockchip_i2s_init(void)
773 return platform_driver_register(&rockchip_i2s_driver);
775 subsys_initcall_sync(rockchip_i2s_init);
777 static void __exit rockchip_i2s_exit(void)
779 platform_driver_unregister(&rockchip_i2s_driver);
781 module_exit(rockchip_i2s_exit);
783 MODULE_AUTHOR("Sugar <sugar.zhang@rock-chips.com>");
784 MODULE_DESCRIPTION("Rockchip I2S Controller Driver");
785 MODULE_LICENSE("GPL v2");