sound/soc/omap/mcbsp.c

   1 /*
   2  * sound/soc/omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
   8  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * Multichannel mode not supported.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26 #include <linux/slab.h>
  27
  28 #include <plat/mcbsp.h>
  29
  30 #include "mcbsp.h"
  31
  32 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  33 {
  34         void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
  35
  36         if (mcbsp->pdata->reg_size == 2) {
  37                 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
  38                 __raw_writew((u16)val, addr);
  39         } else {
  40                 ((u32 *)mcbsp->reg_cache)[reg] = val;
  41                 __raw_writel(val, addr);
  42         }
  43 }
  44
  45 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
  46 {
  47         void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
  48
  49         if (mcbsp->pdata->reg_size == 2) {
  50                 return !from_cache ? __raw_readw(addr) :
  51                                      ((u16 *)mcbsp->reg_cache)[reg];
  52         } else {
  53                 return !from_cache ? __raw_readl(addr) :
  54                                      ((u32 *)mcbsp->reg_cache)[reg];
  55         }
  56 }
  57
  58 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  59 {
  60         __raw_writel(val, mcbsp->st_data->io_base_st + reg);
  61 }
  62
  63 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
  64 {
  65         return __raw_readl(mcbsp->st_data->io_base_st + reg);
  66 }
  67
  68 #define MCBSP_READ(mcbsp, reg) \
  69                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
  70 #define MCBSP_WRITE(mcbsp, reg, val) \
  71                 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
  72 #define MCBSP_READ_CACHE(mcbsp, reg) \
  73                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
  74
  75 #define MCBSP_ST_READ(mcbsp, reg) \
  76                         omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
  77 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
  78                         omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
  79
  80 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
  81 {
  82         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  83         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  84                         MCBSP_READ(mcbsp, DRR2));
  85         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  86                         MCBSP_READ(mcbsp, DRR1));
  87         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
  88                         MCBSP_READ(mcbsp, DXR2));
  89         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
  90                         MCBSP_READ(mcbsp, DXR1));
  91         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
  92                         MCBSP_READ(mcbsp, SPCR2));
  93         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
  94                         MCBSP_READ(mcbsp, SPCR1));
  95         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
  96                         MCBSP_READ(mcbsp, RCR2));
  97         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
  98                         MCBSP_READ(mcbsp, RCR1));
  99         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
 100                         MCBSP_READ(mcbsp, XCR2));
 101         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
 102                         MCBSP_READ(mcbsp, XCR1));
 103         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
 104                         MCBSP_READ(mcbsp, SRGR2));
 105         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
 106                         MCBSP_READ(mcbsp, SRGR1));
 107         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
 108                         MCBSP_READ(mcbsp, PCR0));
 109         dev_dbg(mcbsp->dev, "***********************\n");
 110 }
 111
 112 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 113 {
 114         struct omap_mcbsp *mcbsp_tx = dev_id;
 115         u16 irqst_spcr2;
 116
 117         irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
 118         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 119
 120         if (irqst_spcr2 & XSYNC_ERR) {
 121                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 122                         irqst_spcr2);
 123                 /* Writing zero to XSYNC_ERR clears the IRQ */
 124                 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
 125         }
 126
 127         return IRQ_HANDLED;
 128 }
 129
 130 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 131 {
 132         struct omap_mcbsp *mcbsp_rx = dev_id;
 133         u16 irqst_spcr1;
 134
 135         irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
 136         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 137
 138         if (irqst_spcr1 & RSYNC_ERR) {
 139                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 140                         irqst_spcr1);
 141                 /* Writing zero to RSYNC_ERR clears the IRQ */
 142                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
 143         }
 144
 145         return IRQ_HANDLED;
 146 }
 147
 148 /*
 149  * omap_mcbsp_config simply write a config to the
 150  * appropriate McBSP.
 151  * You either call this function or set the McBSP registers
 152  * by yourself before calling omap_mcbsp_start().
 153  */
 154 void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
 155                        const struct omap_mcbsp_reg_cfg *config)
 156 {
 157         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 158                         mcbsp->id, mcbsp->phys_base);
 159
 160         /* We write the given config */
 161         MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
 162         MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
 163         MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
 164         MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
 165         MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
 166         MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
 167         MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
 168         MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
 169         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
 170         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
 171         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
 172         if (mcbsp->pdata->has_ccr) {
 173                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
 174                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
 175         }
 176         /* Enable wakeup behavior */
 177         if (mcbsp->pdata->has_wakeup)
 178                 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 179 }
 180
 181 /**
 182  * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
 183  * @id - mcbsp id
 184  * @stream - indicates the direction of data flow (rx or tx)
 185  *
 186  * Returns the address of mcbsp data transmit register or data receive register
 187  * to be used by DMA for transferring/receiving data based on the value of
 188  * @stream for the requested mcbsp given by @id
 189  */
 190 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
 191                                      unsigned int stream)
 192 {
 193         int data_reg;
 194
 195         if (mcbsp->pdata->reg_size == 2) {
 196                 if (stream)
 197                         data_reg = OMAP_MCBSP_REG_DRR1;
 198                 else
 199                         data_reg = OMAP_MCBSP_REG_DXR1;
 200         } else {
 201                 if (stream)
 202                         data_reg = OMAP_MCBSP_REG_DRR;
 203                 else
 204                         data_reg = OMAP_MCBSP_REG_DXR;
 205         }
 206
 207         return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
 208 }
 209
 210 static void omap_st_on(struct omap_mcbsp *mcbsp)
 211 {
 212         unsigned int w;
 213
 214         if (mcbsp->pdata->enable_st_clock)
 215                 mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
 216
 217         /* Enable McBSP Sidetone */
 218         w = MCBSP_READ(mcbsp, SSELCR);
 219         MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
 220
 221         /* Enable Sidetone from Sidetone Core */
 222         w = MCBSP_ST_READ(mcbsp, SSELCR);
 223         MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
 224 }
 225
 226 static void omap_st_off(struct omap_mcbsp *mcbsp)
 227 {
 228         unsigned int w;
 229
 230         w = MCBSP_ST_READ(mcbsp, SSELCR);
 231         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
 232
 233         w = MCBSP_READ(mcbsp, SSELCR);
 234         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 235
 236         if (mcbsp->pdata->enable_st_clock)
 237                 mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
 238 }
 239
 240 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 241 {
 242         u16 val, i;
 243
 244         val = MCBSP_ST_READ(mcbsp, SSELCR);
 245
 246         if (val & ST_COEFFWREN)
 247                 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 248
 249         MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
 250
 251         for (i = 0; i < 128; i++)
 252                 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
 253
 254         i = 0;
 255
 256         val = MCBSP_ST_READ(mcbsp, SSELCR);
 257         while (!(val & ST_COEFFWRDONE) && (++i < 1000))
 258                 val = MCBSP_ST_READ(mcbsp, SSELCR);
 259
 260         MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 261
 262         if (i == 1000)
 263                 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
 264 }
 265
 266 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 267 {
 268         u16 w;
 269         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 270
 271         w = MCBSP_ST_READ(mcbsp, SSELCR);
 272
 273         MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
 274                       ST_CH1GAIN(st_data->ch1gain));
 275 }
 276
 277 int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain)
 278 {
 279         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 280         int ret = 0;
 281
 282         if (!st_data)
 283                 return -ENOENT;
 284
 285         spin_lock_irq(&mcbsp->lock);
 286         if (channel == 0)
 287                 st_data->ch0gain = chgain;
 288         else if (channel == 1)
 289                 st_data->ch1gain = chgain;
 290         else
 291                 ret = -EINVAL;
 292
 293         if (st_data->enabled)
 294                 omap_st_chgain(mcbsp);
 295         spin_unlock_irq(&mcbsp->lock);
 296
 297         return ret;
 298 }
 299
 300 int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain)
 301 {
 302         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 303         int ret = 0;
 304
 305         if (!st_data)
 306                 return -ENOENT;
 307
 308         spin_lock_irq(&mcbsp->lock);
 309         if (channel == 0)
 310                 *chgain = st_data->ch0gain;
 311         else if (channel == 1)
 312                 *chgain = st_data->ch1gain;
 313         else
 314                 ret = -EINVAL;
 315         spin_unlock_irq(&mcbsp->lock);
 316
 317         return ret;
 318 }
 319
 320 static int omap_st_start(struct omap_mcbsp *mcbsp)
 321 {
 322         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 323
 324         if (st_data->enabled && !st_data->running) {
 325                 omap_st_fir_write(mcbsp, st_data->taps);
 326                 omap_st_chgain(mcbsp);
 327
 328                 if (!mcbsp->free) {
 329                         omap_st_on(mcbsp);
 330                         st_data->running = 1;
 331                 }
 332         }
 333
 334         return 0;
 335 }
 336
 337 int omap_st_enable(struct omap_mcbsp *mcbsp)
 338 {
 339         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 340
 341         if (!st_data)
 342                 return -ENODEV;
 343
 344         spin_lock_irq(&mcbsp->lock);
 345         st_data->enabled = 1;
 346         omap_st_start(mcbsp);
 347         spin_unlock_irq(&mcbsp->lock);
 348
 349         return 0;
 350 }
 351
 352 static int omap_st_stop(struct omap_mcbsp *mcbsp)
 353 {
 354         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 355
 356         if (st_data->running) {
 357                 if (!mcbsp->free) {
 358                         omap_st_off(mcbsp);
 359                         st_data->running = 0;
 360                 }
 361         }
 362
 363         return 0;
 364 }
 365
 366 int omap_st_disable(struct omap_mcbsp *mcbsp)
 367 {
 368         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 369         int ret = 0;
 370
 371         if (!st_data)
 372                 return -ENODEV;
 373
 374         spin_lock_irq(&mcbsp->lock);
 375         omap_st_stop(mcbsp);
 376         st_data->enabled = 0;
 377         spin_unlock_irq(&mcbsp->lock);
 378
 379         return ret;
 380 }
 381
 382 int omap_st_is_enabled(struct omap_mcbsp *mcbsp)
 383 {
 384         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 385
 386         if (!st_data)
 387                 return -ENODEV;
 388
 389         return st_data->enabled;
 390 }
 391
 392 /*
 393  * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
 394  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 395  * for the THRSH2 register.
 396  */
 397 void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
 398 {
 399         if (mcbsp->pdata->buffer_size == 0)
 400                 return;
 401
 402         if (threshold && threshold <= mcbsp->max_tx_thres)
 403                 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
 404 }
 405
 406 /*
 407  * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
 408  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 409  * for the THRSH1 register.
 410  */
 411 void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
 412 {
 413         if (mcbsp->pdata->buffer_size == 0)
 414                 return;
 415
 416         if (threshold && threshold <= mcbsp->max_rx_thres)
 417                 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
 418 }
 419
 420 /*
 421  * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
 422  */
 423 u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
 424 {
 425         u16 buffstat;
 426
 427         if (mcbsp->pdata->buffer_size == 0)
 428                 return 0;
 429
 430         /* Returns the number of free locations in the buffer */
 431         buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
 432
 433         /* Number of slots are different in McBSP ports */
 434         return mcbsp->pdata->buffer_size - buffstat;
 435 }
 436
 437 /*
 438  * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
 439  * to reach the threshold value (when the DMA will be triggered to read it)
 440  */
 441 u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
 442 {
 443         u16 buffstat, threshold;
 444
 445         if (mcbsp->pdata->buffer_size == 0)
 446                 return 0;
 447
 448         /* Returns the number of used locations in the buffer */
 449         buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
 450         /* RX threshold */
 451         threshold = MCBSP_READ(mcbsp, THRSH1);
 452
 453         /* Return the number of location till we reach the threshold limit */
 454         if (threshold <= buffstat)
 455                 return 0;
 456         else
 457                 return threshold - buffstat;
 458 }
 459
 460 int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
 461 {
 462         void *reg_cache;
 463         int err;
 464
 465         reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
 466         if (!reg_cache) {
 467                 return -ENOMEM;
 468         }
 469
 470         spin_lock(&mcbsp->lock);
 471         if (!mcbsp->free) {
 472                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 473                         mcbsp->id);
 474                 err = -EBUSY;
 475                 goto err_kfree;
 476         }
 477
 478         mcbsp->free = false;
 479         mcbsp->reg_cache = reg_cache;
 480         spin_unlock(&mcbsp->lock);
 481
 482         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 483                 mcbsp->pdata->ops->request(mcbsp->id - 1);
 484
 485         /*
 486          * Make sure that transmitter, receiver and sample-rate generator are
 487          * not running before activating IRQs.
 488          */
 489         MCBSP_WRITE(mcbsp, SPCR1, 0);
 490         MCBSP_WRITE(mcbsp, SPCR2, 0);
 491
 492         err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 493                                 0, "McBSP", (void *)mcbsp);
 494         if (err != 0) {
 495                 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 496                                 "for McBSP%d\n", mcbsp->tx_irq,
 497                                 mcbsp->id);
 498                 goto err_clk_disable;
 499         }
 500
 501         if (mcbsp->rx_irq) {
 502                 err = request_irq(mcbsp->rx_irq,
 503                                 omap_mcbsp_rx_irq_handler,
 504                                 0, "McBSP", (void *)mcbsp);
 505                 if (err != 0) {
 506                         dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 507                                         "for McBSP%d\n", mcbsp->rx_irq,
 508                                         mcbsp->id);
 509                         goto err_free_irq;
 510                 }
 511         }
 512
 513         return 0;
 514 err_free_irq:
 515         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 516 err_clk_disable:
 517         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 518                 mcbsp->pdata->ops->free(mcbsp->id - 1);
 519
 520         /* Disable wakeup behavior */
 521         if (mcbsp->pdata->has_wakeup)
 522                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 523
 524         spin_lock(&mcbsp->lock);
 525         mcbsp->free = true;
 526         mcbsp->reg_cache = NULL;
 527 err_kfree:
 528         spin_unlock(&mcbsp->lock);
 529         kfree(reg_cache);
 530
 531         return err;
 532 }
 533
 534 void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
 535 {
 536         void *reg_cache;
 537
 538         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 539                 mcbsp->pdata->ops->free(mcbsp->id - 1);
 540
 541         /* Disable wakeup behavior */
 542         if (mcbsp->pdata->has_wakeup)
 543                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 544
 545         if (mcbsp->rx_irq)
 546                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 547         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 548
 549         reg_cache = mcbsp->reg_cache;
 550
 551         /*
 552          * Select CLKS source from internal source unconditionally before
 553          * marking the McBSP port as free.
 554          * If the external clock source via MCBSP_CLKS pin has been selected the
 555          * system will refuse to enter idle if the CLKS pin source is not reset
 556          * back to internal source.
 557          */
 558         if (!cpu_class_is_omap1())
 559                 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
 560
 561         spin_lock(&mcbsp->lock);
 562         if (mcbsp->free)
 563                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
 564         else
 565                 mcbsp->free = true;
 566         mcbsp->reg_cache = NULL;
 567         spin_unlock(&mcbsp->lock);
 568
 569         if (reg_cache)
 570                 kfree(reg_cache);
 571 }
 572
 573 /*
 574  * Here we start the McBSP, by enabling transmitter, receiver or both.
 575  * If no transmitter or receiver is active prior calling, then sample-rate
 576  * generator and frame sync are started.
 577  */
 578 void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx)
 579 {
 580         int enable_srg = 0;
 581         u16 w;
 582
 583         if (mcbsp->st_data)
 584                 omap_st_start(mcbsp);
 585
 586         /* Only enable SRG, if McBSP is master */
 587         w = MCBSP_READ_CACHE(mcbsp, PCR0);
 588         if (w & (FSXM | FSRM | CLKXM | CLKRM))
 589                 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 590                                 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 591
 592         if (enable_srg) {
 593                 /* Start the sample generator */
 594                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 595                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
 596         }
 597
 598         /* Enable transmitter and receiver */
 599         tx &= 1;
 600         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 601         MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 602
 603         rx &= 1;
 604         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 605         MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 606
 607         /*
 608          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 609          * REVISIT: 100us may give enough time for two CLKSRG, however
 610          * due to some unknown PM related, clock gating etc. reason it
 611          * is now at 500us.
 612          */
 613         udelay(500);
 614
 615         if (enable_srg) {
 616                 /* Start frame sync */
 617                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 618                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 619         }
 620
 621         if (mcbsp->pdata->has_ccr) {
 622                 /* Release the transmitter and receiver */
 623                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 624                 w &= ~(tx ? XDISABLE : 0);
 625                 MCBSP_WRITE(mcbsp, XCCR, w);
 626                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 627                 w &= ~(rx ? RDISABLE : 0);
 628                 MCBSP_WRITE(mcbsp, RCCR, w);
 629         }
 630
 631         /* Dump McBSP Regs */
 632         omap_mcbsp_dump_reg(mcbsp);
 633 }
 634
 635 void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx)
 636 {
 637         int idle;
 638         u16 w;
 639
 640         /* Reset transmitter */
 641         tx &= 1;
 642         if (mcbsp->pdata->has_ccr) {
 643                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 644                 w |= (tx ? XDISABLE : 0);
 645                 MCBSP_WRITE(mcbsp, XCCR, w);
 646         }
 647         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 648         MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 649
 650         /* Reset receiver */
 651         rx &= 1;
 652         if (mcbsp->pdata->has_ccr) {
 653                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 654                 w |= (rx ? RDISABLE : 0);
 655                 MCBSP_WRITE(mcbsp, RCCR, w);
 656         }
 657         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 658         MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 659
 660         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 661                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 662
 663         if (idle) {
 664                 /* Reset the sample rate generator */
 665                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 666                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
 667         }
 668
 669         if (mcbsp->st_data)
 670                 omap_st_stop(mcbsp);
 671 }
 672
 673 int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
 674 {
 675         const char *src;
 676
 677         if (fck_src_id == MCBSP_CLKS_PAD_SRC)
 678                 src = "clks_ext";
 679         else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
 680                 src = "clks_fclk";
 681         else
 682                 return -EINVAL;
 683
 684         if (mcbsp->pdata->set_clk_src)
 685                 return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
 686         else
 687                 return -EINVAL;
 688 }
 689
 690 int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux)
 691 {
 692         const char *signal, *src;
 693
 694         if (mcbsp->pdata->mux_signal)
 695                 return -EINVAL;
 696
 697         switch (mux) {
 698         case CLKR_SRC_CLKR:
 699                 signal = "clkr";
 700                 src = "clkr";
 701                 break;
 702         case CLKR_SRC_CLKX:
 703                 signal = "clkr";
 704                 src = "clkx";
 705                 break;
 706         case FSR_SRC_FSR:
 707                 signal = "fsr";
 708                 src = "fsr";
 709                 break;
 710         case FSR_SRC_FSX:
 711                 signal = "fsr";
 712                 src = "fsx";
 713                 break;
 714         default:
 715                 return -EINVAL;
 716         }
 717
 718         return mcbsp->pdata->mux_signal(mcbsp->dev, signal, src);
 719 }
 720
 721 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
 722 #define valid_threshold(m, val)         ((val) <= max_thres(m))
 723 #define THRESHOLD_PROP_BUILDER(prop)                                    \
 724 static ssize_t prop##_show(struct device *dev,                          \
 725                         struct device_attribute *attr, char *buf)       \
 726 {                                                                       \
 727         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 728                                                                         \
 729         return sprintf(buf, "%u\n", mcbsp->prop);                       \
 730 }                                                                       \
 731                                                                         \
 732 static ssize_t prop##_store(struct device *dev,                         \
 733                                 struct device_attribute *attr,          \
 734                                 const char *buf, size_t size)           \
 735 {                                                                       \
 736         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 737         unsigned long val;                                              \
 738         int status;                                                     \
 739                                                                         \
 740         status = strict_strtoul(buf, 0, &val);                          \
 741         if (status)                                                     \
 742                 return status;                                          \
 743                                                                         \
 744         if (!valid_threshold(mcbsp, val))                               \
 745                 return -EDOM;                                           \
 746                                                                         \
 747         mcbsp->prop = val;                                              \
 748         return size;                                                    \
 749 }                                                                       \
 750                                                                         \
 751 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
 752
 753 THRESHOLD_PROP_BUILDER(max_tx_thres);
 754 THRESHOLD_PROP_BUILDER(max_rx_thres);
 755
 756 static const char *dma_op_modes[] = {
 757         "element", "threshold", "frame",
 758 };
 759
 760 static ssize_t dma_op_mode_show(struct device *dev,
 761                         struct device_attribute *attr, char *buf)
 762 {
 763         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 764         int dma_op_mode, i = 0;
 765         ssize_t len = 0;
 766         const char * const *s;
 767
 768         dma_op_mode = mcbsp->dma_op_mode;
 769
 770         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
 771                 if (dma_op_mode == i)
 772                         len += sprintf(buf + len, "[%s] ", *s);
 773                 else
 774                         len += sprintf(buf + len, "%s ", *s);
 775         }
 776         len += sprintf(buf + len, "\n");
 777
 778         return len;
 779 }
 780
 781 static ssize_t dma_op_mode_store(struct device *dev,
 782                                 struct device_attribute *attr,
 783                                 const char *buf, size_t size)
 784 {
 785         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 786         const char * const *s;
 787         int i = 0;
 788
 789         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
 790                 if (sysfs_streq(buf, *s))
 791                         break;
 792
 793         if (i == ARRAY_SIZE(dma_op_modes))
 794                 return -EINVAL;
 795
 796         spin_lock_irq(&mcbsp->lock);
 797         if (!mcbsp->free) {
 798                 size = -EBUSY;
 799                 goto unlock;
 800         }
 801         mcbsp->dma_op_mode = i;
 802
 803 unlock:
 804         spin_unlock_irq(&mcbsp->lock);
 805
 806         return size;
 807 }
 808
 809 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
 810
 811 static const struct attribute *additional_attrs[] = {
 812         &dev_attr_max_tx_thres.attr,
 813         &dev_attr_max_rx_thres.attr,
 814         &dev_attr_dma_op_mode.attr,
 815         NULL,
 816 };
 817
 818 static const struct attribute_group additional_attr_group = {
 819         .attrs = (struct attribute **)additional_attrs,
 820 };
 821
 822 static ssize_t st_taps_show(struct device *dev,
 823                             struct device_attribute *attr, char *buf)
 824 {
 825         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 826         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 827         ssize_t status = 0;
 828         int i;
 829
 830         spin_lock_irq(&mcbsp->lock);
 831         for (i = 0; i < st_data->nr_taps; i++)
 832                 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
 833                                   st_data->taps[i]);
 834         if (i)
 835                 status += sprintf(&buf[status], "\n");
 836         spin_unlock_irq(&mcbsp->lock);
 837
 838         return status;
 839 }
 840
 841 static ssize_t st_taps_store(struct device *dev,
 842                              struct device_attribute *attr,
 843                              const char *buf, size_t size)
 844 {
 845         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 846         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 847         int val, tmp, status, i = 0;
 848
 849         spin_lock_irq(&mcbsp->lock);
 850         memset(st_data->taps, 0, sizeof(st_data->taps));
 851         st_data->nr_taps = 0;
 852
 853         do {
 854                 status = sscanf(buf, "%d%n", &val, &tmp);
 855                 if (status < 0 || status == 0) {
 856                         size = -EINVAL;
 857                         goto out;
 858                 }
 859                 if (val < -32768 || val > 32767) {
 860                         size = -EINVAL;
 861                         goto out;
 862                 }
 863                 st_data->taps[i++] = val;
 864                 buf += tmp;
 865                 if (*buf != ',')
 866                         break;
 867                 buf++;
 868         } while (1);
 869
 870         st_data->nr_taps = i;
 871
 872 out:
 873         spin_unlock_irq(&mcbsp->lock);
 874
 875         return size;
 876 }
 877
 878 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
 879
 880 static const struct attribute *sidetone_attrs[] = {
 881         &dev_attr_st_taps.attr,
 882         NULL,
 883 };
 884
 885 static const struct attribute_group sidetone_attr_group = {
 886         .attrs = (struct attribute **)sidetone_attrs,
 887 };
 888
 889 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
 890                                  struct resource *res)
 891 {
 892         struct omap_mcbsp_st_data *st_data;
 893         int err;
 894
 895         st_data = devm_kzalloc(mcbsp->dev, sizeof(*mcbsp->st_data), GFP_KERNEL);
 896         if (!st_data)
 897                 return -ENOMEM;
 898
 899         st_data->io_base_st = devm_ioremap(mcbsp->dev, res->start,
 900                                            resource_size(res));
 901         if (!st_data->io_base_st)
 902                 return -ENOMEM;
 903
 904         err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
 905         if (err)
 906                 return err;
 907
 908         mcbsp->st_data = st_data;
 909         return 0;
 910 }
 911
 912 /*
 913  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 914  * 730 has only 2 McBSP, and both of them are MPU peripherals.
 915  */
 916 int __devinit omap_mcbsp_init(struct platform_device *pdev)
 917 {
 918         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 919         struct resource *res;
 920         int ret = 0;
 921
 922         spin_lock_init(&mcbsp->lock);
 923         mcbsp->free = true;
 924
 925         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
 926         if (!res) {
 927                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 928                 if (!res) {
 929                         dev_err(mcbsp->dev, "invalid memory resource\n");
 930                         return -ENOMEM;
 931                 }
 932         }
 933         if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
 934                                      dev_name(&pdev->dev))) {
 935                 dev_err(mcbsp->dev, "memory region already claimed\n");
 936                 return -ENODEV;
 937         }
 938
 939         mcbsp->phys_base = res->start;
 940         mcbsp->reg_cache_size = resource_size(res);
 941         mcbsp->io_base = devm_ioremap(&pdev->dev, res->start,
 942                                       resource_size(res));
 943         if (!mcbsp->io_base)
 944                 return -ENOMEM;
 945
 946         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
 947         if (!res)
 948                 mcbsp->phys_dma_base = mcbsp->phys_base;
 949         else
 950                 mcbsp->phys_dma_base = res->start;
 951
 952         mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
 953         mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
 954
 955         /* From OMAP4 there will be a single irq line */
 956         if (mcbsp->tx_irq == -ENXIO) {
 957                 mcbsp->tx_irq = platform_get_irq(pdev, 0);
 958                 mcbsp->rx_irq = 0;
 959         }
 960
 961         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
 962         if (!res) {
 963                 dev_err(&pdev->dev, "invalid rx DMA channel\n");
 964                 return -ENODEV;
 965         }
 966         /* RX DMA request number, and port address configuration */
 967         mcbsp->dma_data[1].name = "Audio Capture";
 968         mcbsp->dma_data[1].dma_req = res->start;
 969         mcbsp->dma_data[1].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 1);
 970
 971         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
 972         if (!res) {
 973                 dev_err(&pdev->dev, "invalid tx DMA channel\n");
 974                 return -ENODEV;
 975         }
 976         /* TX DMA request number, and port address configuration */
 977         mcbsp->dma_data[0].name = "Audio Playback";
 978         mcbsp->dma_data[0].dma_req = res->start;
 979         mcbsp->dma_data[0].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 0);
 980
 981         mcbsp->fclk = clk_get(&pdev->dev, "fck");
 982         if (IS_ERR(mcbsp->fclk)) {
 983                 ret = PTR_ERR(mcbsp->fclk);
 984                 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
 985                 return ret;
 986         }
 987
 988         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
 989         if (mcbsp->pdata->buffer_size) {
 990                 /*
 991                  * Initially configure the maximum thresholds to a safe value.
 992                  * The McBSP FIFO usage with these values should not go under
 993                  * 16 locations.
 994                  * If the whole FIFO without safety buffer is used, than there
 995                  * is a possibility that the DMA will be not able to push the
 996                  * new data on time, causing channel shifts in runtime.
 997                  */
 998                 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
 999                 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1000
1001                 ret = sysfs_create_group(&mcbsp->dev->kobj,
1002                                          &additional_attr_group);
1003                 if (ret) {
1004                         dev_err(mcbsp->dev,
1005                                 "Unable to create additional controls\n");
1006                         goto err_thres;
1007                 }
1008         } else {
1009                 mcbsp->max_tx_thres = -EINVAL;
1010                 mcbsp->max_rx_thres = -EINVAL;
1011         }
1012
1013         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1014         if (res) {
1015                 ret = omap_st_add(mcbsp, res);
1016                 if (ret) {
1017                         dev_err(mcbsp->dev,
1018                                 "Unable to create sidetone controls\n");
1019                         goto err_st;
1020                 }
1021         }
1022
1023         return 0;
1024
1025 err_st:
1026         if (mcbsp->pdata->buffer_size)
1027                 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1028 err_thres:
1029         clk_put(mcbsp->fclk);
1030         return ret;
1031 }
1032
1033 void __devexit omap_mcbsp_sysfs_remove(struct omap_mcbsp *mcbsp)
1034 {
1035         if (mcbsp->pdata->buffer_size)
1036                 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1037
1038         if (mcbsp->st_data)
1039                 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1040 }