2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
43 #include <linux/of_address.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_platform.h>
47 #include <sound/core.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/initval.h>
51 #include <sound/soc.h>
52 #include <sound/dmaengine_pcm.h>
58 * FSLSSI_I2S_RATES: sample rates supported by the I2S
60 * This driver currently only supports the SSI running in I2S slave mode,
61 * which means the codec determines the sample rate. Therefore, we tell
62 * ALSA that we support all rates and let the codec driver decide what rates
63 * are really supported.
65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
68 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
70 * This driver currently only supports the SSI running in I2S slave mode.
72 * The SSI has a limitation in that the samples must be in the same byte
73 * order as the host CPU. This is because when multiple bytes are written
74 * to the STX register, the bytes and bits must be written in the same
75 * order. The STX is a shift register, so all the bits need to be aligned
76 * (bit-endianness must match byte-endianness). Processors typically write
77 * the bits within a byte in the same order that the bytes of a word are
78 * written in. So if the host CPU is big-endian, then only big-endian
79 * samples will be written to STX properly.
82 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
83 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
84 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
86 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
87 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
88 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
91 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
92 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
93 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
94 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
95 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
96 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
105 struct fsl_ssi_reg_val {
112 struct fsl_ssi_rxtx_reg_val {
113 struct fsl_ssi_reg_val rx;
114 struct fsl_ssi_reg_val tx;
116 static const struct regmap_config fsl_ssi_regconfig = {
117 .max_register = CCSR_SSI_SACCDIS,
121 .val_format_endian = REGMAP_ENDIAN_NATIVE,
124 struct fsl_ssi_soc_data {
131 * fsl_ssi_private: per-SSI private data
133 * @reg: Pointer to the regmap registers
134 * @irq: IRQ of this SSI
135 * @cpu_dai_drv: CPU DAI driver for this device
137 * @dai_fmt: DAI configuration this device is currently used with
138 * @i2s_mode: i2s and network mode configuration of the device. Is used to
139 * switch between normal and i2s/network mode
140 * mode depending on the number of channels
141 * @use_dma: DMA is used or FIQ with stream filter
142 * @use_dual_fifo: DMA with support for both FIFOs used
143 * @fifo_deph: Depth of the SSI FIFOs
144 * @rxtx_reg_val: Specific register settings for receive/transmit configuration
147 * @baudclk: SSI baud clock for master mode
148 * @baudclk_streams: Active streams that are using baudclk
149 * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
151 * @dma_params_tx: DMA transmit parameters
152 * @dma_params_rx: DMA receive parameters
153 * @ssi_phys: physical address of the SSI registers
155 * @fiq_params: FIQ stream filtering parameters
157 * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
159 * @dbg_stats: Debugging statistics
161 * @soc: SoC specifc data
163 struct fsl_ssi_private {
166 struct snd_soc_dai_driver cpu_dai_drv;
168 unsigned int dai_fmt;
172 unsigned int fifo_depth;
173 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
177 unsigned int baudclk_streams;
178 unsigned int bitclk_freq;
181 struct snd_dmaengine_dai_dma_data dma_params_tx;
182 struct snd_dmaengine_dai_dma_data dma_params_rx;
185 /* params for non-dma FIQ stream filtered mode */
186 struct imx_pcm_fiq_params fiq_params;
188 /* Used when using fsl-ssi as sound-card. This is only used by ppc and
189 * should be replaced with simple-sound-card. */
190 struct platform_device *pdev;
192 struct fsl_ssi_dbg dbg_stats;
194 const struct fsl_ssi_soc_data *soc;
198 * imx51 and later SoCs have a slightly different IP that allows the
199 * SSI configuration while the SSI unit is running.
201 * More important, it is necessary on those SoCs to configure the
202 * sperate TX/RX DMA bits just before starting the stream
203 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
204 * sends any DMA requests to the SDMA unit, otherwise it is not defined
205 * how the SDMA unit handles the DMA request.
207 * SDMA units are present on devices starting at imx35 but the imx35
208 * reference manual states that the DMA bits should not be changed
209 * while the SSI unit is running (SSIEN). So we support the necessary
210 * online configuration of fsl-ssi starting at imx51.
213 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
215 .offline_config = true,
216 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
217 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
218 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
221 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
223 .offline_config = true,
224 .sisr_write_mask = 0,
227 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
229 .offline_config = true,
230 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
231 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
232 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
235 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
237 .offline_config = false,
238 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
239 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
242 static const struct of_device_id fsl_ssi_ids[] = {
243 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
244 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
245 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
246 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
249 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
251 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
253 return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97);
256 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
258 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
259 SND_SOC_DAIFMT_CBS_CFS;
263 * fsl_ssi_isr: SSI interrupt handler
265 * Although it's possible to use the interrupt handler to send and receive
266 * data to/from the SSI, we use the DMA instead. Programming is more
267 * complicated, but the performance is much better.
269 * This interrupt handler is used only to gather statistics.
271 * @irq: IRQ of the SSI device
272 * @dev_id: pointer to the ssi_private structure for this SSI device
274 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
276 struct fsl_ssi_private *ssi_private = dev_id;
277 struct regmap *regs = ssi_private->regs;
281 /* We got an interrupt, so read the status register to see what we
282 were interrupted for. We mask it with the Interrupt Enable register
283 so that we only check for events that we're interested in.
285 regmap_read(regs, CCSR_SSI_SISR, &sisr);
287 sisr2 = sisr & ssi_private->soc->sisr_write_mask;
288 /* Clear the bits that we set */
290 regmap_write(regs, CCSR_SSI_SISR, sisr2);
292 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
298 * Enable/Disable all rx/tx config flags at once.
300 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
303 struct regmap *regs = ssi_private->regs;
304 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
307 regmap_update_bits(regs, CCSR_SSI_SIER,
308 vals->rx.sier | vals->tx.sier,
309 vals->rx.sier | vals->tx.sier);
310 regmap_update_bits(regs, CCSR_SSI_SRCR,
311 vals->rx.srcr | vals->tx.srcr,
312 vals->rx.srcr | vals->tx.srcr);
313 regmap_update_bits(regs, CCSR_SSI_STCR,
314 vals->rx.stcr | vals->tx.stcr,
315 vals->rx.stcr | vals->tx.stcr);
317 regmap_update_bits(regs, CCSR_SSI_SRCR,
318 vals->rx.srcr | vals->tx.srcr, 0);
319 regmap_update_bits(regs, CCSR_SSI_STCR,
320 vals->rx.stcr | vals->tx.stcr, 0);
321 regmap_update_bits(regs, CCSR_SSI_SIER,
322 vals->rx.sier | vals->tx.sier, 0);
327 * Calculate the bits that have to be disabled for the current stream that is
328 * getting disabled. This keeps the bits enabled that are necessary for the
329 * second stream to work if 'stream_active' is true.
331 * Detailed calculation:
332 * These are the values that need to be active after disabling. For non-active
333 * second stream, this is 0:
334 * vals_stream * !!stream_active
336 * The following computes the overall differences between the setup for the
337 * to-disable stream and the active stream, a simple XOR:
338 * vals_disable ^ (vals_stream * !!(stream_active))
340 * The full expression adds a mask on all values we care about
342 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
344 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
347 * Enable/Disable a ssi configuration. You have to pass either
348 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
350 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
351 struct fsl_ssi_reg_val *vals)
353 struct regmap *regs = ssi_private->regs;
354 struct fsl_ssi_reg_val *avals;
355 int nr_active_streams;
359 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
361 nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
362 !!(scr_val & CCSR_SSI_SCR_RE);
364 if (nr_active_streams - 1 > 0)
369 /* Find the other direction values rx or tx which we do not want to
371 if (&ssi_private->rxtx_reg_val.rx == vals)
372 avals = &ssi_private->rxtx_reg_val.tx;
374 avals = &ssi_private->rxtx_reg_val.rx;
376 /* If vals should be disabled, start with disabling the unit */
378 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
380 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
384 * We are running on a SoC which does not support online SSI
385 * reconfiguration, so we have to enable all necessary flags at once
386 * even if we do not use them later (capture and playback configuration)
388 if (ssi_private->soc->offline_config) {
389 if ((enable && !nr_active_streams) ||
390 (!enable && !keep_active))
391 fsl_ssi_rxtx_config(ssi_private, enable);
397 * Configure single direction units while the SSI unit is running
398 * (online configuration)
401 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
402 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
403 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
410 * Disabling the necessary flags for one of rx/tx while the
411 * other stream is active is a little bit more difficult. We
412 * have to disable only those flags that differ between both
413 * streams (rx XOR tx) and that are set in the stream that is
414 * disabled now. Otherwise we could alter flags of the other
418 /* These assignments are simply vals without bits set in avals*/
419 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
421 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
423 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
426 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
427 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
428 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
432 /* Enabling of subunits is done after configuration */
434 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
438 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
440 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
443 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
445 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
449 * Setup rx/tx register values used to enable/disable the streams. These will
450 * be used later in fsl_ssi_config to setup the streams without the need to
451 * check for all different SSI modes.
453 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
455 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
457 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
458 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
460 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
461 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
464 if (!fsl_ssi_is_ac97(ssi_private)) {
465 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
466 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
467 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
468 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
471 if (ssi_private->use_dma) {
472 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
473 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
475 reg->rx.sier |= CCSR_SSI_SIER_RIE;
476 reg->tx.sier |= CCSR_SSI_SIER_TIE;
479 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
480 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
483 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
485 struct regmap *regs = ssi_private->regs;
488 * Setup the clock control register
490 regmap_write(regs, CCSR_SSI_STCCR,
491 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
492 regmap_write(regs, CCSR_SSI_SRCCR,
493 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
496 * Enable AC97 mode and startup the SSI
498 regmap_write(regs, CCSR_SSI_SACNT,
499 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
500 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
501 regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
504 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
505 * codec before a stream is started.
507 regmap_update_bits(regs, CCSR_SSI_SCR,
508 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
509 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
511 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
515 * fsl_ssi_startup: create a new substream
517 * This is the first function called when a stream is opened.
519 * If this is the first stream open, then grab the IRQ and program most of
522 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
523 struct snd_soc_dai *dai)
525 struct snd_soc_pcm_runtime *rtd = substream->private_data;
526 struct fsl_ssi_private *ssi_private =
527 snd_soc_dai_get_drvdata(rtd->cpu_dai);
529 /* When using dual fifo mode, it is safer to ensure an even period
530 * size. If appearing to an odd number while DMA always starts its
531 * task from fifo0, fifo1 would be neglected at the end of each
532 * period. But SSI would still access fifo1 with an invalid data.
534 if (ssi_private->use_dual_fifo)
535 snd_pcm_hw_constraint_step(substream->runtime, 0,
536 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
542 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
544 * Note: This function can be only called when using SSI as DAI master
546 * Quick instruction for parameters:
547 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
548 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
550 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
551 struct snd_soc_dai *cpu_dai,
552 struct snd_pcm_hw_params *hw_params)
554 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
555 struct regmap *regs = ssi_private->regs;
556 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
557 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
558 unsigned long clkrate, baudrate, tmprate;
559 u64 sub, savesub = 100000;
561 bool baudclk_is_used;
563 /* Prefer the explicitly set bitclock frequency */
564 if (ssi_private->bitclk_freq)
565 freq = ssi_private->bitclk_freq;
567 freq = params_channels(hw_params) * 32 * params_rate(hw_params);
569 /* Don't apply it to any non-baudclk circumstance */
570 if (IS_ERR(ssi_private->baudclk))
573 baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
575 /* It should be already enough to divide clock by setting pm alone */
579 factor = (div2 + 1) * (7 * psr + 1) * 2;
581 for (i = 0; i < 255; i++) {
582 /* The bclk rate must be smaller than 1/5 sysclk rate */
583 if (factor * (i + 1) < 5)
586 tmprate = freq * factor * (i + 2);
589 clkrate = clk_get_rate(ssi_private->baudclk);
591 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
594 afreq = clkrate / (i + 1);
598 else if (freq / afreq == 1)
600 else if (afreq / freq == 1)
605 /* Calculate the fraction */
620 /* No proper pm found if it is still remaining the initial value */
622 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
626 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
627 (psr ? CCSR_SSI_SxCCR_PSR : 0);
628 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
631 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
632 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
634 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
636 if (!baudclk_is_used) {
637 ret = clk_set_rate(ssi_private->baudclk, baudrate);
639 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
647 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
648 int clk_id, unsigned int freq, int dir)
650 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
652 ssi_private->bitclk_freq = freq;
658 * fsl_ssi_hw_params - program the sample size
660 * Most of the SSI registers have been programmed in the startup function,
661 * but the word length must be programmed here. Unfortunately, programming
662 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
663 * cause a problem with supporting simultaneous playback and capture. If
664 * the SSI is already playing a stream, then that stream may be temporarily
665 * stopped when you start capture.
667 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
670 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
671 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
673 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
674 struct regmap *regs = ssi_private->regs;
675 unsigned int channels = params_channels(hw_params);
676 unsigned int sample_size =
677 snd_pcm_format_width(params_format(hw_params));
678 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
683 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
684 enabled = scr_val & CCSR_SSI_SCR_SSIEN;
687 * If we're in synchronous mode, and the SSI is already enabled,
688 * then STCCR is already set properly.
690 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
693 if (fsl_ssi_is_i2s_master(ssi_private)) {
694 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
698 /* Do not enable the clock if it is already enabled */
699 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
700 ret = clk_prepare_enable(ssi_private->baudclk);
704 ssi_private->baudclk_streams |= BIT(substream->stream);
709 * FIXME: The documentation says that SxCCR[WL] should not be
710 * modified while the SSI is enabled. The only time this can
711 * happen is if we're trying to do simultaneous playback and
712 * capture in asynchronous mode. Unfortunately, I have been enable
713 * to get that to work at all on the P1022DS. Therefore, we don't
714 * bother to disable/enable the SSI when setting SxCCR[WL], because
715 * the SSI will stop anyway. Maybe one day, this will get fixed.
718 /* In synchronous mode, the SSI uses STCCR for capture */
719 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
720 ssi_private->cpu_dai_drv.symmetric_rates)
721 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
724 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
727 if (!fsl_ssi_is_ac97(ssi_private))
728 regmap_update_bits(regs, CCSR_SSI_SCR,
729 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
730 channels == 1 ? 0 : ssi_private->i2s_mode);
735 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
736 struct snd_soc_dai *cpu_dai)
738 struct snd_soc_pcm_runtime *rtd = substream->private_data;
739 struct fsl_ssi_private *ssi_private =
740 snd_soc_dai_get_drvdata(rtd->cpu_dai);
742 if (fsl_ssi_is_i2s_master(ssi_private) &&
743 ssi_private->baudclk_streams & BIT(substream->stream)) {
744 clk_disable_unprepare(ssi_private->baudclk);
745 ssi_private->baudclk_streams &= ~BIT(substream->stream);
751 static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private *ssi_private,
754 struct regmap *regs = ssi_private->regs;
755 u32 strcr = 0, stcr, srcr, scr, mask;
758 ssi_private->dai_fmt = fmt;
760 if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
761 dev_err(&ssi_private->pdev->dev, "baudclk is missing which is necessary for master mode\n");
765 fsl_ssi_setup_reg_vals(ssi_private);
767 regmap_read(regs, CCSR_SSI_SCR, &scr);
768 scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
769 scr |= CCSR_SSI_SCR_SYNC_TX_FS;
771 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
772 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
774 regmap_read(regs, CCSR_SSI_STCR, &stcr);
775 regmap_read(regs, CCSR_SSI_SRCR, &srcr);
779 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
780 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
781 case SND_SOC_DAIFMT_I2S:
782 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
783 case SND_SOC_DAIFMT_CBS_CFS:
784 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
785 regmap_update_bits(regs, CCSR_SSI_STCCR,
786 CCSR_SSI_SxCCR_DC_MASK,
787 CCSR_SSI_SxCCR_DC(2));
788 regmap_update_bits(regs, CCSR_SSI_SRCCR,
789 CCSR_SSI_SxCCR_DC_MASK,
790 CCSR_SSI_SxCCR_DC(2));
792 case SND_SOC_DAIFMT_CBM_CFM:
793 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
799 /* Data on rising edge of bclk, frame low, 1clk before data */
800 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
801 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
803 case SND_SOC_DAIFMT_LEFT_J:
804 /* Data on rising edge of bclk, frame high */
805 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
807 case SND_SOC_DAIFMT_DSP_A:
808 /* Data on rising edge of bclk, frame high, 1clk before data */
809 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
810 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
812 case SND_SOC_DAIFMT_DSP_B:
813 /* Data on rising edge of bclk, frame high */
814 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
815 CCSR_SSI_STCR_TXBIT0;
817 case SND_SOC_DAIFMT_AC97:
818 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
823 scr |= ssi_private->i2s_mode;
825 /* DAI clock inversion */
826 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
827 case SND_SOC_DAIFMT_NB_NF:
828 /* Nothing to do for both normal cases */
830 case SND_SOC_DAIFMT_IB_NF:
831 /* Invert bit clock */
832 strcr ^= CCSR_SSI_STCR_TSCKP;
834 case SND_SOC_DAIFMT_NB_IF:
835 /* Invert frame clock */
836 strcr ^= CCSR_SSI_STCR_TFSI;
838 case SND_SOC_DAIFMT_IB_IF:
839 /* Invert both clocks */
840 strcr ^= CCSR_SSI_STCR_TSCKP;
841 strcr ^= CCSR_SSI_STCR_TFSI;
847 /* DAI clock master masks */
848 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
849 case SND_SOC_DAIFMT_CBS_CFS:
850 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
851 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
853 case SND_SOC_DAIFMT_CBM_CFM:
854 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
863 if (ssi_private->cpu_dai_drv.symmetric_rates) {
864 /* Need to clear RXDIR when using SYNC mode */
865 srcr &= ~CCSR_SSI_SRCR_RXDIR;
866 scr |= CCSR_SSI_SCR_SYN;
869 regmap_write(regs, CCSR_SSI_STCR, stcr);
870 regmap_write(regs, CCSR_SSI_SRCR, srcr);
871 regmap_write(regs, CCSR_SSI_SCR, scr);
874 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
875 * use FIFO 1. We program the transmit water to signal a DMA transfer
876 * if there are only two (or fewer) elements left in the FIFO. Two
877 * elements equals one frame (left channel, right channel). This value,
878 * however, depends on the depth of the transmit buffer.
880 * We set the watermark on the same level as the DMA burstsize. For
881 * fiq it is probably better to use the biggest possible watermark
884 if (ssi_private->use_dma)
885 wm = ssi_private->fifo_depth - 2;
887 wm = ssi_private->fifo_depth;
889 regmap_write(regs, CCSR_SSI_SFCSR,
890 CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
891 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
893 if (ssi_private->use_dual_fifo) {
894 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
895 CCSR_SSI_SRCR_RFEN1);
896 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
897 CCSR_SSI_STCR_TFEN1);
898 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
899 CCSR_SSI_SCR_TCH_EN);
902 if (fmt & SND_SOC_DAIFMT_AC97)
903 fsl_ssi_setup_ac97(ssi_private);
910 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
912 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
914 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
916 return _fsl_ssi_set_dai_fmt(ssi_private, fmt);
920 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
922 * Note: This function can be only called when using SSI as DAI master
924 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
925 u32 rx_mask, int slots, int slot_width)
927 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
928 struct regmap *regs = ssi_private->regs;
931 /* The slot number should be >= 2 if using Network mode or I2S mode */
932 regmap_read(regs, CCSR_SSI_SCR, &val);
933 val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
934 if (val && slots < 2) {
935 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
939 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
940 CCSR_SSI_SxCCR_DC(slots));
941 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
942 CCSR_SSI_SxCCR_DC(slots));
944 /* The register SxMSKs needs SSI to provide essential clock due to
945 * hardware design. So we here temporarily enable SSI to set them.
947 regmap_read(regs, CCSR_SSI_SCR, &val);
948 val &= CCSR_SSI_SCR_SSIEN;
949 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
952 regmap_write(regs, CCSR_SSI_STMSK, tx_mask);
953 regmap_write(regs, CCSR_SSI_SRMSK, rx_mask);
955 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
961 * fsl_ssi_trigger: start and stop the DMA transfer.
963 * This function is called by ALSA to start, stop, pause, and resume the DMA
966 * The DMA channel is in external master start and pause mode, which
967 * means the SSI completely controls the flow of data.
969 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
970 struct snd_soc_dai *dai)
972 struct snd_soc_pcm_runtime *rtd = substream->private_data;
973 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
974 struct regmap *regs = ssi_private->regs;
977 case SNDRV_PCM_TRIGGER_START:
978 case SNDRV_PCM_TRIGGER_RESUME:
979 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
980 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
981 fsl_ssi_tx_config(ssi_private, true);
983 fsl_ssi_rx_config(ssi_private, true);
986 case SNDRV_PCM_TRIGGER_STOP:
987 case SNDRV_PCM_TRIGGER_SUSPEND:
988 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
989 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
990 fsl_ssi_tx_config(ssi_private, false);
992 fsl_ssi_rx_config(ssi_private, false);
999 if (fsl_ssi_is_ac97(ssi_private)) {
1000 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1001 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
1003 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
1009 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1011 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1013 if (ssi_private->soc->imx && ssi_private->use_dma) {
1014 dai->playback_dma_data = &ssi_private->dma_params_tx;
1015 dai->capture_dma_data = &ssi_private->dma_params_rx;
1021 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1022 .startup = fsl_ssi_startup,
1023 .hw_params = fsl_ssi_hw_params,
1024 .hw_free = fsl_ssi_hw_free,
1025 .set_fmt = fsl_ssi_set_dai_fmt,
1026 .set_sysclk = fsl_ssi_set_dai_sysclk,
1027 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1028 .trigger = fsl_ssi_trigger,
1031 /* Template for the CPU dai driver structure */
1032 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1033 .probe = fsl_ssi_dai_probe,
1035 .stream_name = "CPU-Playback",
1038 .rates = FSLSSI_I2S_RATES,
1039 .formats = FSLSSI_I2S_FORMATS,
1042 .stream_name = "CPU-Capture",
1045 .rates = FSLSSI_I2S_RATES,
1046 .formats = FSLSSI_I2S_FORMATS,
1048 .ops = &fsl_ssi_dai_ops,
1051 static const struct snd_soc_component_driver fsl_ssi_component = {
1055 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1058 .stream_name = "AC97 Playback",
1061 .rates = SNDRV_PCM_RATE_8000_48000,
1062 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1065 .stream_name = "AC97 Capture",
1068 .rates = SNDRV_PCM_RATE_48000,
1069 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1071 .ops = &fsl_ssi_dai_ops,
1075 static struct fsl_ssi_private *fsl_ac97_data;
1077 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1080 struct regmap *regs = fsl_ac97_data->regs;
1089 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1092 regmap_write(regs, CCSR_SSI_SACDAT, lval);
1094 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1099 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1102 struct regmap *regs = fsl_ac97_data->regs;
1104 unsigned short val = -1;
1108 lreg = (reg & 0x7f) << 12;
1109 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1110 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1115 regmap_read(regs, CCSR_SSI_SACDAT, ®_val);
1116 val = (reg_val >> 4) & 0xffff;
1121 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1122 .read = fsl_ssi_ac97_read,
1123 .write = fsl_ssi_ac97_write,
1127 * Make every character in a string lower-case
1129 static void make_lowercase(char *s)
1135 if ((c >= 'A') && (c <= 'Z'))
1136 *p = c + ('a' - 'A');
1141 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1142 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1144 struct device_node *np = pdev->dev.of_node;
1148 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1149 if (IS_ERR(ssi_private->clk)) {
1150 ret = PTR_ERR(ssi_private->clk);
1151 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1155 ret = clk_prepare_enable(ssi_private->clk);
1157 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1161 /* For those SLAVE implementations, we ingore non-baudclk cases
1162 * and, instead, abandon MASTER mode that needs baud clock.
1164 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1165 if (IS_ERR(ssi_private->baudclk))
1166 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1167 PTR_ERR(ssi_private->baudclk));
1170 * We have burstsize be "fifo_depth - 2" to match the SSI
1171 * watermark setting in fsl_ssi_startup().
1173 ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1174 ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1175 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
1176 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
1178 ret = !of_property_read_u32_array(np, "dmas", dmas, 4);
1179 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1180 ssi_private->use_dual_fifo = true;
1181 /* When using dual fifo mode, we need to keep watermark
1182 * as even numbers due to dma script limitation.
1184 ssi_private->dma_params_tx.maxburst &= ~0x1;
1185 ssi_private->dma_params_rx.maxburst &= ~0x1;
1188 if (!ssi_private->use_dma) {
1191 * Some boards use an incompatible codec. To get it
1192 * working, we are using imx-fiq-pcm-audio, that
1193 * can handle those codecs. DMA is not possible in this
1197 ssi_private->fiq_params.irq = ssi_private->irq;
1198 ssi_private->fiq_params.base = iomem;
1199 ssi_private->fiq_params.dma_params_rx =
1200 &ssi_private->dma_params_rx;
1201 ssi_private->fiq_params.dma_params_tx =
1202 &ssi_private->dma_params_tx;
1204 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1208 ret = imx_pcm_dma_init(pdev);
1216 clk_disable_unprepare(ssi_private->clk);
1221 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1222 struct fsl_ssi_private *ssi_private)
1224 if (!ssi_private->use_dma)
1225 imx_pcm_fiq_exit(pdev);
1226 clk_disable_unprepare(ssi_private->clk);
1229 static int fsl_ssi_probe(struct platform_device *pdev)
1231 struct fsl_ssi_private *ssi_private;
1233 struct device_node *np = pdev->dev.of_node;
1234 const struct of_device_id *of_id;
1235 const char *p, *sprop;
1236 const uint32_t *iprop;
1237 struct resource res;
1238 void __iomem *iomem;
1241 /* SSIs that are not connected on the board should have a
1242 * status = "disabled"
1243 * property in their device tree nodes.
1245 if (!of_device_is_available(np))
1248 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1249 if (!of_id || !of_id->data)
1252 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1255 dev_err(&pdev->dev, "could not allocate DAI object\n");
1259 ssi_private->soc = of_id->data;
1261 sprop = of_get_property(np, "fsl,mode", NULL);
1263 if (!strcmp(sprop, "ac97-slave"))
1264 ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
1265 else if (!strcmp(sprop, "i2s-slave"))
1266 ssi_private->dai_fmt = SND_SOC_DAIFMT_I2S |
1267 SND_SOC_DAIFMT_CBM_CFM;
1270 ssi_private->use_dma = !of_property_read_bool(np,
1271 "fsl,fiq-stream-filter");
1273 if (fsl_ssi_is_ac97(ssi_private)) {
1274 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1275 sizeof(fsl_ssi_ac97_dai));
1277 fsl_ac97_data = ssi_private;
1279 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1281 /* Initialize this copy of the CPU DAI driver structure */
1282 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1283 sizeof(fsl_ssi_dai_template));
1285 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1287 /* Get the addresses and IRQ */
1288 ret = of_address_to_resource(np, 0, &res);
1290 dev_err(&pdev->dev, "could not determine device resources\n");
1293 ssi_private->ssi_phys = res.start;
1295 iomem = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
1297 dev_err(&pdev->dev, "could not map device resources\n");
1301 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1302 &fsl_ssi_regconfig);
1303 if (IS_ERR(ssi_private->regs)) {
1304 dev_err(&pdev->dev, "Failed to init register map\n");
1305 return PTR_ERR(ssi_private->regs);
1308 ssi_private->irq = irq_of_parse_and_map(np, 0);
1309 if (!ssi_private->irq) {
1310 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1314 /* Are the RX and the TX clocks locked? */
1315 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1316 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1317 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1318 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1321 /* Determine the FIFO depth. */
1322 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1324 ssi_private->fifo_depth = be32_to_cpup(iprop);
1326 /* Older 8610 DTs didn't have the fifo-depth property */
1327 ssi_private->fifo_depth = 8;
1329 dev_set_drvdata(&pdev->dev, ssi_private);
1331 if (ssi_private->soc->imx) {
1332 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
1337 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1338 &ssi_private->cpu_dai_drv, 1);
1340 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1341 goto error_asoc_register;
1344 if (ssi_private->use_dma) {
1345 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1346 fsl_ssi_isr, 0, dev_name(&pdev->dev),
1349 dev_err(&pdev->dev, "could not claim irq %u\n",
1355 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1357 goto error_asoc_register;
1360 * If codec-handle property is missing from SSI node, we assume
1361 * that the machine driver uses new binding which does not require
1362 * SSI driver to trigger machine driver's probe.
1364 if (!of_get_property(np, "codec-handle", NULL))
1367 /* Trigger the machine driver's probe function. The platform driver
1368 * name of the machine driver is taken from /compatible property of the
1369 * device tree. We also pass the address of the CPU DAI driver
1372 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1373 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1374 p = strrchr(sprop, ',');
1377 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1378 make_lowercase(name);
1381 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1382 if (IS_ERR(ssi_private->pdev)) {
1383 ret = PTR_ERR(ssi_private->pdev);
1384 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1385 goto error_sound_card;
1389 if (ssi_private->dai_fmt)
1390 _fsl_ssi_set_dai_fmt(ssi_private, ssi_private->dai_fmt);
1395 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1398 snd_soc_unregister_component(&pdev->dev);
1400 error_asoc_register:
1401 if (ssi_private->soc->imx)
1402 fsl_ssi_imx_clean(pdev, ssi_private);
1405 if (ssi_private->use_dma)
1406 irq_dispose_mapping(ssi_private->irq);
1411 static int fsl_ssi_remove(struct platform_device *pdev)
1413 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1415 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1417 if (ssi_private->pdev)
1418 platform_device_unregister(ssi_private->pdev);
1419 snd_soc_unregister_component(&pdev->dev);
1421 if (ssi_private->soc->imx)
1422 fsl_ssi_imx_clean(pdev, ssi_private);
1424 if (ssi_private->use_dma)
1425 irq_dispose_mapping(ssi_private->irq);
1430 static struct platform_driver fsl_ssi_driver = {
1432 .name = "fsl-ssi-dai",
1433 .owner = THIS_MODULE,
1434 .of_match_table = fsl_ssi_ids,
1436 .probe = fsl_ssi_probe,
1437 .remove = fsl_ssi_remove,
1440 module_platform_driver(fsl_ssi_driver);
1442 MODULE_ALIAS("platform:fsl-ssi-dai");
1443 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1444 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1445 MODULE_LICENSE("GPL v2");