2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
43 #include <linux/of_address.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_platform.h>
47 #include <sound/core.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/initval.h>
51 #include <sound/soc.h>
52 #include <sound/dmaengine_pcm.h>
58 * FSLSSI_I2S_RATES: sample rates supported by the I2S
60 * This driver currently only supports the SSI running in I2S slave mode,
61 * which means the codec determines the sample rate. Therefore, we tell
62 * ALSA that we support all rates and let the codec driver decide what rates
63 * are really supported.
65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
68 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
70 * This driver currently only supports the SSI running in I2S slave mode.
72 * The SSI has a limitation in that the samples must be in the same byte
73 * order as the host CPU. This is because when multiple bytes are written
74 * to the STX register, the bytes and bits must be written in the same
75 * order. The STX is a shift register, so all the bits need to be aligned
76 * (bit-endianness must match byte-endianness). Processors typically write
77 * the bits within a byte in the same order that the bytes of a word are
78 * written in. So if the host CPU is big-endian, then only big-endian
79 * samples will be written to STX properly.
82 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
83 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
84 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
86 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
87 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
88 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
91 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
92 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
93 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
94 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
95 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
96 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
105 struct fsl_ssi_reg_val {
112 struct fsl_ssi_rxtx_reg_val {
113 struct fsl_ssi_reg_val rx;
114 struct fsl_ssi_reg_val tx;
116 static const struct regmap_config fsl_ssi_regconfig = {
117 .max_register = CCSR_SSI_SACCDIS,
121 .val_format_endian = REGMAP_ENDIAN_NATIVE,
124 struct fsl_ssi_soc_data {
131 * fsl_ssi_private: per-SSI private data
133 * @reg: Pointer to the regmap registers
134 * @irq: IRQ of this SSI
135 * @cpu_dai_drv: CPU DAI driver for this device
137 * @dai_fmt: DAI configuration this device is currently used with
138 * @i2s_mode: i2s and network mode configuration of the device. Is used to
139 * switch between normal and i2s/network mode
140 * mode depending on the number of channels
141 * @use_dma: DMA is used or FIQ with stream filter
142 * @use_dual_fifo: DMA with support for both FIFOs used
143 * @fifo_deph: Depth of the SSI FIFOs
144 * @rxtx_reg_val: Specific register settings for receive/transmit configuration
147 * @baudclk: SSI baud clock for master mode
148 * @baudclk_streams: Active streams that are using baudclk
149 * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
151 * @dma_params_tx: DMA transmit parameters
152 * @dma_params_rx: DMA receive parameters
153 * @ssi_phys: physical address of the SSI registers
155 * @fiq_params: FIQ stream filtering parameters
157 * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
159 * @dbg_stats: Debugging statistics
161 * @soc: SoC specifc data
163 struct fsl_ssi_private {
166 struct snd_soc_dai_driver cpu_dai_drv;
168 unsigned int dai_fmt;
172 unsigned int fifo_depth;
173 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
177 unsigned int baudclk_streams;
178 unsigned int bitclk_freq;
181 struct snd_dmaengine_dai_dma_data dma_params_tx;
182 struct snd_dmaengine_dai_dma_data dma_params_rx;
185 /* params for non-dma FIQ stream filtered mode */
186 struct imx_pcm_fiq_params fiq_params;
188 /* Used when using fsl-ssi as sound-card. This is only used by ppc and
189 * should be replaced with simple-sound-card. */
190 struct platform_device *pdev;
192 struct fsl_ssi_dbg dbg_stats;
194 const struct fsl_ssi_soc_data *soc;
198 * imx51 and later SoCs have a slightly different IP that allows the
199 * SSI configuration while the SSI unit is running.
201 * More important, it is necessary on those SoCs to configure the
202 * sperate TX/RX DMA bits just before starting the stream
203 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
204 * sends any DMA requests to the SDMA unit, otherwise it is not defined
205 * how the SDMA unit handles the DMA request.
207 * SDMA units are present on devices starting at imx35 but the imx35
208 * reference manual states that the DMA bits should not be changed
209 * while the SSI unit is running (SSIEN). So we support the necessary
210 * online configuration of fsl-ssi starting at imx51.
213 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
215 .offline_config = true,
216 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
217 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
218 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
221 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
223 .offline_config = true,
224 .sisr_write_mask = 0,
227 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
229 .offline_config = true,
230 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
231 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
232 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
235 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
237 .offline_config = false,
238 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
239 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
242 static const struct of_device_id fsl_ssi_ids[] = {
243 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
244 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
245 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
246 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
249 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
251 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
253 return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97);
256 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
258 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
259 SND_SOC_DAIFMT_CBS_CFS;
263 * fsl_ssi_isr: SSI interrupt handler
265 * Although it's possible to use the interrupt handler to send and receive
266 * data to/from the SSI, we use the DMA instead. Programming is more
267 * complicated, but the performance is much better.
269 * This interrupt handler is used only to gather statistics.
271 * @irq: IRQ of the SSI device
272 * @dev_id: pointer to the ssi_private structure for this SSI device
274 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
276 struct fsl_ssi_private *ssi_private = dev_id;
277 struct regmap *regs = ssi_private->regs;
281 /* We got an interrupt, so read the status register to see what we
282 were interrupted for. We mask it with the Interrupt Enable register
283 so that we only check for events that we're interested in.
285 regmap_read(regs, CCSR_SSI_SISR, &sisr);
287 sisr2 = sisr & ssi_private->soc->sisr_write_mask;
288 /* Clear the bits that we set */
290 regmap_write(regs, CCSR_SSI_SISR, sisr2);
292 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
298 * Enable/Disable all rx/tx config flags at once.
300 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
303 struct regmap *regs = ssi_private->regs;
304 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
307 regmap_update_bits(regs, CCSR_SSI_SIER,
308 vals->rx.sier | vals->tx.sier,
309 vals->rx.sier | vals->tx.sier);
310 regmap_update_bits(regs, CCSR_SSI_SRCR,
311 vals->rx.srcr | vals->tx.srcr,
312 vals->rx.srcr | vals->tx.srcr);
313 regmap_update_bits(regs, CCSR_SSI_STCR,
314 vals->rx.stcr | vals->tx.stcr,
315 vals->rx.stcr | vals->tx.stcr);
317 regmap_update_bits(regs, CCSR_SSI_SRCR,
318 vals->rx.srcr | vals->tx.srcr, 0);
319 regmap_update_bits(regs, CCSR_SSI_STCR,
320 vals->rx.stcr | vals->tx.stcr, 0);
321 regmap_update_bits(regs, CCSR_SSI_SIER,
322 vals->rx.sier | vals->tx.sier, 0);
327 * Calculate the bits that have to be disabled for the current stream that is
328 * getting disabled. This keeps the bits enabled that are necessary for the
329 * second stream to work if 'stream_active' is true.
331 * Detailed calculation:
332 * These are the values that need to be active after disabling. For non-active
333 * second stream, this is 0:
334 * vals_stream * !!stream_active
336 * The following computes the overall differences between the setup for the
337 * to-disable stream and the active stream, a simple XOR:
338 * vals_disable ^ (vals_stream * !!(stream_active))
340 * The full expression adds a mask on all values we care about
342 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
344 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
347 * Enable/Disable a ssi configuration. You have to pass either
348 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
350 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
351 struct fsl_ssi_reg_val *vals)
353 struct regmap *regs = ssi_private->regs;
354 struct fsl_ssi_reg_val *avals;
355 int nr_active_streams;
359 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
361 nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
362 !!(scr_val & CCSR_SSI_SCR_RE);
364 if (nr_active_streams - 1 > 0)
369 /* Find the other direction values rx or tx which we do not want to
371 if (&ssi_private->rxtx_reg_val.rx == vals)
372 avals = &ssi_private->rxtx_reg_val.tx;
374 avals = &ssi_private->rxtx_reg_val.rx;
376 /* If vals should be disabled, start with disabling the unit */
378 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
380 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
384 * We are running on a SoC which does not support online SSI
385 * reconfiguration, so we have to enable all necessary flags at once
386 * even if we do not use them later (capture and playback configuration)
388 if (ssi_private->soc->offline_config) {
389 if ((enable && !nr_active_streams) ||
390 (!enable && !keep_active))
391 fsl_ssi_rxtx_config(ssi_private, enable);
397 * Configure single direction units while the SSI unit is running
398 * (online configuration)
401 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
402 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
403 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
410 * Disabling the necessary flags for one of rx/tx while the
411 * other stream is active is a little bit more difficult. We
412 * have to disable only those flags that differ between both
413 * streams (rx XOR tx) and that are set in the stream that is
414 * disabled now. Otherwise we could alter flags of the other
418 /* These assignments are simply vals without bits set in avals*/
419 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
421 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
423 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
426 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
427 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
428 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
432 /* Enabling of subunits is done after configuration */
434 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
438 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
440 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
443 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
445 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
449 * Setup rx/tx register values used to enable/disable the streams. These will
450 * be used later in fsl_ssi_config to setup the streams without the need to
451 * check for all different SSI modes.
453 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
455 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
457 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
458 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
460 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
461 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
464 if (!fsl_ssi_is_ac97(ssi_private)) {
465 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
466 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
467 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
468 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
471 if (ssi_private->use_dma) {
472 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
473 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
475 reg->rx.sier |= CCSR_SSI_SIER_RIE;
476 reg->tx.sier |= CCSR_SSI_SIER_TIE;
479 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
480 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
483 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
485 struct regmap *regs = ssi_private->regs;
488 * Setup the clock control register
490 regmap_write(regs, CCSR_SSI_STCCR,
491 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
492 regmap_write(regs, CCSR_SSI_SRCCR,
493 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
496 * Enable AC97 mode and startup the SSI
498 regmap_write(regs, CCSR_SSI_SACNT,
499 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
500 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
501 regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
504 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
505 * codec before a stream is started.
507 regmap_update_bits(regs, CCSR_SSI_SCR,
508 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
509 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
511 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
515 * fsl_ssi_startup: create a new substream
517 * This is the first function called when a stream is opened.
519 * If this is the first stream open, then grab the IRQ and program most of
522 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
523 struct snd_soc_dai *dai)
525 struct snd_soc_pcm_runtime *rtd = substream->private_data;
526 struct fsl_ssi_private *ssi_private =
527 snd_soc_dai_get_drvdata(rtd->cpu_dai);
529 /* When using dual fifo mode, it is safer to ensure an even period
530 * size. If appearing to an odd number while DMA always starts its
531 * task from fifo0, fifo1 would be neglected at the end of each
532 * period. But SSI would still access fifo1 with an invalid data.
534 if (ssi_private->use_dual_fifo)
535 snd_pcm_hw_constraint_step(substream->runtime, 0,
536 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
542 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
544 * Note: This function can be only called when using SSI as DAI master
546 * Quick instruction for parameters:
547 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
548 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
550 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
551 struct snd_soc_dai *cpu_dai,
552 struct snd_pcm_hw_params *hw_params)
554 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
555 struct regmap *regs = ssi_private->regs;
556 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
557 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
558 unsigned long clkrate, baudrate, tmprate;
559 u64 sub, savesub = 100000;
561 bool baudclk_is_used;
563 /* Prefer the explicitly set bitclock frequency */
564 if (ssi_private->bitclk_freq)
565 freq = ssi_private->bitclk_freq;
567 freq = params_channels(hw_params) * 32 * params_rate(hw_params);
569 /* Don't apply it to any non-baudclk circumstance */
570 if (IS_ERR(ssi_private->baudclk))
573 baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
575 /* It should be already enough to divide clock by setting pm alone */
579 factor = (div2 + 1) * (7 * psr + 1) * 2;
581 for (i = 0; i < 255; i++) {
582 /* The bclk rate must be smaller than 1/5 sysclk rate */
583 if (factor * (i + 1) < 5)
586 tmprate = freq * factor * (i + 2);
589 clkrate = clk_get_rate(ssi_private->baudclk);
591 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
594 afreq = clkrate / (i + 1);
598 else if (freq / afreq == 1)
600 else if (afreq / freq == 1)
605 /* Calculate the fraction */
620 /* No proper pm found if it is still remaining the initial value */
622 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
626 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
627 (psr ? CCSR_SSI_SxCCR_PSR : 0);
628 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
631 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
632 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
634 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
636 if (!baudclk_is_used) {
637 ret = clk_set_rate(ssi_private->baudclk, baudrate);
639 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
647 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
648 int clk_id, unsigned int freq, int dir)
650 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
652 ssi_private->bitclk_freq = freq;
658 * fsl_ssi_hw_params - program the sample size
660 * Most of the SSI registers have been programmed in the startup function,
661 * but the word length must be programmed here. Unfortunately, programming
662 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
663 * cause a problem with supporting simultaneous playback and capture. If
664 * the SSI is already playing a stream, then that stream may be temporarily
665 * stopped when you start capture.
667 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
670 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
671 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
673 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
674 struct regmap *regs = ssi_private->regs;
675 unsigned int channels = params_channels(hw_params);
676 unsigned int sample_size =
677 snd_pcm_format_width(params_format(hw_params));
678 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
683 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
684 enabled = scr_val & CCSR_SSI_SCR_SSIEN;
687 * If we're in synchronous mode, and the SSI is already enabled,
688 * then STCCR is already set properly.
690 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
693 if (fsl_ssi_is_i2s_master(ssi_private)) {
694 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
698 /* Do not enable the clock if it is already enabled */
699 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
700 ret = clk_prepare_enable(ssi_private->baudclk);
704 ssi_private->baudclk_streams |= BIT(substream->stream);
709 * FIXME: The documentation says that SxCCR[WL] should not be
710 * modified while the SSI is enabled. The only time this can
711 * happen is if we're trying to do simultaneous playback and
712 * capture in asynchronous mode. Unfortunately, I have been enable
713 * to get that to work at all on the P1022DS. Therefore, we don't
714 * bother to disable/enable the SSI when setting SxCCR[WL], because
715 * the SSI will stop anyway. Maybe one day, this will get fixed.
718 /* In synchronous mode, the SSI uses STCCR for capture */
719 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
720 ssi_private->cpu_dai_drv.symmetric_rates)
721 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
724 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
727 if (!fsl_ssi_is_ac97(ssi_private))
728 regmap_update_bits(regs, CCSR_SSI_SCR,
729 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
730 channels == 1 ? 0 : ssi_private->i2s_mode);
735 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
736 struct snd_soc_dai *cpu_dai)
738 struct snd_soc_pcm_runtime *rtd = substream->private_data;
739 struct fsl_ssi_private *ssi_private =
740 snd_soc_dai_get_drvdata(rtd->cpu_dai);
742 if (fsl_ssi_is_i2s_master(ssi_private) &&
743 ssi_private->baudclk_streams & BIT(substream->stream)) {
744 clk_disable_unprepare(ssi_private->baudclk);
745 ssi_private->baudclk_streams &= ~BIT(substream->stream);
751 static int _fsl_ssi_set_dai_fmt(struct device *dev,
752 struct fsl_ssi_private *ssi_private,
755 struct regmap *regs = ssi_private->regs;
756 u32 strcr = 0, stcr, srcr, scr, mask;
759 ssi_private->dai_fmt = fmt;
761 if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
762 dev_err(dev, "baudclk is missing which is necessary for master mode\n");
766 fsl_ssi_setup_reg_vals(ssi_private);
768 regmap_read(regs, CCSR_SSI_SCR, &scr);
769 scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
770 scr |= CCSR_SSI_SCR_SYNC_TX_FS;
772 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
773 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
775 regmap_read(regs, CCSR_SSI_STCR, &stcr);
776 regmap_read(regs, CCSR_SSI_SRCR, &srcr);
780 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
781 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
782 case SND_SOC_DAIFMT_I2S:
783 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
784 case SND_SOC_DAIFMT_CBS_CFS:
785 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
786 regmap_update_bits(regs, CCSR_SSI_STCCR,
787 CCSR_SSI_SxCCR_DC_MASK,
788 CCSR_SSI_SxCCR_DC(2));
789 regmap_update_bits(regs, CCSR_SSI_SRCCR,
790 CCSR_SSI_SxCCR_DC_MASK,
791 CCSR_SSI_SxCCR_DC(2));
793 case SND_SOC_DAIFMT_CBM_CFM:
794 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
800 /* Data on rising edge of bclk, frame low, 1clk before data */
801 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
802 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
804 case SND_SOC_DAIFMT_LEFT_J:
805 /* Data on rising edge of bclk, frame high */
806 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
808 case SND_SOC_DAIFMT_DSP_A:
809 /* Data on rising edge of bclk, frame high, 1clk before data */
810 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
811 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
813 case SND_SOC_DAIFMT_DSP_B:
814 /* Data on rising edge of bclk, frame high */
815 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
816 CCSR_SSI_STCR_TXBIT0;
818 case SND_SOC_DAIFMT_AC97:
819 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
824 scr |= ssi_private->i2s_mode;
826 /* DAI clock inversion */
827 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
828 case SND_SOC_DAIFMT_NB_NF:
829 /* Nothing to do for both normal cases */
831 case SND_SOC_DAIFMT_IB_NF:
832 /* Invert bit clock */
833 strcr ^= CCSR_SSI_STCR_TSCKP;
835 case SND_SOC_DAIFMT_NB_IF:
836 /* Invert frame clock */
837 strcr ^= CCSR_SSI_STCR_TFSI;
839 case SND_SOC_DAIFMT_IB_IF:
840 /* Invert both clocks */
841 strcr ^= CCSR_SSI_STCR_TSCKP;
842 strcr ^= CCSR_SSI_STCR_TFSI;
848 /* DAI clock master masks */
849 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
850 case SND_SOC_DAIFMT_CBS_CFS:
851 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
852 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
854 case SND_SOC_DAIFMT_CBM_CFM:
855 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
864 if (ssi_private->cpu_dai_drv.symmetric_rates) {
865 /* Need to clear RXDIR when using SYNC mode */
866 srcr &= ~CCSR_SSI_SRCR_RXDIR;
867 scr |= CCSR_SSI_SCR_SYN;
870 regmap_write(regs, CCSR_SSI_STCR, stcr);
871 regmap_write(regs, CCSR_SSI_SRCR, srcr);
872 regmap_write(regs, CCSR_SSI_SCR, scr);
875 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
876 * use FIFO 1. We program the transmit water to signal a DMA transfer
877 * if there are only two (or fewer) elements left in the FIFO. Two
878 * elements equals one frame (left channel, right channel). This value,
879 * however, depends on the depth of the transmit buffer.
881 * We set the watermark on the same level as the DMA burstsize. For
882 * fiq it is probably better to use the biggest possible watermark
885 if (ssi_private->use_dma)
886 wm = ssi_private->fifo_depth - 2;
888 wm = ssi_private->fifo_depth;
890 regmap_write(regs, CCSR_SSI_SFCSR,
891 CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
892 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
894 if (ssi_private->use_dual_fifo) {
895 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
896 CCSR_SSI_SRCR_RFEN1);
897 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
898 CCSR_SSI_STCR_TFEN1);
899 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
900 CCSR_SSI_SCR_TCH_EN);
903 if (fmt & SND_SOC_DAIFMT_AC97)
904 fsl_ssi_setup_ac97(ssi_private);
911 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
913 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
915 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
917 return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt);
921 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
923 * Note: This function can be only called when using SSI as DAI master
925 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
926 u32 rx_mask, int slots, int slot_width)
928 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
929 struct regmap *regs = ssi_private->regs;
932 /* The slot number should be >= 2 if using Network mode or I2S mode */
933 regmap_read(regs, CCSR_SSI_SCR, &val);
934 val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
935 if (val && slots < 2) {
936 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
940 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
941 CCSR_SSI_SxCCR_DC(slots));
942 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
943 CCSR_SSI_SxCCR_DC(slots));
945 /* The register SxMSKs needs SSI to provide essential clock due to
946 * hardware design. So we here temporarily enable SSI to set them.
948 regmap_read(regs, CCSR_SSI_SCR, &val);
949 val &= CCSR_SSI_SCR_SSIEN;
950 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
953 regmap_write(regs, CCSR_SSI_STMSK, tx_mask);
954 regmap_write(regs, CCSR_SSI_SRMSK, rx_mask);
956 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
962 * fsl_ssi_trigger: start and stop the DMA transfer.
964 * This function is called by ALSA to start, stop, pause, and resume the DMA
967 * The DMA channel is in external master start and pause mode, which
968 * means the SSI completely controls the flow of data.
970 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
971 struct snd_soc_dai *dai)
973 struct snd_soc_pcm_runtime *rtd = substream->private_data;
974 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
975 struct regmap *regs = ssi_private->regs;
978 case SNDRV_PCM_TRIGGER_START:
979 case SNDRV_PCM_TRIGGER_RESUME:
980 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
981 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
982 fsl_ssi_tx_config(ssi_private, true);
984 fsl_ssi_rx_config(ssi_private, true);
987 case SNDRV_PCM_TRIGGER_STOP:
988 case SNDRV_PCM_TRIGGER_SUSPEND:
989 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
990 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
991 fsl_ssi_tx_config(ssi_private, false);
993 fsl_ssi_rx_config(ssi_private, false);
1000 if (fsl_ssi_is_ac97(ssi_private)) {
1001 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1002 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
1004 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
1010 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1012 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1014 if (ssi_private->soc->imx && ssi_private->use_dma) {
1015 dai->playback_dma_data = &ssi_private->dma_params_tx;
1016 dai->capture_dma_data = &ssi_private->dma_params_rx;
1022 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1023 .startup = fsl_ssi_startup,
1024 .hw_params = fsl_ssi_hw_params,
1025 .hw_free = fsl_ssi_hw_free,
1026 .set_fmt = fsl_ssi_set_dai_fmt,
1027 .set_sysclk = fsl_ssi_set_dai_sysclk,
1028 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1029 .trigger = fsl_ssi_trigger,
1032 /* Template for the CPU dai driver structure */
1033 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1034 .probe = fsl_ssi_dai_probe,
1036 .stream_name = "CPU-Playback",
1039 .rates = FSLSSI_I2S_RATES,
1040 .formats = FSLSSI_I2S_FORMATS,
1043 .stream_name = "CPU-Capture",
1046 .rates = FSLSSI_I2S_RATES,
1047 .formats = FSLSSI_I2S_FORMATS,
1049 .ops = &fsl_ssi_dai_ops,
1052 static const struct snd_soc_component_driver fsl_ssi_component = {
1056 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1059 .stream_name = "AC97 Playback",
1062 .rates = SNDRV_PCM_RATE_8000_48000,
1063 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1066 .stream_name = "AC97 Capture",
1069 .rates = SNDRV_PCM_RATE_48000,
1070 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1072 .ops = &fsl_ssi_dai_ops,
1076 static struct fsl_ssi_private *fsl_ac97_data;
1078 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1081 struct regmap *regs = fsl_ac97_data->regs;
1090 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1093 regmap_write(regs, CCSR_SSI_SACDAT, lval);
1095 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1100 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1103 struct regmap *regs = fsl_ac97_data->regs;
1105 unsigned short val = -1;
1109 lreg = (reg & 0x7f) << 12;
1110 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1111 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1116 regmap_read(regs, CCSR_SSI_SACDAT, ®_val);
1117 val = (reg_val >> 4) & 0xffff;
1122 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1123 .read = fsl_ssi_ac97_read,
1124 .write = fsl_ssi_ac97_write,
1128 * Make every character in a string lower-case
1130 static void make_lowercase(char *s)
1136 if ((c >= 'A') && (c <= 'Z'))
1137 *p = c + ('a' - 'A');
1142 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1143 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1145 struct device_node *np = pdev->dev.of_node;
1149 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1150 if (IS_ERR(ssi_private->clk)) {
1151 ret = PTR_ERR(ssi_private->clk);
1152 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1156 ret = clk_prepare_enable(ssi_private->clk);
1158 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1162 /* For those SLAVE implementations, we ingore non-baudclk cases
1163 * and, instead, abandon MASTER mode that needs baud clock.
1165 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1166 if (IS_ERR(ssi_private->baudclk))
1167 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1168 PTR_ERR(ssi_private->baudclk));
1171 * We have burstsize be "fifo_depth - 2" to match the SSI
1172 * watermark setting in fsl_ssi_startup().
1174 ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1175 ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1176 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
1177 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
1179 ret = !of_property_read_u32_array(np, "dmas", dmas, 4);
1180 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1181 ssi_private->use_dual_fifo = true;
1182 /* When using dual fifo mode, we need to keep watermark
1183 * as even numbers due to dma script limitation.
1185 ssi_private->dma_params_tx.maxburst &= ~0x1;
1186 ssi_private->dma_params_rx.maxburst &= ~0x1;
1189 if (!ssi_private->use_dma) {
1192 * Some boards use an incompatible codec. To get it
1193 * working, we are using imx-fiq-pcm-audio, that
1194 * can handle those codecs. DMA is not possible in this
1198 ssi_private->fiq_params.irq = ssi_private->irq;
1199 ssi_private->fiq_params.base = iomem;
1200 ssi_private->fiq_params.dma_params_rx =
1201 &ssi_private->dma_params_rx;
1202 ssi_private->fiq_params.dma_params_tx =
1203 &ssi_private->dma_params_tx;
1205 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1209 ret = imx_pcm_dma_init(pdev);
1217 clk_disable_unprepare(ssi_private->clk);
1222 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1223 struct fsl_ssi_private *ssi_private)
1225 if (!ssi_private->use_dma)
1226 imx_pcm_fiq_exit(pdev);
1227 clk_disable_unprepare(ssi_private->clk);
1230 static int fsl_ssi_probe(struct platform_device *pdev)
1232 struct fsl_ssi_private *ssi_private;
1234 struct device_node *np = pdev->dev.of_node;
1235 const struct of_device_id *of_id;
1236 const char *p, *sprop;
1237 const uint32_t *iprop;
1238 struct resource res;
1239 void __iomem *iomem;
1242 /* SSIs that are not connected on the board should have a
1243 * status = "disabled"
1244 * property in their device tree nodes.
1246 if (!of_device_is_available(np))
1249 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1250 if (!of_id || !of_id->data)
1253 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1256 dev_err(&pdev->dev, "could not allocate DAI object\n");
1260 ssi_private->soc = of_id->data;
1262 sprop = of_get_property(np, "fsl,mode", NULL);
1264 if (!strcmp(sprop, "ac97-slave"))
1265 ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
1266 else if (!strcmp(sprop, "i2s-slave"))
1267 ssi_private->dai_fmt = SND_SOC_DAIFMT_I2S |
1268 SND_SOC_DAIFMT_CBM_CFM;
1271 ssi_private->use_dma = !of_property_read_bool(np,
1272 "fsl,fiq-stream-filter");
1274 if (fsl_ssi_is_ac97(ssi_private)) {
1275 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1276 sizeof(fsl_ssi_ac97_dai));
1278 fsl_ac97_data = ssi_private;
1280 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1282 /* Initialize this copy of the CPU DAI driver structure */
1283 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1284 sizeof(fsl_ssi_dai_template));
1286 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1288 /* Get the addresses and IRQ */
1289 ret = of_address_to_resource(np, 0, &res);
1291 dev_err(&pdev->dev, "could not determine device resources\n");
1294 ssi_private->ssi_phys = res.start;
1296 iomem = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
1298 dev_err(&pdev->dev, "could not map device resources\n");
1302 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1303 &fsl_ssi_regconfig);
1304 if (IS_ERR(ssi_private->regs)) {
1305 dev_err(&pdev->dev, "Failed to init register map\n");
1306 return PTR_ERR(ssi_private->regs);
1309 ssi_private->irq = irq_of_parse_and_map(np, 0);
1310 if (!ssi_private->irq) {
1311 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1315 /* Are the RX and the TX clocks locked? */
1316 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1317 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1318 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1319 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1322 /* Determine the FIFO depth. */
1323 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1325 ssi_private->fifo_depth = be32_to_cpup(iprop);
1327 /* Older 8610 DTs didn't have the fifo-depth property */
1328 ssi_private->fifo_depth = 8;
1330 dev_set_drvdata(&pdev->dev, ssi_private);
1332 if (ssi_private->soc->imx) {
1333 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
1338 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1339 &ssi_private->cpu_dai_drv, 1);
1341 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1342 goto error_asoc_register;
1345 if (ssi_private->use_dma) {
1346 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1347 fsl_ssi_isr, 0, dev_name(&pdev->dev),
1350 dev_err(&pdev->dev, "could not claim irq %u\n",
1356 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1358 goto error_asoc_register;
1361 * If codec-handle property is missing from SSI node, we assume
1362 * that the machine driver uses new binding which does not require
1363 * SSI driver to trigger machine driver's probe.
1365 if (!of_get_property(np, "codec-handle", NULL))
1368 /* Trigger the machine driver's probe function. The platform driver
1369 * name of the machine driver is taken from /compatible property of the
1370 * device tree. We also pass the address of the CPU DAI driver
1373 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1374 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1375 p = strrchr(sprop, ',');
1378 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1379 make_lowercase(name);
1382 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1383 if (IS_ERR(ssi_private->pdev)) {
1384 ret = PTR_ERR(ssi_private->pdev);
1385 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1386 goto error_sound_card;
1390 if (ssi_private->dai_fmt)
1391 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private,
1392 ssi_private->dai_fmt);
1397 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1400 snd_soc_unregister_component(&pdev->dev);
1402 error_asoc_register:
1403 if (ssi_private->soc->imx)
1404 fsl_ssi_imx_clean(pdev, ssi_private);
1407 if (ssi_private->use_dma)
1408 irq_dispose_mapping(ssi_private->irq);
1413 static int fsl_ssi_remove(struct platform_device *pdev)
1415 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1417 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1419 if (ssi_private->pdev)
1420 platform_device_unregister(ssi_private->pdev);
1421 snd_soc_unregister_component(&pdev->dev);
1423 if (ssi_private->soc->imx)
1424 fsl_ssi_imx_clean(pdev, ssi_private);
1426 if (ssi_private->use_dma)
1427 irq_dispose_mapping(ssi_private->irq);
1432 static struct platform_driver fsl_ssi_driver = {
1434 .name = "fsl-ssi-dai",
1435 .owner = THIS_MODULE,
1436 .of_match_table = fsl_ssi_ids,
1438 .probe = fsl_ssi_probe,
1439 .remove = fsl_ssi_remove,
1442 module_platform_driver(fsl_ssi_driver);
1444 MODULE_ALIAS("platform:fsl-ssi-dai");
1445 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1446 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1447 MODULE_LICENSE("GPL v2");