2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/debugfs.h>
39 #include <linux/device.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/of_address.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_platform.h>
47 #include <sound/core.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/initval.h>
51 #include <sound/soc.h>
52 #include <sound/dmaengine_pcm.h>
58 #define read_ssi(addr) in_be32(addr)
59 #define write_ssi(val, addr) out_be32(addr, val)
60 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
62 #define read_ssi(addr) readl(addr)
63 #define write_ssi(val, addr) writel(val, addr)
65 * FIXME: Proper locking should be added at write_ssi_mask caller level
66 * to ensure this register read/modify/write sequence is race free.
68 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
70 u32 val = readl(addr);
71 val = (val & ~clear) | set;
77 * FSLSSI_I2S_RATES: sample rates supported by the I2S
79 * This driver currently only supports the SSI running in I2S slave mode,
80 * which means the codec determines the sample rate. Therefore, we tell
81 * ALSA that we support all rates and let the codec driver decide what rates
82 * are really supported.
84 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
87 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
89 * This driver currently only supports the SSI running in I2S slave mode.
91 * The SSI has a limitation in that the samples must be in the same byte
92 * order as the host CPU. This is because when multiple bytes are written
93 * to the STX register, the bytes and bits must be written in the same
94 * order. The STX is a shift register, so all the bits need to be aligned
95 * (bit-endianness must match byte-endianness). Processors typically write
96 * the bits within a byte in the same order that the bytes of a word are
97 * written in. So if the host CPU is big-endian, then only big-endian
98 * samples will be written to STX properly.
101 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
102 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
103 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
105 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
106 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
107 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
110 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
111 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
112 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
113 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
114 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
115 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
116 #define FSLSSI_SISR_MASK (FSLSSI_SIER_DBG_RX_FLAGS | FSLSSI_SIER_DBG_TX_FLAGS)
126 struct fsl_ssi_reg_val {
133 struct fsl_ssi_rxtx_reg_val {
134 struct fsl_ssi_reg_val rx;
135 struct fsl_ssi_reg_val tx;
139 * fsl_ssi_private: per-SSI private data
141 * @ssi: pointer to the SSI's registers
142 * @ssi_phys: physical address of the SSI registers
143 * @irq: IRQ of this SSI
144 * @playback: the number of playback streams opened
145 * @capture: the number of capture streams opened
146 * @cpu_dai: the CPU DAI for this device
147 * @dev_attr: the sysfs device attribute structure
148 * @stats: SSI statistics
149 * @name: name for this device
151 struct fsl_ssi_private {
152 struct ccsr_ssi __iomem *ssi;
155 unsigned int fifo_depth;
156 struct snd_soc_dai_driver cpu_dai_drv;
157 struct platform_device *pdev;
159 enum fsl_ssi_type hw_type;
168 spinlock_t baudclk_lock;
171 struct snd_dmaengine_dai_dma_data dma_params_tx;
172 struct snd_dmaengine_dai_dma_data dma_params_rx;
173 struct imx_dma_data filter_data_tx;
174 struct imx_dma_data filter_data_rx;
175 struct imx_pcm_fiq_params fiq_params;
176 /* Register values for rx/tx configuration */
177 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
202 struct dentry *dbg_dir;
203 struct dentry *dbg_stats;
208 static const struct of_device_id fsl_ssi_ids[] = {
209 { .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610},
210 { .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51},
211 { .compatible = "fsl,imx35-ssi", .data = (void *) FSL_SSI_MX35},
212 { .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21},
215 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
218 * fsl_ssi_isr: SSI interrupt handler
220 * Although it's possible to use the interrupt handler to send and receive
221 * data to/from the SSI, we use the DMA instead. Programming is more
222 * complicated, but the performance is much better.
224 * This interrupt handler is used only to gather statistics.
226 * @irq: IRQ of the SSI device
227 * @dev_id: pointer to the ssi_private structure for this SSI device
229 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
231 struct fsl_ssi_private *ssi_private = dev_id;
232 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
233 irqreturn_t ret = IRQ_NONE;
236 __be32 sisr_write_mask = 0;
238 switch (ssi_private->hw_type) {
243 case FSL_SSI_MCP8610:
245 sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
246 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
247 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
251 sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
252 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
256 /* We got an interrupt, so read the status register to see what we
257 were interrupted for. We mask it with the Interrupt Enable register
258 so that we only check for events that we're interested in.
260 sisr = read_ssi(&ssi->sisr) & FSLSSI_SISR_MASK;
262 if (sisr & CCSR_SSI_SISR_RFRC) {
263 ssi_private->stats.rfrc++;
267 if (sisr & CCSR_SSI_SISR_TFRC) {
268 ssi_private->stats.tfrc++;
272 if (sisr & CCSR_SSI_SISR_CMDAU) {
273 ssi_private->stats.cmdau++;
277 if (sisr & CCSR_SSI_SISR_CMDDU) {
278 ssi_private->stats.cmddu++;
282 if (sisr & CCSR_SSI_SISR_RXT) {
283 ssi_private->stats.rxt++;
287 if (sisr & CCSR_SSI_SISR_RDR1) {
288 ssi_private->stats.rdr1++;
292 if (sisr & CCSR_SSI_SISR_RDR0) {
293 ssi_private->stats.rdr0++;
297 if (sisr & CCSR_SSI_SISR_TDE1) {
298 ssi_private->stats.tde1++;
302 if (sisr & CCSR_SSI_SISR_TDE0) {
303 ssi_private->stats.tde0++;
307 if (sisr & CCSR_SSI_SISR_ROE1) {
308 ssi_private->stats.roe1++;
312 if (sisr & CCSR_SSI_SISR_ROE0) {
313 ssi_private->stats.roe0++;
317 if (sisr & CCSR_SSI_SISR_TUE1) {
318 ssi_private->stats.tue1++;
322 if (sisr & CCSR_SSI_SISR_TUE0) {
323 ssi_private->stats.tue0++;
327 if (sisr & CCSR_SSI_SISR_TFS) {
328 ssi_private->stats.tfs++;
332 if (sisr & CCSR_SSI_SISR_RFS) {
333 ssi_private->stats.rfs++;
337 if (sisr & CCSR_SSI_SISR_TLS) {
338 ssi_private->stats.tls++;
342 if (sisr & CCSR_SSI_SISR_RLS) {
343 ssi_private->stats.rls++;
347 if (sisr & CCSR_SSI_SISR_RFF1) {
348 ssi_private->stats.rff1++;
352 if (sisr & CCSR_SSI_SISR_RFF0) {
353 ssi_private->stats.rff0++;
357 if (sisr & CCSR_SSI_SISR_TFE1) {
358 ssi_private->stats.tfe1++;
362 if (sisr & CCSR_SSI_SISR_TFE0) {
363 ssi_private->stats.tfe0++;
367 sisr2 = sisr & sisr_write_mask;
368 /* Clear the bits that we set */
370 write_ssi(sisr2, &ssi->sisr);
375 #if IS_ENABLED(CONFIG_DEBUG_FS)
376 /* Show the statistics of a flag only if its interrupt is enabled. The
377 * compiler will optimze this code to a no-op if the interrupt is not
380 #define SIER_SHOW(flag, name) \
382 if (FSLSSI_SISR_MASK & CCSR_SSI_SIER_##flag) \
383 seq_printf(s, #name "=%u\n", ssi_private->stats.name); \
388 * fsl_sysfs_ssi_show: display SSI statistics
390 * Display the statistics for the current SSI device. To avoid confusion,
391 * we only show those counts that are enabled.
393 static int fsl_ssi_stats_show(struct seq_file *s, void *unused)
395 struct fsl_ssi_private *ssi_private = s->private;
397 SIER_SHOW(RFRC_EN, rfrc);
398 SIER_SHOW(TFRC_EN, tfrc);
399 SIER_SHOW(CMDAU_EN, cmdau);
400 SIER_SHOW(CMDDU_EN, cmddu);
401 SIER_SHOW(RXT_EN, rxt);
402 SIER_SHOW(RDR1_EN, rdr1);
403 SIER_SHOW(RDR0_EN, rdr0);
404 SIER_SHOW(TDE1_EN, tde1);
405 SIER_SHOW(TDE0_EN, tde0);
406 SIER_SHOW(ROE1_EN, roe1);
407 SIER_SHOW(ROE0_EN, roe0);
408 SIER_SHOW(TUE1_EN, tue1);
409 SIER_SHOW(TUE0_EN, tue0);
410 SIER_SHOW(TFS_EN, tfs);
411 SIER_SHOW(RFS_EN, rfs);
412 SIER_SHOW(TLS_EN, tls);
413 SIER_SHOW(RLS_EN, rls);
414 SIER_SHOW(RFF1_EN, rff1);
415 SIER_SHOW(RFF0_EN, rff0);
416 SIER_SHOW(TFE1_EN, tfe1);
417 SIER_SHOW(TFE0_EN, tfe0);
422 static int fsl_ssi_stats_open(struct inode *inode, struct file *file)
424 return single_open(file, fsl_ssi_stats_show, inode->i_private);
427 static const struct file_operations fsl_ssi_stats_ops = {
428 .open = fsl_ssi_stats_open,
431 .release = single_release,
434 static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
437 ssi_private->dbg_dir = debugfs_create_dir(dev_name(dev), NULL);
438 if (!ssi_private->dbg_dir)
441 ssi_private->dbg_stats = debugfs_create_file("stats", S_IRUGO,
442 ssi_private->dbg_dir, ssi_private, &fsl_ssi_stats_ops);
443 if (!ssi_private->dbg_stats) {
444 debugfs_remove(ssi_private->dbg_dir);
451 static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
453 debugfs_remove(ssi_private->dbg_stats);
454 debugfs_remove(ssi_private->dbg_dir);
459 static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
465 static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
469 #endif /* IS_ENABLED(CONFIG_DEBUG_FS) */
472 * Enable/Disable all rx/tx config flags at once.
474 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
477 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
478 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
481 write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier);
482 write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr);
483 write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr);
485 write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0);
486 write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0);
487 write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0);
492 * Enable/Disable a ssi configuration. You have to pass either
493 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
495 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
496 struct fsl_ssi_reg_val *vals)
498 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
499 struct fsl_ssi_reg_val *avals;
500 u32 scr_val = read_ssi(&ssi->scr);
501 int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
502 !!(scr_val & CCSR_SSI_SCR_RE);
504 /* Find the other direction values rx or tx which we do not want to
506 if (&ssi_private->rxtx_reg_val.rx == vals)
507 avals = &ssi_private->rxtx_reg_val.tx;
509 avals = &ssi_private->rxtx_reg_val.rx;
511 /* If vals should be disabled, start with disabling the unit */
513 u32 scr = vals->scr & (vals->scr ^ avals->scr);
514 write_ssi_mask(&ssi->scr, scr, 0);
518 * We are running on a SoC which does not support online SSI
519 * reconfiguration, so we have to enable all necessary flags at once
520 * even if we do not use them later (capture and playback configuration)
522 if (ssi_private->offline_config) {
523 if ((enable && !nr_active_streams) ||
524 (!enable && nr_active_streams == 1))
525 fsl_ssi_rxtx_config(ssi_private, enable);
531 * Configure single direction units while the SSI unit is running
532 * (online configuration)
535 write_ssi_mask(&ssi->sier, 0, vals->sier);
536 write_ssi_mask(&ssi->srcr, 0, vals->srcr);
537 write_ssi_mask(&ssi->stcr, 0, vals->stcr);
544 * Disabling the necessary flags for one of rx/tx while the
545 * other stream is active is a little bit more difficult. We
546 * have to disable only those flags that differ between both
547 * streams (rx XOR tx) and that are set in the stream that is
548 * disabled now. Otherwise we could alter flags of the other
552 /* These assignments are simply vals without bits set in avals*/
553 sier = vals->sier & (vals->sier ^ avals->sier);
554 srcr = vals->srcr & (vals->srcr ^ avals->srcr);
555 stcr = vals->stcr & (vals->stcr ^ avals->stcr);
557 write_ssi_mask(&ssi->srcr, srcr, 0);
558 write_ssi_mask(&ssi->stcr, stcr, 0);
559 write_ssi_mask(&ssi->sier, sier, 0);
563 /* Enabling of subunits is done after configuration */
565 write_ssi_mask(&ssi->scr, 0, vals->scr);
569 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
571 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
574 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
576 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
580 * Setup rx/tx register values used to enable/disable the streams. These will
581 * be used later in fsl_ssi_config to setup the streams without the need to
582 * check for all different SSI modes.
584 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
586 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
588 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
589 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
591 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
592 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
595 if (!ssi_private->imx_ac97) {
596 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
597 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
598 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
599 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
602 if (ssi_private->use_dma) {
603 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
604 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
606 reg->rx.sier |= CCSR_SSI_SIER_RIE;
607 reg->tx.sier |= CCSR_SSI_SIER_TIE;
610 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
611 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
614 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
616 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
619 * Setup the clock control register
621 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
623 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
627 * Enable AC97 mode and startup the SSI
629 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
631 write_ssi(0xff, &ssi->saccdis);
632 write_ssi(0x300, &ssi->saccen);
635 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
636 * codec before a stream is started.
638 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
639 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
641 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
644 static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
646 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
648 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
650 fsl_ssi_setup_reg_vals(ssi_private);
652 if (ssi_private->imx_ac97)
653 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
655 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
658 * Section 16.5 of the MPC8610 reference manual says that the SSI needs
659 * to be disabled before updating the registers we set here.
661 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
664 * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
665 * enable the transmit and receive FIFO.
667 * FIXME: Little-endian samples require a different shift dir
669 write_ssi_mask(&ssi->scr,
670 CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
671 CCSR_SSI_SCR_TFR_CLK_DIS |
672 ssi_private->i2s_mode |
673 (synchronous ? CCSR_SSI_SCR_SYN : 0));
675 write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFSI |
676 CCSR_SSI_STCR_TEFS | CCSR_SSI_STCR_TSCKP, &ssi->stcr);
678 write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFSI |
679 CCSR_SSI_SRCR_REFS | CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
682 * The DC and PM bits are only used if the SSI is the clock master.
686 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
687 * use FIFO 1. We program the transmit water to signal a DMA transfer
688 * if there are only two (or fewer) elements left in the FIFO. Two
689 * elements equals one frame (left channel, right channel). This value,
690 * however, depends on the depth of the transmit buffer.
692 * We set the watermark on the same level as the DMA burstsize. For
693 * fiq it is probably better to use the biggest possible watermark
696 if (ssi_private->use_dma)
697 wm = ssi_private->fifo_depth - 2;
699 wm = ssi_private->fifo_depth;
701 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
702 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
706 * For ac97 interrupts are enabled with the startup of the substream
707 * because it is also running without an active substream. Normally SSI
708 * is only enabled when there is a substream.
710 if (ssi_private->imx_ac97)
711 fsl_ssi_setup_ac97(ssi_private);
714 * Set a default slot number so that there is no need for those common
715 * cases like I2S mode to call the extra set_tdm_slot() any more.
717 if (!ssi_private->imx_ac97) {
718 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
719 CCSR_SSI_SxCCR_DC(2));
720 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
721 CCSR_SSI_SxCCR_DC(2));
729 * fsl_ssi_startup: create a new substream
731 * This is the first function called when a stream is opened.
733 * If this is the first stream open, then grab the IRQ and program most of
736 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
737 struct snd_soc_dai *dai)
739 struct snd_soc_pcm_runtime *rtd = substream->private_data;
740 struct fsl_ssi_private *ssi_private =
741 snd_soc_dai_get_drvdata(rtd->cpu_dai);
744 /* First, we only do fsl_ssi_setup() when SSI is going to be active.
745 * Second, fsl_ssi_setup was already called by ac97_init earlier if
746 * the driver is in ac97 mode.
748 if (!dai->active && !ssi_private->imx_ac97) {
749 fsl_ssi_setup(ssi_private);
750 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
751 ssi_private->baudclk_locked = false;
752 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
759 * fsl_ssi_hw_params - program the sample size
761 * Most of the SSI registers have been programmed in the startup function,
762 * but the word length must be programmed here. Unfortunately, programming
763 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
764 * cause a problem with supporting simultaneous playback and capture. If
765 * the SSI is already playing a stream, then that stream may be temporarily
766 * stopped when you start capture.
768 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
771 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
772 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
774 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
775 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
776 unsigned int channels = params_channels(hw_params);
777 unsigned int sample_size =
778 snd_pcm_format_width(params_format(hw_params));
779 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
780 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
783 * If we're in synchronous mode, and the SSI is already enabled,
784 * then STCCR is already set properly.
786 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
790 * FIXME: The documentation says that SxCCR[WL] should not be
791 * modified while the SSI is enabled. The only time this can
792 * happen is if we're trying to do simultaneous playback and
793 * capture in asynchronous mode. Unfortunately, I have been enable
794 * to get that to work at all on the P1022DS. Therefore, we don't
795 * bother to disable/enable the SSI when setting SxCCR[WL], because
796 * the SSI will stop anyway. Maybe one day, this will get fixed.
799 /* In synchronous mode, the SSI uses STCCR for capture */
800 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
801 ssi_private->cpu_dai_drv.symmetric_rates)
802 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
804 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
806 if (!ssi_private->imx_ac97)
807 write_ssi_mask(&ssi->scr,
808 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
809 channels == 1 ? 0 : ssi_private->i2s_mode);
815 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
817 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
819 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
820 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
821 u32 strcr = 0, stcr, srcr, scr, mask;
823 scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
824 scr |= CCSR_SSI_SCR_NET;
826 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
827 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
829 stcr = read_ssi(&ssi->stcr) & ~mask;
830 srcr = read_ssi(&ssi->srcr) & ~mask;
832 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
833 case SND_SOC_DAIFMT_I2S:
834 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
835 case SND_SOC_DAIFMT_CBS_CFS:
836 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_MASTER;
838 case SND_SOC_DAIFMT_CBM_CFM:
839 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
844 scr |= ssi_private->i2s_mode;
846 /* Data on rising edge of bclk, frame low, 1clk before data */
847 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
848 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
850 case SND_SOC_DAIFMT_LEFT_J:
851 /* Data on rising edge of bclk, frame high */
852 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
854 case SND_SOC_DAIFMT_DSP_A:
855 /* Data on rising edge of bclk, frame high, 1clk before data */
856 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
857 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
859 case SND_SOC_DAIFMT_DSP_B:
860 /* Data on rising edge of bclk, frame high */
861 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
862 CCSR_SSI_STCR_TXBIT0;
868 /* DAI clock inversion */
869 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
870 case SND_SOC_DAIFMT_NB_NF:
871 /* Nothing to do for both normal cases */
873 case SND_SOC_DAIFMT_IB_NF:
874 /* Invert bit clock */
875 strcr ^= CCSR_SSI_STCR_TSCKP;
877 case SND_SOC_DAIFMT_NB_IF:
878 /* Invert frame clock */
879 strcr ^= CCSR_SSI_STCR_TFSI;
881 case SND_SOC_DAIFMT_IB_IF:
882 /* Invert both clocks */
883 strcr ^= CCSR_SSI_STCR_TSCKP;
884 strcr ^= CCSR_SSI_STCR_TFSI;
890 /* DAI clock master masks */
891 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
892 case SND_SOC_DAIFMT_CBS_CFS:
893 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
894 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
896 case SND_SOC_DAIFMT_CBM_CFM:
897 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
906 if (ssi_private->cpu_dai_drv.symmetric_rates) {
907 /* Need to clear RXDIR when using SYNC mode */
908 srcr &= ~CCSR_SSI_SRCR_RXDIR;
909 scr |= CCSR_SSI_SCR_SYN;
912 write_ssi(stcr, &ssi->stcr);
913 write_ssi(srcr, &ssi->srcr);
914 write_ssi(scr, &ssi->scr);
920 * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock
922 * Note: This function can be only called when using SSI as DAI master
924 * Quick instruction for parameters:
925 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
926 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
928 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
929 int clk_id, unsigned int freq, int dir)
931 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
932 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
933 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
934 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
935 unsigned long flags, clkrate, baudrate, tmprate;
936 u64 sub, savesub = 100000;
938 /* Don't apply it to any non-baudclk circumstance */
939 if (IS_ERR(ssi_private->baudclk))
942 /* It should be already enough to divide clock by setting pm alone */
946 factor = (div2 + 1) * (7 * psr + 1) * 2;
948 for (i = 0; i < 255; i++) {
949 /* The bclk rate must be smaller than 1/5 sysclk rate */
950 if (factor * (i + 1) < 5)
953 tmprate = freq * factor * (i + 2);
954 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
956 do_div(clkrate, factor);
957 afreq = (u32)clkrate / (i + 1);
961 else if (freq / afreq == 1)
963 else if (afreq / freq == 1)
968 /* Calculate the fraction */
983 /* No proper pm found if it is still remaining the initial value */
985 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
989 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
990 (psr ? CCSR_SSI_SxCCR_PSR : 0);
991 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | CCSR_SSI_SxCCR_PSR;
993 if (dir == SND_SOC_CLOCK_OUT || synchronous)
994 write_ssi_mask(&ssi->stccr, mask, stccr);
996 write_ssi_mask(&ssi->srccr, mask, stccr);
998 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
999 if (!ssi_private->baudclk_locked) {
1000 ret = clk_set_rate(ssi_private->baudclk, baudrate);
1002 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
1003 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
1006 ssi_private->baudclk_locked = true;
1008 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
1014 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
1016 * Note: This function can be only called when using SSI as DAI master
1018 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
1019 u32 rx_mask, int slots, int slot_width)
1021 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1022 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
1025 /* The slot number should be >= 2 if using Network mode or I2S mode */
1026 val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET);
1027 if (val && slots < 2) {
1028 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
1032 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
1033 CCSR_SSI_SxCCR_DC(slots));
1034 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
1035 CCSR_SSI_SxCCR_DC(slots));
1037 /* The register SxMSKs needs SSI to provide essential clock due to
1038 * hardware design. So we here temporarily enable SSI to set them.
1040 val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
1041 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
1043 write_ssi(tx_mask, &ssi->stmsk);
1044 write_ssi(rx_mask, &ssi->srmsk);
1046 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val);
1052 * fsl_ssi_trigger: start and stop the DMA transfer.
1054 * This function is called by ALSA to start, stop, pause, and resume the DMA
1057 * The DMA channel is in external master start and pause mode, which
1058 * means the SSI completely controls the flow of data.
1060 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1061 struct snd_soc_dai *dai)
1063 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1064 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1065 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
1066 unsigned long flags;
1069 case SNDRV_PCM_TRIGGER_START:
1070 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1071 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1072 fsl_ssi_tx_config(ssi_private, true);
1074 fsl_ssi_rx_config(ssi_private, true);
1077 case SNDRV_PCM_TRIGGER_STOP:
1078 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1079 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1080 fsl_ssi_tx_config(ssi_private, false);
1082 fsl_ssi_rx_config(ssi_private, false);
1084 if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
1085 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) {
1086 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
1087 ssi_private->baudclk_locked = false;
1088 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
1096 if (ssi_private->imx_ac97) {
1097 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1098 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
1100 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
1106 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1108 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1110 if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
1111 dai->playback_dma_data = &ssi_private->dma_params_tx;
1112 dai->capture_dma_data = &ssi_private->dma_params_rx;
1118 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1119 .startup = fsl_ssi_startup,
1120 .hw_params = fsl_ssi_hw_params,
1121 .set_fmt = fsl_ssi_set_dai_fmt,
1122 .set_sysclk = fsl_ssi_set_dai_sysclk,
1123 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1124 .trigger = fsl_ssi_trigger,
1127 /* Template for the CPU dai driver structure */
1128 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1129 .probe = fsl_ssi_dai_probe,
1133 .rates = FSLSSI_I2S_RATES,
1134 .formats = FSLSSI_I2S_FORMATS,
1139 .rates = FSLSSI_I2S_RATES,
1140 .formats = FSLSSI_I2S_FORMATS,
1142 .ops = &fsl_ssi_dai_ops,
1145 static const struct snd_soc_component_driver fsl_ssi_component = {
1149 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1152 .stream_name = "AC97 Playback",
1155 .rates = SNDRV_PCM_RATE_8000_48000,
1156 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1159 .stream_name = "AC97 Capture",
1162 .rates = SNDRV_PCM_RATE_48000,
1163 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1165 .ops = &fsl_ssi_dai_ops,
1169 static struct fsl_ssi_private *fsl_ac97_data;
1171 static void fsl_ssi_ac97_init(void)
1173 fsl_ssi_setup(fsl_ac97_data);
1176 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1179 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
1188 write_ssi(lreg, &ssi->sacadd);
1191 write_ssi(lval , &ssi->sacdat);
1193 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
1198 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1201 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
1203 unsigned short val = -1;
1206 lreg = (reg & 0x7f) << 12;
1207 write_ssi(lreg, &ssi->sacadd);
1208 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
1213 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
1218 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1219 .read = fsl_ssi_ac97_read,
1220 .write = fsl_ssi_ac97_write,
1224 * Make every character in a string lower-case
1226 static void make_lowercase(char *s)
1232 if ((c >= 'A') && (c <= 'Z'))
1233 *p = c + ('a' - 'A');
1238 static int fsl_ssi_probe(struct platform_device *pdev)
1240 struct fsl_ssi_private *ssi_private;
1242 struct device_attribute *dev_attr = NULL;
1243 struct device_node *np = pdev->dev.of_node;
1244 const struct of_device_id *of_id;
1245 enum fsl_ssi_type hw_type;
1246 const char *p, *sprop;
1247 const uint32_t *iprop;
1248 struct resource res;
1253 /* SSIs that are not connected on the board should have a
1254 * status = "disabled"
1255 * property in their device tree nodes.
1257 if (!of_device_is_available(np))
1260 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1263 hw_type = (enum fsl_ssi_type) of_id->data;
1265 /* We only support the SSI in "I2S Slave" mode */
1266 sprop = of_get_property(np, "fsl,mode", NULL);
1268 dev_err(&pdev->dev, "fsl,mode property is necessary\n");
1271 if (!strcmp(sprop, "ac97-slave")) {
1273 } else if (strcmp(sprop, "i2s-slave")) {
1274 dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop);
1278 /* The DAI name is the last part of the full name of the node. */
1279 p = strrchr(np->full_name, '/') + 1;
1280 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
1283 dev_err(&pdev->dev, "could not allocate DAI object\n");
1287 strcpy(ssi_private->name, p);
1289 ssi_private->use_dma = !of_property_read_bool(np,
1290 "fsl,fiq-stream-filter");
1291 ssi_private->hw_type = hw_type;
1294 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1295 sizeof(fsl_ssi_ac97_dai));
1297 fsl_ac97_data = ssi_private;
1298 ssi_private->imx_ac97 = true;
1300 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1302 /* Initialize this copy of the CPU DAI driver structure */
1303 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1304 sizeof(fsl_ssi_dai_template));
1306 ssi_private->cpu_dai_drv.name = ssi_private->name;
1308 /* Get the addresses and IRQ */
1309 ret = of_address_to_resource(np, 0, &res);
1311 dev_err(&pdev->dev, "could not determine device resources\n");
1314 ssi_private->ssi = of_iomap(np, 0);
1315 if (!ssi_private->ssi) {
1316 dev_err(&pdev->dev, "could not map device resources\n");
1319 ssi_private->ssi_phys = res.start;
1321 ssi_private->irq = irq_of_parse_and_map(np, 0);
1322 if (!ssi_private->irq) {
1323 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1327 /* Are the RX and the TX clocks locked? */
1328 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1329 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1330 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1331 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1334 /* Determine the FIFO depth. */
1335 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1337 ssi_private->fifo_depth = be32_to_cpup(iprop);
1339 /* Older 8610 DTs didn't have the fifo-depth property */
1340 ssi_private->fifo_depth = 8;
1342 ssi_private->baudclk_locked = false;
1343 spin_lock_init(&ssi_private->baudclk_lock);
1346 * imx51 and later SoCs have a slightly different IP that allows the
1347 * SSI configuration while the SSI unit is running.
1349 * More important, it is necessary on those SoCs to configure the
1350 * sperate TX/RX DMA bits just before starting the stream
1351 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
1352 * sends any DMA requests to the SDMA unit, otherwise it is not defined
1353 * how the SDMA unit handles the DMA request.
1355 * SDMA units are present on devices starting at imx35 but the imx35
1356 * reference manual states that the DMA bits should not be changed
1357 * while the SSI unit is running (SSIEN). So we support the necessary
1358 * online configuration of fsl-ssi starting at imx51.
1361 case FSL_SSI_MCP8610:
1364 ssi_private->offline_config = true;
1367 ssi_private->offline_config = false;
1371 if (hw_type == FSL_SSI_MX21 || hw_type == FSL_SSI_MX51 ||
1372 hw_type == FSL_SSI_MX35) {
1374 ssi_private->ssi_on_imx = true;
1376 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1377 if (IS_ERR(ssi_private->clk)) {
1378 ret = PTR_ERR(ssi_private->clk);
1379 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1382 ret = clk_prepare_enable(ssi_private->clk);
1384 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n",
1389 /* For those SLAVE implementations, we ingore non-baudclk cases
1390 * and, instead, abandon MASTER mode that needs baud clock.
1392 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1393 if (IS_ERR(ssi_private->baudclk))
1394 dev_warn(&pdev->dev, "could not get baud clock: %ld\n",
1395 PTR_ERR(ssi_private->baudclk));
1397 clk_prepare_enable(ssi_private->baudclk);
1400 * We have burstsize be "fifo_depth - 2" to match the SSI
1401 * watermark setting in fsl_ssi_startup().
1403 ssi_private->dma_params_tx.maxburst =
1404 ssi_private->fifo_depth - 2;
1405 ssi_private->dma_params_rx.maxburst =
1406 ssi_private->fifo_depth - 2;
1407 ssi_private->dma_params_tx.addr =
1408 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
1409 ssi_private->dma_params_rx.addr =
1410 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
1411 ssi_private->dma_params_tx.filter_data =
1412 &ssi_private->filter_data_tx;
1413 ssi_private->dma_params_rx.filter_data =
1414 &ssi_private->filter_data_rx;
1415 if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
1416 ssi_private->use_dma) {
1418 * FIXME: This is a temporary solution until all
1419 * necessary dma drivers support the generic dma
1422 ret = of_property_read_u32_array(pdev->dev.of_node,
1423 "fsl,ssi-dma-events", dma_events, 2);
1424 if (ret && ssi_private->use_dma) {
1425 dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
1430 shared = of_device_is_compatible(of_get_parent(np),
1433 imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
1434 dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1435 imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
1436 dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1440 * Enable interrupts only for MCP8610 and MX51. The other MXs have
1441 * different writeable interrupt status registers.
1443 if (ssi_private->use_dma) {
1444 /* The 'name' should not have any slashes in it. */
1445 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1446 fsl_ssi_isr, 0, ssi_private->name,
1448 ssi_private->irq_stats = true;
1450 dev_err(&pdev->dev, "could not claim irq %u\n",
1456 /* Register with ASoC */
1457 dev_set_drvdata(&pdev->dev, ssi_private);
1459 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1460 &ssi_private->cpu_dai_drv, 1);
1462 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1466 ret = fsl_ssi_debugfs_create(ssi_private, &pdev->dev);
1470 if (ssi_private->ssi_on_imx) {
1471 if (!ssi_private->use_dma) {
1474 * Some boards use an incompatible codec. To get it
1475 * working, we are using imx-fiq-pcm-audio, that
1476 * can handle those codecs. DMA is not possible in this
1480 ssi_private->fiq_params.irq = ssi_private->irq;
1481 ssi_private->fiq_params.base = ssi_private->ssi;
1482 ssi_private->fiq_params.dma_params_rx =
1483 &ssi_private->dma_params_rx;
1484 ssi_private->fiq_params.dma_params_tx =
1485 &ssi_private->dma_params_tx;
1487 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1491 ret = imx_pcm_dma_init(pdev);
1498 * If codec-handle property is missing from SSI node, we assume
1499 * that the machine driver uses new binding which does not require
1500 * SSI driver to trigger machine driver's probe.
1502 if (!of_get_property(np, "codec-handle", NULL)) {
1503 ssi_private->new_binding = true;
1507 /* Trigger the machine driver's probe function. The platform driver
1508 * name of the machine driver is taken from /compatible property of the
1509 * device tree. We also pass the address of the CPU DAI driver
1512 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1513 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1514 p = strrchr(sprop, ',');
1517 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1518 make_lowercase(name);
1521 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1522 if (IS_ERR(ssi_private->pdev)) {
1523 ret = PTR_ERR(ssi_private->pdev);
1524 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1529 if (ssi_private->imx_ac97)
1530 fsl_ssi_ac97_init();
1535 if (ssi_private->ssi_on_imx && !ssi_private->use_dma)
1536 imx_pcm_fiq_exit(pdev);
1539 fsl_ssi_debugfs_remove(ssi_private);
1542 snd_soc_unregister_component(&pdev->dev);
1545 device_remove_file(&pdev->dev, dev_attr);
1548 if (ssi_private->ssi_on_imx) {
1549 if (!IS_ERR(ssi_private->baudclk))
1550 clk_disable_unprepare(ssi_private->baudclk);
1551 clk_disable_unprepare(ssi_private->clk);
1555 if (ssi_private->irq_stats)
1556 irq_dispose_mapping(ssi_private->irq);
1561 static int fsl_ssi_remove(struct platform_device *pdev)
1563 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1565 fsl_ssi_debugfs_remove(ssi_private);
1567 if (!ssi_private->new_binding)
1568 platform_device_unregister(ssi_private->pdev);
1569 snd_soc_unregister_component(&pdev->dev);
1570 if (ssi_private->ssi_on_imx) {
1571 if (!IS_ERR(ssi_private->baudclk))
1572 clk_disable_unprepare(ssi_private->baudclk);
1573 clk_disable_unprepare(ssi_private->clk);
1575 if (ssi_private->irq_stats)
1576 irq_dispose_mapping(ssi_private->irq);
1581 static struct platform_driver fsl_ssi_driver = {
1583 .name = "fsl-ssi-dai",
1584 .owner = THIS_MODULE,
1585 .of_match_table = fsl_ssi_ids,
1587 .probe = fsl_ssi_probe,
1588 .remove = fsl_ssi_remove,
1591 module_platform_driver(fsl_ssi_driver);
1593 MODULE_ALIAS("platform:fsl-ssi-dai");
1594 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1595 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1596 MODULE_LICENSE("GPL v2");