2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/of_platform.h>
27 #include <linux/of_device.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/initval.h>
33 #include <sound/soc.h>
35 #include "davinci-pcm.h"
36 #include "davinci-mcasp.h"
39 * McASP register definitions
41 #define DAVINCI_MCASP_PID_REG 0x00
42 #define DAVINCI_MCASP_PWREMUMGT_REG 0x04
44 #define DAVINCI_MCASP_PFUNC_REG 0x10
45 #define DAVINCI_MCASP_PDIR_REG 0x14
46 #define DAVINCI_MCASP_PDOUT_REG 0x18
47 #define DAVINCI_MCASP_PDSET_REG 0x1c
49 #define DAVINCI_MCASP_PDCLR_REG 0x20
51 #define DAVINCI_MCASP_TLGC_REG 0x30
52 #define DAVINCI_MCASP_TLMR_REG 0x34
54 #define DAVINCI_MCASP_GBLCTL_REG 0x44
55 #define DAVINCI_MCASP_AMUTE_REG 0x48
56 #define DAVINCI_MCASP_LBCTL_REG 0x4c
58 #define DAVINCI_MCASP_TXDITCTL_REG 0x50
60 #define DAVINCI_MCASP_GBLCTLR_REG 0x60
61 #define DAVINCI_MCASP_RXMASK_REG 0x64
62 #define DAVINCI_MCASP_RXFMT_REG 0x68
63 #define DAVINCI_MCASP_RXFMCTL_REG 0x6c
65 #define DAVINCI_MCASP_ACLKRCTL_REG 0x70
66 #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
67 #define DAVINCI_MCASP_RXTDM_REG 0x78
68 #define DAVINCI_MCASP_EVTCTLR_REG 0x7c
70 #define DAVINCI_MCASP_RXSTAT_REG 0x80
71 #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
72 #define DAVINCI_MCASP_RXCLKCHK_REG 0x88
73 #define DAVINCI_MCASP_REVTCTL_REG 0x8c
75 #define DAVINCI_MCASP_GBLCTLX_REG 0xa0
76 #define DAVINCI_MCASP_TXMASK_REG 0xa4
77 #define DAVINCI_MCASP_TXFMT_REG 0xa8
78 #define DAVINCI_MCASP_TXFMCTL_REG 0xac
80 #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
81 #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
82 #define DAVINCI_MCASP_TXTDM_REG 0xb8
83 #define DAVINCI_MCASP_EVTCTLX_REG 0xbc
85 #define DAVINCI_MCASP_TXSTAT_REG 0xc0
86 #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
87 #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
88 #define DAVINCI_MCASP_XEVTCTL_REG 0xcc
90 /* Left(even TDM Slot) Channel Status Register File */
91 #define DAVINCI_MCASP_DITCSRA_REG 0x100
92 /* Right(odd TDM slot) Channel Status Register File */
93 #define DAVINCI_MCASP_DITCSRB_REG 0x118
94 /* Left(even TDM slot) User Data Register File */
95 #define DAVINCI_MCASP_DITUDRA_REG 0x130
96 /* Right(odd TDM Slot) User Data Register File */
97 #define DAVINCI_MCASP_DITUDRB_REG 0x148
99 /* Serializer n Control Register */
100 #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
101 #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
104 /* Transmit Buffer for Serializer n */
105 #define DAVINCI_MCASP_TXBUF_REG 0x200
106 /* Receive Buffer for Serializer n */
107 #define DAVINCI_MCASP_RXBUF_REG 0x280
109 /* McASP FIFO Registers */
110 #define DAVINCI_MCASP_WFIFOCTL (0x1010)
111 #define DAVINCI_MCASP_WFIFOSTS (0x1014)
112 #define DAVINCI_MCASP_RFIFOCTL (0x1018)
113 #define DAVINCI_MCASP_RFIFOSTS (0x101C)
114 #define MCASP_VER3_WFIFOCTL (0x1000)
115 #define MCASP_VER3_WFIFOSTS (0x1004)
116 #define MCASP_VER3_RFIFOCTL (0x1008)
117 #define MCASP_VER3_RFIFOSTS (0x100C)
120 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
123 #define MCASP_FREE BIT(0)
124 #define MCASP_SOFT BIT(1)
127 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
129 #define AXR(n) (1<<n)
130 #define PFUNC_AMUTE BIT(25)
131 #define ACLKX BIT(26)
132 #define AHCLKX BIT(27)
134 #define ACLKR BIT(29)
135 #define AHCLKR BIT(30)
139 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
141 #define AXR(n) (1<<n)
142 #define PDIR_AMUTE BIT(25)
143 #define ACLKX BIT(26)
144 #define AHCLKX BIT(27)
146 #define ACLKR BIT(29)
147 #define AHCLKR BIT(30)
151 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
153 #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
158 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
160 #define TXROT(val) (val)
162 #define TXSSZ(val) (val<<4)
163 #define TXPBIT(val) (val<<8)
164 #define TXPAD(val) (val<<13)
165 #define TXORD BIT(15)
166 #define FSXDLY(val) (val<<16)
169 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
171 #define RXROT(val) (val)
173 #define RXSSZ(val) (val<<4)
174 #define RXPBIT(val) (val<<8)
175 #define RXPAD(val) (val<<13)
176 #define RXORD BIT(15)
177 #define FSRDLY(val) (val<<16)
180 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
182 #define FSXPOL BIT(0)
184 #define FSXDUR BIT(4)
185 #define FSXMOD(val) (val<<7)
188 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
190 #define FSRPOL BIT(0)
192 #define FSRDUR BIT(4)
193 #define FSRMOD(val) (val<<7)
196 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
198 #define ACLKXDIV(val) (val)
199 #define ACLKXE BIT(5)
200 #define TX_ASYNC BIT(6)
201 #define ACLKXPOL BIT(7)
202 #define ACLKXDIV_MASK 0x1f
205 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
207 #define ACLKRDIV(val) (val)
208 #define ACLKRE BIT(5)
209 #define RX_ASYNC BIT(6)
210 #define ACLKRPOL BIT(7)
211 #define ACLKRDIV_MASK 0x1f
214 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
217 #define AHCLKXDIV(val) (val)
218 #define AHCLKXPOL BIT(14)
219 #define AHCLKXE BIT(15)
220 #define AHCLKXDIV_MASK 0xfff
223 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
226 #define AHCLKRDIV(val) (val)
227 #define AHCLKRPOL BIT(14)
228 #define AHCLKRE BIT(15)
229 #define AHCLKRDIV_MASK 0xfff
232 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
234 #define MODE(val) (val)
235 #define DISMOD (val)(val<<2)
236 #define TXSTATE BIT(4)
237 #define RXSTATE BIT(5)
239 #define SRMOD_INACTIVE 0
242 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
246 #define LBGENMODE(val) (val<<2)
249 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
251 #define TXTDMS(n) (1<<n)
254 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
256 #define RXTDMS(n) (1<<n)
259 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
261 #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
262 #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
263 #define RXSERCLR BIT(2) /* Receiver Serializer Clear */
264 #define RXSMRST BIT(3) /* Receiver State Machine Reset */
265 #define RXFSRST BIT(4) /* Frame Sync Generator Reset */
266 #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
267 #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
268 #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
269 #define TXSMRST BIT(11) /* Transmitter State Machine Reset */
270 #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
273 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
275 #define MUTENA(val) (val)
276 #define MUTEINPOL BIT(2)
277 #define MUTEINENA BIT(3)
278 #define MUTEIN BIT(4)
281 #define MUTEFSR BIT(7)
282 #define MUTEFSX BIT(8)
283 #define MUTEBADCLKR BIT(9)
284 #define MUTEBADCLKX BIT(10)
285 #define MUTERXDMAERR BIT(11)
286 #define MUTETXDMAERR BIT(12)
289 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
291 #define RXDATADMADIS BIT(0)
294 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
296 #define TXDATADMADIS BIT(0)
299 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
301 #define FIFO_ENABLE BIT(16)
302 #define NUMEVT_MASK (0xFF << 8)
303 #define NUMDMA_MASK (0xFF)
305 #define DAVINCI_MCASP_NUM_SERIALIZER 16
307 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
309 __raw_writel(__raw_readl(reg) | val, reg);
312 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
314 __raw_writel((__raw_readl(reg) & ~(val)), reg);
317 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
319 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
322 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
324 __raw_writel(val, reg);
327 static inline u32 mcasp_get_reg(void __iomem *reg)
329 return (unsigned int)__raw_readl(reg);
332 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
336 mcasp_set_bits(regs, val);
338 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
339 /* loop count is to avoid the lock-up */
340 for (i = 0; i < 1000; i++) {
341 if ((mcasp_get_reg(regs) & val) == val)
345 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
346 printk(KERN_ERR "GBLCTL write error\n");
349 static void mcasp_start_rx(struct davinci_audio_dev *dev)
351 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
352 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
353 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
354 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
356 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
357 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
358 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
360 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
361 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
364 static void mcasp_start_tx(struct davinci_audio_dev *dev)
369 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
370 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
371 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
372 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
374 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
375 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
376 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
377 for (i = 0; i < dev->num_serializer; i++) {
378 if (dev->serial_dir[i] == TX_MODE) {
384 /* wait for TX ready */
386 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
387 TXSTATE) && (cnt < 100000))
390 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
393 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
395 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
396 if (dev->txnumevt) { /* enable FIFO */
397 switch (dev->version) {
398 case MCASP_VERSION_3:
399 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
401 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
405 mcasp_clr_bits(dev->base +
406 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
407 mcasp_set_bits(dev->base +
408 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
413 if (dev->rxnumevt) { /* enable FIFO */
414 switch (dev->version) {
415 case MCASP_VERSION_3:
416 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
418 mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
422 mcasp_clr_bits(dev->base +
423 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
424 mcasp_set_bits(dev->base +
425 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
432 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
434 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
435 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
438 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
440 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
441 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
444 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
446 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
447 if (dev->txnumevt) { /* disable FIFO */
448 switch (dev->version) {
449 case MCASP_VERSION_3:
450 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
454 mcasp_clr_bits(dev->base +
455 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
460 if (dev->rxnumevt) { /* disable FIFO */
461 switch (dev->version) {
462 case MCASP_VERSION_3:
463 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
468 mcasp_clr_bits(dev->base +
469 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
476 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
479 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
480 void __iomem *base = dev->base;
482 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
483 case SND_SOC_DAIFMT_DSP_B:
484 case SND_SOC_DAIFMT_AC97:
485 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
486 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
489 /* configure a full-word SYNC pulse (LRCLK) */
490 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
491 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
493 /* make 1st data bit occur one ACLK cycle after the frame sync */
494 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
495 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
499 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
500 case SND_SOC_DAIFMT_CBS_CFS:
501 /* codec is clock and frame slave */
502 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
503 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
505 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
506 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
508 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, ACLKX | AFSX);
510 case SND_SOC_DAIFMT_CBM_CFS:
511 /* codec is clock master and frame slave */
512 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
513 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
515 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
516 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
518 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
520 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
523 case SND_SOC_DAIFMT_CBM_CFM:
524 /* codec is clock and frame master */
525 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
526 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
528 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
529 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
531 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
532 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
539 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
540 case SND_SOC_DAIFMT_IB_NF:
541 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
542 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
544 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
545 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
548 case SND_SOC_DAIFMT_NB_IF:
549 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
550 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
552 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
553 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
556 case SND_SOC_DAIFMT_IB_IF:
557 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
558 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
560 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
561 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
564 case SND_SOC_DAIFMT_NB_NF:
565 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
566 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
568 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
569 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
579 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
581 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
584 case 0: /* MCLK divider */
585 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
586 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
587 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
588 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
591 case 1: /* BCLK divider */
592 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
593 ACLKXDIV(div - 1), ACLKXDIV_MASK);
594 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
595 ACLKRDIV(div - 1), ACLKRDIV_MASK);
598 case 2: /* BCLK/LRCLK ratio */
599 dev->bclk_lrclk_ratio = div;
609 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
610 unsigned int freq, int dir)
612 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
614 if (dir == SND_SOC_CLOCK_OUT) {
615 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
616 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
617 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
619 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
620 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
621 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
627 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
631 u32 rotate = (word_length / 4) & 0x7;
632 u32 mask = (1ULL << word_length) - 1;
635 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
636 * callback, take it into account here. That allows us to for example
637 * send 32 bits per channel to the codec, while only 16 of them carry
639 * The clock ratio is given for a full period of data (for I2S format
640 * both left and right channels), so it has to be divided by number of
641 * tdm-slots (for I2S - divided by 2).
643 if (dev->bclk_lrclk_ratio)
644 word_length = dev->bclk_lrclk_ratio / dev->tdm_slots;
646 /* mapping of the XSSZ bit-field as described in the datasheet */
647 fmt = (word_length >> 1) - 1;
649 if (dev->op_mode != DAVINCI_MCASP_DIT_MODE) {
650 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
651 RXSSZ(fmt), RXSSZ(0x0F));
652 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
653 TXSSZ(fmt), TXSSZ(0x0F));
654 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
655 TXROT(rotate), TXROT(7));
656 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
657 RXROT(rotate), RXROT(7));
658 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG,
662 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
667 static int davinci_hw_common_param(struct davinci_audio_dev *dev, int stream,
674 u8 slots = dev->tdm_slots;
675 u8 max_active_serializers = (channels + slots - 1) / slots;
676 /* Default configuration */
677 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
679 /* All PINS as McASP */
680 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
682 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
683 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
684 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
687 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
688 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
692 for (i = 0; i < dev->num_serializer; i++) {
693 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
695 if (dev->serial_dir[i] == TX_MODE &&
696 tx_ser < max_active_serializers) {
697 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
700 } else if (dev->serial_dir[i] == RX_MODE &&
701 rx_ser < max_active_serializers) {
702 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
706 mcasp_mod_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
707 SRMOD_INACTIVE, SRMOD_MASK);
711 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
716 if (ser < max_active_serializers) {
717 dev_warn(dev->dev, "stream has more channels (%d) than are "
718 "enabled in mcasp (%d)\n", channels, ser * slots);
722 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
723 if (dev->txnumevt * tx_ser > 64)
726 switch (dev->version) {
727 case MCASP_VERSION_3:
728 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
730 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
731 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
734 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
735 tx_ser, NUMDMA_MASK);
736 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
737 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
741 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
742 if (dev->rxnumevt * rx_ser > 64)
744 switch (dev->version) {
745 case MCASP_VERSION_3:
746 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
748 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
749 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
752 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
753 rx_ser, NUMDMA_MASK);
754 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
755 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
762 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
767 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
768 for (i = 0; i < active_slots; i++)
771 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
773 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
774 /* bit stream is MSB first with no delay */
776 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
777 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
779 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
780 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
781 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
783 printk(KERN_ERR "playback tdm slot %d not supported\n",
786 /* bit stream is MSB first with no delay */
788 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
789 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
791 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
792 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
793 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
795 printk(KERN_ERR "capture tdm slot %d not supported\n",
801 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
803 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
805 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
806 TXROT(6) | TXSSZ(15));
808 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
809 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
810 AFSXE | FSXMOD(0x180));
812 /* Set the TX tdm : for all the slots */
813 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
815 /* Set the TX clock controls : div = 1 and internal */
816 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
819 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
821 /* Only 44100 and 48000 are valid, both have the same setting */
822 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
825 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
828 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
829 struct snd_pcm_hw_params *params,
830 struct snd_soc_dai *cpu_dai)
832 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
833 struct davinci_pcm_dma_params *dma_params =
834 &dev->dma_params[substream->stream];
837 u8 slots = dev->tdm_slots;
838 u8 active_serializers;
840 struct snd_interval *pcm_channels = hw_param_interval(params,
841 SNDRV_PCM_HW_PARAM_CHANNELS);
842 channels = pcm_channels->min;
844 active_serializers = (channels + slots - 1) / slots;
846 if (davinci_hw_common_param(dev, substream->stream, channels) == -EINVAL)
848 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
849 fifo_level = dev->txnumevt * active_serializers;
851 fifo_level = dev->rxnumevt * active_serializers;
853 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
854 davinci_hw_dit_param(dev);
856 davinci_hw_param(dev, substream->stream);
858 switch (params_format(params)) {
859 case SNDRV_PCM_FORMAT_U8:
860 case SNDRV_PCM_FORMAT_S8:
861 dma_params->data_type = 1;
865 case SNDRV_PCM_FORMAT_U16_LE:
866 case SNDRV_PCM_FORMAT_S16_LE:
867 dma_params->data_type = 2;
871 case SNDRV_PCM_FORMAT_U24_3LE:
872 case SNDRV_PCM_FORMAT_S24_3LE:
873 dma_params->data_type = 3;
877 case SNDRV_PCM_FORMAT_U24_LE:
878 case SNDRV_PCM_FORMAT_S24_LE:
879 case SNDRV_PCM_FORMAT_U32_LE:
880 case SNDRV_PCM_FORMAT_S32_LE:
881 dma_params->data_type = 4;
886 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
890 if (dev->version == MCASP_VERSION_2 && !fifo_level)
891 dma_params->acnt = 4;
893 dma_params->acnt = dma_params->data_type;
895 dma_params->fifo_level = fifo_level;
896 davinci_config_channel_size(dev, word_length);
901 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
902 int cmd, struct snd_soc_dai *cpu_dai)
904 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
908 case SNDRV_PCM_TRIGGER_RESUME:
909 case SNDRV_PCM_TRIGGER_START:
910 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
911 ret = pm_runtime_get_sync(dev->dev);
912 if (IS_ERR_VALUE(ret))
913 dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
914 davinci_mcasp_start(dev, substream->stream);
917 case SNDRV_PCM_TRIGGER_SUSPEND:
918 davinci_mcasp_stop(dev, substream->stream);
919 ret = pm_runtime_put_sync(dev->dev);
920 if (IS_ERR_VALUE(ret))
921 dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
924 case SNDRV_PCM_TRIGGER_STOP:
925 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
926 davinci_mcasp_stop(dev, substream->stream);
936 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
937 struct snd_soc_dai *dai)
939 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
941 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
945 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
946 .startup = davinci_mcasp_startup,
947 .trigger = davinci_mcasp_trigger,
948 .hw_params = davinci_mcasp_hw_params,
949 .set_fmt = davinci_mcasp_set_dai_fmt,
950 .set_clkdiv = davinci_mcasp_set_clkdiv,
951 .set_sysclk = davinci_mcasp_set_sysclk,
954 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
955 SNDRV_PCM_FMTBIT_U8 | \
956 SNDRV_PCM_FMTBIT_S16_LE | \
957 SNDRV_PCM_FMTBIT_U16_LE | \
958 SNDRV_PCM_FMTBIT_S24_LE | \
959 SNDRV_PCM_FMTBIT_U24_LE | \
960 SNDRV_PCM_FMTBIT_S24_3LE | \
961 SNDRV_PCM_FMTBIT_U24_3LE | \
962 SNDRV_PCM_FMTBIT_S32_LE | \
963 SNDRV_PCM_FMTBIT_U32_LE)
965 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
967 .name = "davinci-mcasp.0",
970 .channels_max = 32 * 16,
971 .rates = DAVINCI_MCASP_RATES,
972 .formats = DAVINCI_MCASP_PCM_FMTS,
976 .channels_max = 32 * 16,
977 .rates = DAVINCI_MCASP_RATES,
978 .formats = DAVINCI_MCASP_PCM_FMTS,
980 .ops = &davinci_mcasp_dai_ops,
988 .rates = DAVINCI_MCASP_RATES,
989 .formats = DAVINCI_MCASP_PCM_FMTS,
991 .ops = &davinci_mcasp_dai_ops,
996 static const struct snd_soc_component_driver davinci_mcasp_component = {
997 .name = "davinci-mcasp",
1000 static const struct of_device_id mcasp_dt_ids[] = {
1002 .compatible = "ti,dm646x-mcasp-audio",
1003 .data = (void *)MCASP_VERSION_1,
1006 .compatible = "ti,da830-mcasp-audio",
1007 .data = (void *)MCASP_VERSION_2,
1010 .compatible = "ti,omap2-mcasp-audio",
1011 .data = (void *)MCASP_VERSION_3,
1015 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1017 static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
1018 struct platform_device *pdev)
1020 struct device_node *np = pdev->dev.of_node;
1021 struct snd_platform_data *pdata = NULL;
1022 const struct of_device_id *match =
1023 of_match_device(of_match_ptr(mcasp_dt_ids), &pdev->dev);
1025 const u32 *of_serial_dir32;
1030 if (pdev->dev.platform_data) {
1031 pdata = pdev->dev.platform_data;
1034 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1040 /* control shouldn't reach here. something is wrong */
1046 pdata->version = (u8)((int)match->data);
1048 ret = of_property_read_u32(np, "op-mode", &val);
1050 pdata->op_mode = val;
1052 ret = of_property_read_u32(np, "tdm-slots", &val);
1054 if (val < 2 || val > 32) {
1056 "tdm-slots must be in rage [2-32]\n");
1061 pdata->tdm_slots = val;
1064 ret = of_property_read_u32(np, "num-serializer", &val);
1066 pdata->num_serializer = val;
1068 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1070 if (val != pdata->num_serializer) {
1072 "num-serializer(%d) != serial-dir size(%d)\n",
1073 pdata->num_serializer, val);
1078 if (of_serial_dir32) {
1079 of_serial_dir = devm_kzalloc(&pdev->dev,
1080 (sizeof(*of_serial_dir) * val),
1082 if (!of_serial_dir) {
1087 for (i = 0; i < pdata->num_serializer; i++)
1088 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1090 pdata->serial_dir = of_serial_dir;
1093 ret = of_property_read_u32(np, "tx-num-evt", &val);
1095 pdata->txnumevt = val;
1097 ret = of_property_read_u32(np, "rx-num-evt", &val);
1099 pdata->rxnumevt = val;
1101 ret = of_property_read_u32(np, "sram-size-playback", &val);
1103 pdata->sram_size_playback = val;
1105 ret = of_property_read_u32(np, "sram-size-capture", &val);
1107 pdata->sram_size_capture = val;
1113 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1120 static int davinci_mcasp_probe(struct platform_device *pdev)
1122 struct davinci_pcm_dma_params *dma_data;
1123 struct resource *mem, *ioarea, *res;
1124 struct snd_platform_data *pdata;
1125 struct davinci_audio_dev *dev;
1128 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1129 dev_err(&pdev->dev, "No platform data supplied\n");
1133 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
1138 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1140 dev_err(&pdev->dev, "no platform data\n");
1144 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1146 dev_err(&pdev->dev, "no mem resource?\n");
1150 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1151 resource_size(mem), pdev->name);
1153 dev_err(&pdev->dev, "Audio region already claimed\n");
1157 pm_runtime_enable(&pdev->dev);
1159 ret = pm_runtime_get_sync(&pdev->dev);
1160 if (IS_ERR_VALUE(ret)) {
1161 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1165 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1167 dev_err(&pdev->dev, "ioremap failed\n");
1169 goto err_release_clk;
1172 dev->op_mode = pdata->op_mode;
1173 dev->tdm_slots = pdata->tdm_slots;
1174 dev->num_serializer = pdata->num_serializer;
1175 dev->serial_dir = pdata->serial_dir;
1176 dev->version = pdata->version;
1177 dev->txnumevt = pdata->txnumevt;
1178 dev->rxnumevt = pdata->rxnumevt;
1179 dev->dev = &pdev->dev;
1181 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1182 dma_data->asp_chan_q = pdata->asp_chan_q;
1183 dma_data->ram_chan_q = pdata->ram_chan_q;
1184 dma_data->sram_pool = pdata->sram_pool;
1185 dma_data->sram_size = pdata->sram_size_playback;
1186 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
1189 /* first TX, then RX */
1190 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1192 dev_err(&pdev->dev, "no DMA resource\n");
1194 goto err_release_clk;
1197 dma_data->channel = res->start;
1199 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1200 dma_data->asp_chan_q = pdata->asp_chan_q;
1201 dma_data->ram_chan_q = pdata->ram_chan_q;
1202 dma_data->sram_pool = pdata->sram_pool;
1203 dma_data->sram_size = pdata->sram_size_capture;
1204 dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
1207 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1209 dev_err(&pdev->dev, "no DMA resource\n");
1211 goto err_release_clk;
1214 dma_data->channel = res->start;
1215 dev_set_drvdata(&pdev->dev, dev);
1216 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1217 &davinci_mcasp_dai[pdata->op_mode], 1);
1220 goto err_release_clk;
1222 ret = davinci_soc_platform_register(&pdev->dev);
1224 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1225 goto err_unregister_component;
1230 err_unregister_component:
1231 snd_soc_unregister_component(&pdev->dev);
1233 pm_runtime_put_sync(&pdev->dev);
1234 pm_runtime_disable(&pdev->dev);
1238 static int davinci_mcasp_remove(struct platform_device *pdev)
1241 snd_soc_unregister_component(&pdev->dev);
1242 davinci_soc_platform_unregister(&pdev->dev);
1244 pm_runtime_put_sync(&pdev->dev);
1245 pm_runtime_disable(&pdev->dev);
1250 static struct platform_driver davinci_mcasp_driver = {
1251 .probe = davinci_mcasp_probe,
1252 .remove = davinci_mcasp_remove,
1254 .name = "davinci-mcasp",
1255 .owner = THIS_MODULE,
1256 .of_match_table = of_match_ptr(mcasp_dt_ids),
1260 module_platform_driver(davinci_mcasp_driver);
1262 MODULE_AUTHOR("Steve Chen");
1263 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1264 MODULE_LICENSE("GPL");