2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/device.h>
15 #include <linux/delay.h>
17 #include <linux/clk.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/initval.h>
23 #include <sound/soc.h>
25 #include "davinci-pcm.h"
29 * NOTE: terminology here is confusing.
31 * - This driver supports the "Audio Serial Port" (ASP),
32 * found on dm6446, dm355, and other DaVinci chips.
34 * - But it labels it a "Multi-channel Buffered Serial Port"
35 * (McBSP) as on older chips like the dm642 ... which was
36 * backward-compatible, possibly explaining that confusion.
38 * - OMAP chips have a controller called McBSP, which is
39 * incompatible with the DaVinci flavor of McBSP.
41 * - Newer DaVinci chips have a controller called McASP,
42 * incompatible with ASP and with either McBSP.
44 * In short: this uses ASP to implement I2S, not McBSP.
45 * And it won't be the only DaVinci implemention of I2S.
47 #define DAVINCI_MCBSP_DRR_REG 0x00
48 #define DAVINCI_MCBSP_DXR_REG 0x04
49 #define DAVINCI_MCBSP_SPCR_REG 0x08
50 #define DAVINCI_MCBSP_RCR_REG 0x0c
51 #define DAVINCI_MCBSP_XCR_REG 0x10
52 #define DAVINCI_MCBSP_SRGR_REG 0x14
53 #define DAVINCI_MCBSP_PCR_REG 0x24
55 #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
56 #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
57 #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
58 #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
59 #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
60 #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
61 #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
63 #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
64 #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
65 #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
66 #define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
67 #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
69 #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
70 #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
71 #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
72 #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
73 #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
75 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
76 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
77 #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
79 #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
80 #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
81 #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
82 #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
83 #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
84 #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
85 #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
86 #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
87 #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
90 DAVINCI_MCBSP_WORD_8 = 0,
91 DAVINCI_MCBSP_WORD_12,
92 DAVINCI_MCBSP_WORD_16,
93 DAVINCI_MCBSP_WORD_20,
94 DAVINCI_MCBSP_WORD_24,
95 DAVINCI_MCBSP_WORD_32,
98 static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
99 .name = "I2S PCM Stereo out",
102 static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
103 .name = "I2S PCM Stereo in",
106 struct davinci_mcbsp_dev {
113 struct davinci_pcm_dma_params *dma_params[2];
116 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
119 __raw_writel(val, dev->base + reg);
122 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
124 return __raw_readl(dev->base + reg);
127 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
129 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
130 /* The clock needs to toggle to complete reset.
131 * So, fake it by toggling the clk polarity.
133 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
134 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
137 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
138 struct snd_pcm_substream *substream)
140 struct snd_soc_pcm_runtime *rtd = substream->private_data;
141 struct snd_soc_device *socdev = rtd->socdev;
142 struct snd_soc_platform *platform = socdev->card->platform;
143 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
145 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
146 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
148 /* start off disabled */
149 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
151 toggle_clock(dev, playback);
153 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
154 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
155 /* Start the sample generator */
156 spcr |= DAVINCI_MCBSP_SPCR_GRST;
157 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
161 /* Stop the DMA to avoid data loss */
162 /* while the transmitter is out of reset to handle XSYNCERR */
163 if (platform->pcm_ops->trigger) {
164 int ret = platform->pcm_ops->trigger(substream,
165 SNDRV_PCM_TRIGGER_STOP);
167 printk(KERN_DEBUG "Playback DMA stop failed\n");
170 /* Enable the transmitter */
171 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
172 spcr |= DAVINCI_MCBSP_SPCR_XRST;
173 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
175 /* wait for any unexpected frame sync error to occur */
178 /* Disable the transmitter to clear any outstanding XSYNCERR */
179 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
180 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
181 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
182 toggle_clock(dev, playback);
184 /* Restart the DMA */
185 if (platform->pcm_ops->trigger) {
186 int ret = platform->pcm_ops->trigger(substream,
187 SNDRV_PCM_TRIGGER_START);
189 printk(KERN_DEBUG "Playback DMA start failed\n");
193 /* Enable transmitter or receiver */
194 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
197 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
198 /* Start frame sync */
199 spcr |= DAVINCI_MCBSP_SPCR_FRST;
201 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
204 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
208 /* Reset transmitter/receiver and sample rate/frame sync generators */
209 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
210 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
211 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
212 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
213 toggle_clock(dev, playback);
216 static int davinci_i2s_startup(struct snd_pcm_substream *substream,
217 struct snd_soc_dai *cpu_dai)
219 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
220 cpu_dai->dma_data = dev->dma_params[substream->stream];
224 #define DEFAULT_BITPERSAMPLE 16
226 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
229 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
232 srgr = DAVINCI_MCBSP_SRGR_FSGM |
233 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
234 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
236 /* set master/slave audio interface */
237 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
238 case SND_SOC_DAIFMT_CBS_CFS:
240 pcr = DAVINCI_MCBSP_PCR_FSXM |
241 DAVINCI_MCBSP_PCR_FSRM |
242 DAVINCI_MCBSP_PCR_CLKXM |
243 DAVINCI_MCBSP_PCR_CLKRM;
245 case SND_SOC_DAIFMT_CBM_CFS:
246 /* McBSP CLKR pin is the input for the Sample Rate Generator.
247 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
248 pcr = DAVINCI_MCBSP_PCR_SCLKME |
249 DAVINCI_MCBSP_PCR_FSXM |
250 DAVINCI_MCBSP_PCR_FSRM;
252 case SND_SOC_DAIFMT_CBM_CFM:
253 /* codec is master */
257 printk(KERN_ERR "%s:bad master\n", __func__);
261 /* interface format */
262 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
263 case SND_SOC_DAIFMT_I2S:
264 /* Davinci doesn't support TRUE I2S, but some codecs will have
265 * the left and right channels contiguous. This allows
266 * dsp_a mode to be used with an inverted normal frame clk.
267 * If your codec is master and does not have contiguous
268 * channels, then you will have sound on only one channel.
269 * Try using a different mode, or codec as slave.
271 * The TLV320AIC33 is an example of a codec where this works.
272 * It has a variable bit clock frequency allowing it to have
273 * valid data on every bit clock.
275 * The TLV320AIC23 is an example of a codec where this does not
276 * work. It has a fixed bit clock frequency with progressively
277 * more empty bit clock slots between channels as the sample
280 fmt ^= SND_SOC_DAIFMT_NB_IF;
281 case SND_SOC_DAIFMT_DSP_A:
282 dev->mode = MOD_DSP_A;
284 case SND_SOC_DAIFMT_DSP_B:
285 dev->mode = MOD_DSP_B;
288 printk(KERN_ERR "%s:bad format\n", __func__);
292 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
293 case SND_SOC_DAIFMT_NB_NF:
294 /* CLKRP Receive clock polarity,
295 * 1 - sampled on rising edge of CLKR
296 * valid on rising edge
297 * CLKXP Transmit clock polarity,
298 * 1 - clocked on falling edge of CLKX
299 * valid on rising edge
300 * FSRP Receive frame sync pol, 0 - active high
301 * FSXP Transmit frame sync pol, 0 - active high
303 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
305 case SND_SOC_DAIFMT_IB_IF:
306 /* CLKRP Receive clock polarity,
307 * 0 - sampled on falling edge of CLKR
308 * valid on falling edge
309 * CLKXP Transmit clock polarity,
310 * 0 - clocked on rising edge of CLKX
311 * valid on falling edge
312 * FSRP Receive frame sync pol, 1 - active low
313 * FSXP Transmit frame sync pol, 1 - active low
315 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
317 case SND_SOC_DAIFMT_NB_IF:
318 /* CLKRP Receive clock polarity,
319 * 1 - sampled on rising edge of CLKR
320 * valid on rising edge
321 * CLKXP Transmit clock polarity,
322 * 1 - clocked on falling edge of CLKX
323 * valid on rising edge
324 * FSRP Receive frame sync pol, 1 - active low
325 * FSXP Transmit frame sync pol, 1 - active low
327 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
328 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
330 case SND_SOC_DAIFMT_IB_NF:
331 /* CLKRP Receive clock polarity,
332 * 0 - sampled on falling edge of CLKR
333 * valid on falling edge
334 * CLKXP Transmit clock polarity,
335 * 0 - clocked on rising edge of CLKX
336 * valid on falling edge
337 * FSRP Receive frame sync pol, 0 - active high
338 * FSXP Transmit frame sync pol, 0 - active high
344 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
346 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
350 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
351 struct snd_pcm_hw_params *params,
352 struct snd_soc_dai *dai)
354 struct snd_soc_pcm_runtime *rtd = substream->private_data;
355 struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
356 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
357 struct snd_interval *i = NULL;
358 int mcbsp_word_length;
359 unsigned int rcr, xcr, srgr;
362 /* general line settings */
363 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
364 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
365 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
366 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
368 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
369 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
372 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
373 srgr = DAVINCI_MCBSP_SRGR_FSGM;
374 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
376 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
377 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
378 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
380 rcr = DAVINCI_MCBSP_RCR_RFIG;
381 xcr = DAVINCI_MCBSP_XCR_XFIG;
382 if (dev->mode == MOD_DSP_B) {
383 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
384 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
386 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
387 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
389 /* Determine xfer data type */
390 switch (params_format(params)) {
391 case SNDRV_PCM_FORMAT_S8:
392 dma_params->data_type = 1;
393 mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
395 case SNDRV_PCM_FORMAT_S16_LE:
396 dma_params->data_type = 2;
397 mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
399 case SNDRV_PCM_FORMAT_S32_LE:
400 dma_params->data_type = 4;
401 mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
404 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
408 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(1);
409 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(1);
411 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
412 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
413 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
414 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
416 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
417 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
419 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
423 static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
424 struct snd_soc_dai *dai)
426 struct snd_soc_pcm_runtime *rtd = substream->private_data;
427 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
428 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
429 davinci_mcbsp_stop(dev, playback);
430 if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) {
431 /* codec is master */
432 davinci_mcbsp_start(dev, substream);
437 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
438 struct snd_soc_dai *dai)
440 struct snd_soc_pcm_runtime *rtd = substream->private_data;
441 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
443 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
444 if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0)
445 return 0; /* return if codec is master */
448 case SNDRV_PCM_TRIGGER_START:
449 case SNDRV_PCM_TRIGGER_RESUME:
450 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
451 davinci_mcbsp_start(dev, substream);
453 case SNDRV_PCM_TRIGGER_STOP:
454 case SNDRV_PCM_TRIGGER_SUSPEND:
455 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
456 davinci_mcbsp_stop(dev, playback);
464 static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
465 struct snd_soc_dai *dai)
467 struct snd_soc_pcm_runtime *rtd = substream->private_data;
468 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
469 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
470 davinci_mcbsp_stop(dev, playback);
473 #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
475 static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
476 .startup = davinci_i2s_startup,
477 .shutdown = davinci_i2s_shutdown,
478 .prepare = davinci_i2s_prepare,
479 .trigger = davinci_i2s_trigger,
480 .hw_params = davinci_i2s_hw_params,
481 .set_fmt = davinci_i2s_set_dai_fmt,
485 struct snd_soc_dai davinci_i2s_dai = {
486 .name = "davinci-i2s",
491 .rates = DAVINCI_I2S_RATES,
492 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
496 .rates = DAVINCI_I2S_RATES,
497 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
498 .ops = &davinci_i2s_dai_ops,
501 EXPORT_SYMBOL_GPL(davinci_i2s_dai);
503 static int davinci_i2s_probe(struct platform_device *pdev)
505 struct snd_platform_data *pdata = pdev->dev.platform_data;
506 struct davinci_mcbsp_dev *dev;
507 struct resource *mem, *ioarea, *res;
510 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
512 dev_err(&pdev->dev, "no mem resource?\n");
516 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
519 dev_err(&pdev->dev, "McBSP region already claimed\n");
523 dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
526 goto err_release_region;
529 dev->clk = clk_get(&pdev->dev, pdata->clk_name);
530 if (IS_ERR(dev->clk)) {
534 clk_enable(dev->clk);
536 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
538 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
539 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
540 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
542 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
543 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
544 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
546 /* first TX, then RX */
547 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
549 dev_err(&pdev->dev, "no DMA resource\n");
553 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = res->start;
555 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
557 dev_err(&pdev->dev, "no DMA resource\n");
561 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = res->start;
563 davinci_i2s_dai.private_data = dev;
564 ret = snd_soc_register_dai(&davinci_i2s_dai);
573 release_mem_region(mem->start, (mem->end - mem->start) + 1);
578 static int davinci_i2s_remove(struct platform_device *pdev)
580 struct davinci_mcbsp_dev *dev = davinci_i2s_dai.private_data;
581 struct resource *mem;
583 snd_soc_unregister_dai(&davinci_i2s_dai);
584 clk_disable(dev->clk);
588 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
589 release_mem_region(mem->start, (mem->end - mem->start) + 1);
594 static struct platform_driver davinci_mcbsp_driver = {
595 .probe = davinci_i2s_probe,
596 .remove = davinci_i2s_remove,
598 .name = "davinci-asp",
599 .owner = THIS_MODULE,
603 static int __init davinci_i2s_init(void)
605 return platform_driver_register(&davinci_mcbsp_driver);
607 module_init(davinci_i2s_init);
609 static void __exit davinci_i2s_exit(void)
611 platform_driver_unregister(&davinci_mcbsp_driver);
613 module_exit(davinci_i2s_exit);
615 MODULE_AUTHOR("Vladimir Barinov");
616 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
617 MODULE_LICENSE("GPL");