2 * wm_adsp.c -- Wolfson ADSP support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/firmware.h>
18 #include <linux/list.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/workqueue.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/jack.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
33 #include <linux/mfd/arizona/registers.h>
38 #define adsp_crit(_dsp, fmt, ...) \
39 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
40 #define adsp_err(_dsp, fmt, ...) \
41 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
42 #define adsp_warn(_dsp, fmt, ...) \
43 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
44 #define adsp_info(_dsp, fmt, ...) \
45 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
46 #define adsp_dbg(_dsp, fmt, ...) \
47 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
49 #define ADSP1_CONTROL_1 0x00
50 #define ADSP1_CONTROL_2 0x02
51 #define ADSP1_CONTROL_3 0x03
52 #define ADSP1_CONTROL_4 0x04
53 #define ADSP1_CONTROL_5 0x06
54 #define ADSP1_CONTROL_6 0x07
55 #define ADSP1_CONTROL_7 0x08
56 #define ADSP1_CONTROL_8 0x09
57 #define ADSP1_CONTROL_9 0x0A
58 #define ADSP1_CONTROL_10 0x0B
59 #define ADSP1_CONTROL_11 0x0C
60 #define ADSP1_CONTROL_12 0x0D
61 #define ADSP1_CONTROL_13 0x0F
62 #define ADSP1_CONTROL_14 0x10
63 #define ADSP1_CONTROL_15 0x11
64 #define ADSP1_CONTROL_16 0x12
65 #define ADSP1_CONTROL_17 0x13
66 #define ADSP1_CONTROL_18 0x14
67 #define ADSP1_CONTROL_19 0x16
68 #define ADSP1_CONTROL_20 0x17
69 #define ADSP1_CONTROL_21 0x18
70 #define ADSP1_CONTROL_22 0x1A
71 #define ADSP1_CONTROL_23 0x1B
72 #define ADSP1_CONTROL_24 0x1C
73 #define ADSP1_CONTROL_25 0x1E
74 #define ADSP1_CONTROL_26 0x20
75 #define ADSP1_CONTROL_27 0x21
76 #define ADSP1_CONTROL_28 0x22
77 #define ADSP1_CONTROL_29 0x23
78 #define ADSP1_CONTROL_30 0x24
79 #define ADSP1_CONTROL_31 0x26
84 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
85 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
92 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
93 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
94 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
95 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
96 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
97 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
98 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
99 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
100 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
101 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
102 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
103 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
104 #define ADSP1_START 0x0001 /* DSP1_START */
105 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
106 #define ADSP1_START_SHIFT 0 /* DSP1_START */
107 #define ADSP1_START_WIDTH 1 /* DSP1_START */
112 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
113 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
114 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
116 #define ADSP2_CONTROL 0x0
117 #define ADSP2_CLOCKING 0x1
118 #define ADSP2_STATUS1 0x4
119 #define ADSP2_WDMA_CONFIG_1 0x30
120 #define ADSP2_WDMA_CONFIG_2 0x31
121 #define ADSP2_RDMA_CONFIG_1 0x34
127 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
128 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
129 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
130 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
131 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
132 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
133 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
134 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
135 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
136 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
137 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
138 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
139 #define ADSP2_START 0x0001 /* DSP1_START */
140 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
141 #define ADSP2_START_SHIFT 0 /* DSP1_START */
142 #define ADSP2_START_WIDTH 1 /* DSP1_START */
147 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
148 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
149 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
154 #define ADSP2_RAM_RDY 0x0001
155 #define ADSP2_RAM_RDY_MASK 0x0001
156 #define ADSP2_RAM_RDY_SHIFT 0
157 #define ADSP2_RAM_RDY_WIDTH 1
160 struct list_head list;
164 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
165 struct list_head *list)
167 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
172 buf->buf = kmemdup(src, len, GFP_KERNEL | GFP_DMA);
179 list_add_tail(&buf->list, list);
184 static void wm_adsp_buf_free(struct list_head *list)
186 while (!list_empty(list)) {
187 struct wm_adsp_buf *buf = list_first_entry(list,
190 list_del(&buf->list);
196 #define WM_ADSP_NUM_FW 4
198 #define WM_ADSP_FW_MBC_VSS 0
199 #define WM_ADSP_FW_TX 1
200 #define WM_ADSP_FW_TX_SPK 2
201 #define WM_ADSP_FW_RX_ANC 3
203 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
204 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
205 [WM_ADSP_FW_TX] = "Tx",
206 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
207 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
212 } wm_adsp_fw[WM_ADSP_NUM_FW] = {
213 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
214 [WM_ADSP_FW_TX] = { .file = "tx" },
215 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
216 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
219 struct wm_coeff_ctl_ops {
220 int (*xget)(struct snd_kcontrol *kcontrol,
221 struct snd_ctl_elem_value *ucontrol);
222 int (*xput)(struct snd_kcontrol *kcontrol,
223 struct snd_ctl_elem_value *ucontrol);
224 int (*xinfo)(struct snd_kcontrol *kcontrol,
225 struct snd_ctl_elem_info *uinfo);
228 struct wm_coeff_ctl {
230 struct wm_adsp_alg_region region;
231 struct wm_coeff_ctl_ops ops;
232 struct wm_adsp *adsp;
234 unsigned int enabled:1;
235 struct list_head list;
239 struct snd_kcontrol *kcontrol;
242 static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
243 struct snd_ctl_elem_value *ucontrol)
245 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
246 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
247 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
249 ucontrol->value.integer.value[0] = adsp[e->shift_l].fw;
254 static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
255 struct snd_ctl_elem_value *ucontrol)
257 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
258 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
259 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
261 if (ucontrol->value.integer.value[0] == adsp[e->shift_l].fw)
264 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
267 if (adsp[e->shift_l].running)
270 adsp[e->shift_l].fw = ucontrol->value.integer.value[0];
275 static const struct soc_enum wm_adsp_fw_enum[] = {
276 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
277 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
278 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
279 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
282 const struct snd_kcontrol_new wm_adsp1_fw_controls[] = {
283 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
284 wm_adsp_fw_get, wm_adsp_fw_put),
285 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
286 wm_adsp_fw_get, wm_adsp_fw_put),
287 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
288 wm_adsp_fw_get, wm_adsp_fw_put),
290 EXPORT_SYMBOL_GPL(wm_adsp1_fw_controls);
292 #if IS_ENABLED(CONFIG_SND_SOC_ARIZONA)
293 static const struct soc_enum wm_adsp2_rate_enum[] = {
294 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1,
295 ARIZONA_DSP1_RATE_SHIFT, 0xf,
296 ARIZONA_RATE_ENUM_SIZE,
297 arizona_rate_text, arizona_rate_val),
298 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1,
299 ARIZONA_DSP1_RATE_SHIFT, 0xf,
300 ARIZONA_RATE_ENUM_SIZE,
301 arizona_rate_text, arizona_rate_val),
302 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1,
303 ARIZONA_DSP1_RATE_SHIFT, 0xf,
304 ARIZONA_RATE_ENUM_SIZE,
305 arizona_rate_text, arizona_rate_val),
306 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP4_CONTROL_1,
307 ARIZONA_DSP1_RATE_SHIFT, 0xf,
308 ARIZONA_RATE_ENUM_SIZE,
309 arizona_rate_text, arizona_rate_val),
312 const struct snd_kcontrol_new wm_adsp2_fw_controls[] = {
313 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
314 wm_adsp_fw_get, wm_adsp_fw_put),
315 SOC_ENUM("DSP1 Rate", wm_adsp2_rate_enum[0]),
316 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
317 wm_adsp_fw_get, wm_adsp_fw_put),
318 SOC_ENUM("DSP2 Rate", wm_adsp2_rate_enum[1]),
319 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
320 wm_adsp_fw_get, wm_adsp_fw_put),
321 SOC_ENUM("DSP3 Rate", wm_adsp2_rate_enum[2]),
322 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
323 wm_adsp_fw_get, wm_adsp_fw_put),
324 SOC_ENUM("DSP4 Rate", wm_adsp2_rate_enum[3]),
326 EXPORT_SYMBOL_GPL(wm_adsp2_fw_controls);
329 static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
334 for (i = 0; i < dsp->num_mems; i++)
335 if (dsp->mem[i].type == type)
341 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *region,
344 if (WARN_ON(!region))
346 switch (region->type) {
348 return region->base + (offset * 3);
350 return region->base + (offset * 2);
352 return region->base + (offset * 2);
354 return region->base + (offset * 2);
356 return region->base + (offset * 2);
358 WARN(1, "Unknown memory region type");
363 static int wm_coeff_info(struct snd_kcontrol *kcontrol,
364 struct snd_ctl_elem_info *uinfo)
366 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
368 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
369 uinfo->count = ctl->len;
373 static int wm_coeff_write_control(struct snd_kcontrol *kcontrol,
374 const void *buf, size_t len)
376 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
377 struct wm_adsp_alg_region *region = &ctl->region;
378 const struct wm_adsp_region *mem;
379 struct wm_adsp *adsp = ctl->adsp;
384 mem = wm_adsp_find_region(adsp, region->type);
386 adsp_err(adsp, "No base for region %x\n",
391 reg = ctl->region.base;
392 reg = wm_adsp_region_to_reg(mem, reg);
394 scratch = kmemdup(buf, ctl->len, GFP_KERNEL | GFP_DMA);
398 ret = regmap_raw_write(adsp->regmap, reg, scratch,
401 adsp_err(adsp, "Failed to write %zu bytes to %x: %d\n",
406 adsp_dbg(adsp, "Wrote %zu bytes to %x\n", ctl->len, reg);
413 static int wm_coeff_put(struct snd_kcontrol *kcontrol,
414 struct snd_ctl_elem_value *ucontrol)
416 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
417 char *p = ucontrol->value.bytes.data;
419 memcpy(ctl->cache, p, ctl->len);
426 return wm_coeff_write_control(kcontrol, p, ctl->len);
429 static int wm_coeff_read_control(struct snd_kcontrol *kcontrol,
430 void *buf, size_t len)
432 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
433 struct wm_adsp_alg_region *region = &ctl->region;
434 const struct wm_adsp_region *mem;
435 struct wm_adsp *adsp = ctl->adsp;
440 mem = wm_adsp_find_region(adsp, region->type);
442 adsp_err(adsp, "No base for region %x\n",
447 reg = ctl->region.base;
448 reg = wm_adsp_region_to_reg(mem, reg);
450 scratch = kmalloc(ctl->len, GFP_KERNEL | GFP_DMA);
454 ret = regmap_raw_read(adsp->regmap, reg, scratch, ctl->len);
456 adsp_err(adsp, "Failed to read %zu bytes from %x: %d\n",
461 adsp_dbg(adsp, "Read %zu bytes from %x\n", ctl->len, reg);
463 memcpy(buf, scratch, ctl->len);
469 static int wm_coeff_get(struct snd_kcontrol *kcontrol,
470 struct snd_ctl_elem_value *ucontrol)
472 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
473 char *p = ucontrol->value.bytes.data;
475 memcpy(p, ctl->cache, ctl->len);
479 struct wmfw_ctl_work {
480 struct wm_adsp *adsp;
481 struct wm_coeff_ctl *ctl;
482 struct work_struct work;
485 static int wmfw_add_ctl(struct wm_adsp *adsp, struct wm_coeff_ctl *ctl)
487 struct snd_kcontrol_new *kcontrol;
490 if (!ctl || !ctl->name)
493 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
496 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
498 kcontrol->name = ctl->name;
499 kcontrol->info = wm_coeff_info;
500 kcontrol->get = wm_coeff_get;
501 kcontrol->put = wm_coeff_put;
502 kcontrol->private_value = (unsigned long)ctl;
504 ret = snd_soc_add_card_controls(adsp->card,
511 ctl->kcontrol = snd_soc_card_get_kcontrol(adsp->card,
514 list_add(&ctl->list, &adsp->ctl_list);
522 static int wm_adsp_load(struct wm_adsp *dsp)
525 const struct firmware *firmware;
526 struct regmap *regmap = dsp->regmap;
527 unsigned int pos = 0;
528 const struct wmfw_header *header;
529 const struct wmfw_adsp1_sizes *adsp1_sizes;
530 const struct wmfw_adsp2_sizes *adsp2_sizes;
531 const struct wmfw_footer *footer;
532 const struct wmfw_region *region;
533 const struct wm_adsp_region *mem;
534 const char *region_name;
536 struct wm_adsp_buf *buf;
539 int ret, offset, type, sizes;
541 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
545 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
546 wm_adsp_fw[dsp->fw].file);
547 file[PAGE_SIZE - 1] = '\0';
549 ret = request_firmware(&firmware, file, dsp->dev);
551 adsp_err(dsp, "Failed to request '%s'\n", file);
556 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
557 if (pos >= firmware->size) {
558 adsp_err(dsp, "%s: file too short, %zu bytes\n",
559 file, firmware->size);
563 header = (void*)&firmware->data[0];
565 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
566 adsp_err(dsp, "%s: invalid magic\n", file);
570 if (header->ver != 0) {
571 adsp_err(dsp, "%s: unknown file format %d\n",
575 adsp_info(dsp, "Firmware version: %d\n", header->ver);
577 if (header->core != dsp->type) {
578 adsp_err(dsp, "%s: invalid core %d != %d\n",
579 file, header->core, dsp->type);
585 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
586 adsp1_sizes = (void *)&(header[1]);
587 footer = (void *)&(adsp1_sizes[1]);
588 sizes = sizeof(*adsp1_sizes);
590 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
591 file, le32_to_cpu(adsp1_sizes->dm),
592 le32_to_cpu(adsp1_sizes->pm),
593 le32_to_cpu(adsp1_sizes->zm));
597 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
598 adsp2_sizes = (void *)&(header[1]);
599 footer = (void *)&(adsp2_sizes[1]);
600 sizes = sizeof(*adsp2_sizes);
602 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
603 file, le32_to_cpu(adsp2_sizes->xm),
604 le32_to_cpu(adsp2_sizes->ym),
605 le32_to_cpu(adsp2_sizes->pm),
606 le32_to_cpu(adsp2_sizes->zm));
610 WARN(1, "Unknown DSP type");
614 if (le32_to_cpu(header->len) != sizeof(*header) +
615 sizes + sizeof(*footer)) {
616 adsp_err(dsp, "%s: unexpected header length %d\n",
617 file, le32_to_cpu(header->len));
621 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
622 le64_to_cpu(footer->timestamp));
624 while (pos < firmware->size &&
625 pos - firmware->size > sizeof(*region)) {
626 region = (void *)&(firmware->data[pos]);
627 region_name = "Unknown";
630 offset = le32_to_cpu(region->offset) & 0xffffff;
631 type = be32_to_cpu(region->type) & 0xff;
632 mem = wm_adsp_find_region(dsp, type);
636 region_name = "Firmware name";
637 text = kzalloc(le32_to_cpu(region->len) + 1,
641 region_name = "Information";
642 text = kzalloc(le32_to_cpu(region->len) + 1,
646 region_name = "Absolute";
651 reg = wm_adsp_region_to_reg(mem, offset);
655 reg = wm_adsp_region_to_reg(mem, offset);
659 reg = wm_adsp_region_to_reg(mem, offset);
663 reg = wm_adsp_region_to_reg(mem, offset);
667 reg = wm_adsp_region_to_reg(mem, offset);
671 "%s.%d: Unknown region type %x at %d(%x)\n",
672 file, regions, type, pos, pos);
676 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
677 regions, le32_to_cpu(region->len), offset,
681 memcpy(text, region->data, le32_to_cpu(region->len));
682 adsp_info(dsp, "%s: %s\n", file, text);
687 size_t to_write = PAGE_SIZE;
688 size_t remain = le32_to_cpu(region->len);
689 const u8 *data = region->data;
692 if (remain < PAGE_SIZE)
695 buf = wm_adsp_buf_alloc(data,
699 adsp_err(dsp, "Out of memory\n");
704 ret = regmap_raw_write_async(regmap, reg,
709 "%s.%d: Failed to write %zd bytes at %d in %s: %d\n",
722 pos += le32_to_cpu(region->len) + sizeof(*region);
726 ret = regmap_async_complete(regmap);
728 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
732 if (pos > firmware->size)
733 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
734 file, regions, pos - firmware->size);
737 regmap_async_complete(regmap);
738 wm_adsp_buf_free(&buf_list);
739 release_firmware(firmware);
746 static int wm_coeff_init_control_caches(struct wm_adsp *adsp)
748 struct wm_coeff_ctl *ctl;
751 list_for_each_entry(ctl, &adsp->ctl_list, list) {
752 if (!ctl->enabled || ctl->set)
754 ret = wm_coeff_read_control(ctl->kcontrol,
764 static int wm_coeff_sync_controls(struct wm_adsp *adsp)
766 struct wm_coeff_ctl *ctl;
769 list_for_each_entry(ctl, &adsp->ctl_list, list) {
773 ret = wm_coeff_write_control(ctl->kcontrol,
784 static void wm_adsp_ctl_work(struct work_struct *work)
786 struct wmfw_ctl_work *ctl_work = container_of(work,
787 struct wmfw_ctl_work,
790 wmfw_add_ctl(ctl_work->adsp, ctl_work->ctl);
794 static int wm_adsp_create_control(struct wm_adsp *dsp,
795 const struct wm_adsp_alg_region *region)
798 struct wm_coeff_ctl *ctl;
799 struct wmfw_ctl_work *ctl_work;
804 name = kmalloc(PAGE_SIZE, GFP_KERNEL);
808 switch (region->type) {
829 snprintf(name, PAGE_SIZE, "DSP%d %s %x",
830 dsp->num, region_name, region->alg);
832 list_for_each_entry(ctl, &dsp->ctl_list,
834 if (!strcmp(ctl->name, name)) {
841 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
846 ctl->region = *region;
847 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
854 ctl->ops.xget = wm_coeff_get;
855 ctl->ops.xput = wm_coeff_put;
858 ctl->len = region->len;
859 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
865 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
871 ctl_work->adsp = dsp;
873 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
874 schedule_work(&ctl_work->work);
892 static int wm_adsp_setup_algs(struct wm_adsp *dsp)
894 struct regmap *regmap = dsp->regmap;
895 struct wmfw_adsp1_id_hdr adsp1_id;
896 struct wmfw_adsp2_id_hdr adsp2_id;
897 struct wmfw_adsp1_alg_hdr *adsp1_alg;
898 struct wmfw_adsp2_alg_hdr *adsp2_alg;
900 struct wm_adsp_alg_region *region;
901 const struct wm_adsp_region *mem;
902 unsigned int pos, term;
903 size_t algs, buf_size;
909 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
912 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
924 ret = regmap_raw_read(regmap, mem->base, &adsp1_id,
927 adsp_err(dsp, "Failed to read algorithm info: %d\n",
933 buf_size = sizeof(adsp1_id);
935 algs = be32_to_cpu(adsp1_id.algs);
936 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
937 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
939 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
940 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
941 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
944 region = kzalloc(sizeof(*region), GFP_KERNEL);
947 region->type = WMFW_ADSP1_ZM;
948 region->alg = be32_to_cpu(adsp1_id.fw.id);
949 region->base = be32_to_cpu(adsp1_id.zm);
950 list_add_tail(®ion->list, &dsp->alg_regions);
952 region = kzalloc(sizeof(*region), GFP_KERNEL);
955 region->type = WMFW_ADSP1_DM;
956 region->alg = be32_to_cpu(adsp1_id.fw.id);
957 region->base = be32_to_cpu(adsp1_id.dm);
958 list_add_tail(®ion->list, &dsp->alg_regions);
960 pos = sizeof(adsp1_id) / 2;
961 term = pos + ((sizeof(*adsp1_alg) * algs) / 2);
965 ret = regmap_raw_read(regmap, mem->base, &adsp2_id,
968 adsp_err(dsp, "Failed to read algorithm info: %d\n",
974 buf_size = sizeof(adsp2_id);
976 algs = be32_to_cpu(adsp2_id.algs);
977 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
978 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
980 (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16,
981 (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8,
982 be32_to_cpu(adsp2_id.fw.ver) & 0xff,
985 region = kzalloc(sizeof(*region), GFP_KERNEL);
988 region->type = WMFW_ADSP2_XM;
989 region->alg = be32_to_cpu(adsp2_id.fw.id);
990 region->base = be32_to_cpu(adsp2_id.xm);
991 list_add_tail(®ion->list, &dsp->alg_regions);
993 region = kzalloc(sizeof(*region), GFP_KERNEL);
996 region->type = WMFW_ADSP2_YM;
997 region->alg = be32_to_cpu(adsp2_id.fw.id);
998 region->base = be32_to_cpu(adsp2_id.ym);
999 list_add_tail(®ion->list, &dsp->alg_regions);
1001 region = kzalloc(sizeof(*region), GFP_KERNEL);
1004 region->type = WMFW_ADSP2_ZM;
1005 region->alg = be32_to_cpu(adsp2_id.fw.id);
1006 region->base = be32_to_cpu(adsp2_id.zm);
1007 list_add_tail(®ion->list, &dsp->alg_regions);
1009 pos = sizeof(adsp2_id) / 2;
1010 term = pos + ((sizeof(*adsp2_alg) * algs) / 2);
1014 WARN(1, "Unknown DSP type");
1019 adsp_err(dsp, "No algorithms\n");
1024 adsp_err(dsp, "Algorithm count %zx excessive\n", algs);
1025 print_hex_dump_bytes(dev_name(dsp->dev), DUMP_PREFIX_OFFSET,
1030 /* Read the terminator first to validate the length */
1031 ret = regmap_raw_read(regmap, mem->base + term, &val, sizeof(val));
1033 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1038 if (be32_to_cpu(val) != 0xbedead)
1039 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1040 term, be32_to_cpu(val));
1042 alg = kzalloc((term - pos) * 2, GFP_KERNEL | GFP_DMA);
1046 ret = regmap_raw_read(regmap, mem->base + pos, alg, (term - pos) * 2);
1048 adsp_err(dsp, "Failed to read algorithm list: %d\n",
1056 for (i = 0; i < algs; i++) {
1057 switch (dsp->type) {
1059 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
1060 i, be32_to_cpu(adsp1_alg[i].alg.id),
1061 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1062 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
1063 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1064 be32_to_cpu(adsp1_alg[i].dm),
1065 be32_to_cpu(adsp1_alg[i].zm));
1067 region = kzalloc(sizeof(*region), GFP_KERNEL);
1070 region->type = WMFW_ADSP1_DM;
1071 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
1072 region->base = be32_to_cpu(adsp1_alg[i].dm);
1074 list_add_tail(®ion->list, &dsp->alg_regions);
1076 region->len = be32_to_cpu(adsp1_alg[i + 1].dm);
1077 region->len -= be32_to_cpu(adsp1_alg[i].dm);
1079 wm_adsp_create_control(dsp, region);
1081 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1082 be32_to_cpu(adsp1_alg[i].alg.id));
1085 region = kzalloc(sizeof(*region), GFP_KERNEL);
1088 region->type = WMFW_ADSP1_ZM;
1089 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
1090 region->base = be32_to_cpu(adsp1_alg[i].zm);
1092 list_add_tail(®ion->list, &dsp->alg_regions);
1094 region->len = be32_to_cpu(adsp1_alg[i + 1].zm);
1095 region->len -= be32_to_cpu(adsp1_alg[i].zm);
1097 wm_adsp_create_control(dsp, region);
1099 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1100 be32_to_cpu(adsp1_alg[i].alg.id));
1106 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
1107 i, be32_to_cpu(adsp2_alg[i].alg.id),
1108 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1109 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
1110 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1111 be32_to_cpu(adsp2_alg[i].xm),
1112 be32_to_cpu(adsp2_alg[i].ym),
1113 be32_to_cpu(adsp2_alg[i].zm));
1115 region = kzalloc(sizeof(*region), GFP_KERNEL);
1118 region->type = WMFW_ADSP2_XM;
1119 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
1120 region->base = be32_to_cpu(adsp2_alg[i].xm);
1122 list_add_tail(®ion->list, &dsp->alg_regions);
1124 region->len = be32_to_cpu(adsp2_alg[i + 1].xm);
1125 region->len -= be32_to_cpu(adsp2_alg[i].xm);
1127 wm_adsp_create_control(dsp, region);
1129 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1130 be32_to_cpu(adsp2_alg[i].alg.id));
1133 region = kzalloc(sizeof(*region), GFP_KERNEL);
1136 region->type = WMFW_ADSP2_YM;
1137 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
1138 region->base = be32_to_cpu(adsp2_alg[i].ym);
1140 list_add_tail(®ion->list, &dsp->alg_regions);
1142 region->len = be32_to_cpu(adsp2_alg[i + 1].ym);
1143 region->len -= be32_to_cpu(adsp2_alg[i].ym);
1145 wm_adsp_create_control(dsp, region);
1147 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1148 be32_to_cpu(adsp2_alg[i].alg.id));
1151 region = kzalloc(sizeof(*region), GFP_KERNEL);
1154 region->type = WMFW_ADSP2_ZM;
1155 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
1156 region->base = be32_to_cpu(adsp2_alg[i].zm);
1158 list_add_tail(®ion->list, &dsp->alg_regions);
1160 region->len = be32_to_cpu(adsp2_alg[i + 1].zm);
1161 region->len -= be32_to_cpu(adsp2_alg[i].zm);
1163 wm_adsp_create_control(dsp, region);
1165 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1166 be32_to_cpu(adsp2_alg[i].alg.id));
1177 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
1179 LIST_HEAD(buf_list);
1180 struct regmap *regmap = dsp->regmap;
1181 struct wmfw_coeff_hdr *hdr;
1182 struct wmfw_coeff_item *blk;
1183 const struct firmware *firmware;
1184 const struct wm_adsp_region *mem;
1185 struct wm_adsp_alg_region *alg_region;
1186 const char *region_name;
1187 int ret, pos, blocks, type, offset, reg;
1189 struct wm_adsp_buf *buf;
1192 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1196 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
1197 wm_adsp_fw[dsp->fw].file);
1198 file[PAGE_SIZE - 1] = '\0';
1200 ret = request_firmware(&firmware, file, dsp->dev);
1202 adsp_warn(dsp, "Failed to request '%s'\n", file);
1208 if (sizeof(*hdr) >= firmware->size) {
1209 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1210 file, firmware->size);
1214 hdr = (void*)&firmware->data[0];
1215 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
1216 adsp_err(dsp, "%s: invalid magic\n", file);
1220 switch (be32_to_cpu(hdr->rev) & 0xff) {
1224 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
1225 file, be32_to_cpu(hdr->rev) & 0xff);
1230 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
1231 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
1232 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
1233 le32_to_cpu(hdr->ver) & 0xff);
1235 pos = le32_to_cpu(hdr->len);
1238 while (pos < firmware->size &&
1239 pos - firmware->size > sizeof(*blk)) {
1240 blk = (void*)(&firmware->data[pos]);
1242 type = le16_to_cpu(blk->type);
1243 offset = le16_to_cpu(blk->offset);
1245 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
1246 file, blocks, le32_to_cpu(blk->id),
1247 (le32_to_cpu(blk->ver) >> 16) & 0xff,
1248 (le32_to_cpu(blk->ver) >> 8) & 0xff,
1249 le32_to_cpu(blk->ver) & 0xff);
1250 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
1251 file, blocks, le32_to_cpu(blk->len), offset, type);
1254 region_name = "Unknown";
1256 case (WMFW_NAME_TEXT << 8):
1257 case (WMFW_INFO_TEXT << 8):
1259 case (WMFW_ABSOLUTE << 8):
1261 * Old files may use this for global
1264 if (le32_to_cpu(blk->id) == dsp->fw_id &&
1266 region_name = "global coefficients";
1267 mem = wm_adsp_find_region(dsp, type);
1269 adsp_err(dsp, "No ZM\n");
1272 reg = wm_adsp_region_to_reg(mem, 0);
1275 region_name = "register";
1284 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
1285 file, blocks, le32_to_cpu(blk->len),
1286 type, le32_to_cpu(blk->id));
1288 mem = wm_adsp_find_region(dsp, type);
1290 adsp_err(dsp, "No base for region %x\n", type);
1295 list_for_each_entry(alg_region,
1296 &dsp->alg_regions, list) {
1297 if (le32_to_cpu(blk->id) == alg_region->alg &&
1298 type == alg_region->type) {
1299 reg = alg_region->base;
1300 reg = wm_adsp_region_to_reg(mem,
1308 adsp_err(dsp, "No %x for algorithm %x\n",
1309 type, le32_to_cpu(blk->id));
1313 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
1314 file, blocks, type, pos);
1319 buf = wm_adsp_buf_alloc(blk->data,
1320 le32_to_cpu(blk->len),
1323 adsp_err(dsp, "Out of memory\n");
1328 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
1329 file, blocks, le32_to_cpu(blk->len),
1331 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1332 le32_to_cpu(blk->len));
1335 "%s.%d: Failed to write to %x in %s: %d\n",
1336 file, blocks, reg, region_name, ret);
1340 tmp = le32_to_cpu(blk->len) % 4;
1342 pos += le32_to_cpu(blk->len) + (4 - tmp) + sizeof(*blk);
1344 pos += le32_to_cpu(blk->len) + sizeof(*blk);
1349 ret = regmap_async_complete(regmap);
1351 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1353 if (pos > firmware->size)
1354 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1355 file, blocks, pos - firmware->size);
1358 regmap_async_complete(regmap);
1359 release_firmware(firmware);
1360 wm_adsp_buf_free(&buf_list);
1366 int wm_adsp1_init(struct wm_adsp *adsp)
1368 INIT_LIST_HEAD(&adsp->alg_regions);
1372 EXPORT_SYMBOL_GPL(wm_adsp1_init);
1374 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
1375 struct snd_kcontrol *kcontrol,
1378 struct snd_soc_codec *codec = w->codec;
1379 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1380 struct wm_adsp *dsp = &dsps[w->shift];
1381 struct wm_adsp_alg_region *alg_region;
1382 struct wm_coeff_ctl *ctl;
1386 dsp->card = codec->component.card;
1389 case SND_SOC_DAPM_POST_PMU:
1390 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1391 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
1394 * For simplicity set the DSP clock rate to be the
1395 * SYSCLK rate rather than making it configurable.
1397 if(dsp->sysclk_reg) {
1398 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
1400 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1405 val = (val & dsp->sysclk_mask)
1406 >> dsp->sysclk_shift;
1408 ret = regmap_update_bits(dsp->regmap,
1409 dsp->base + ADSP1_CONTROL_31,
1410 ADSP1_CLK_SEL_MASK, val);
1412 adsp_err(dsp, "Failed to set clock rate: %d\n",
1418 ret = wm_adsp_load(dsp);
1422 ret = wm_adsp_setup_algs(dsp);
1426 ret = wm_adsp_load_coeff(dsp);
1430 /* Initialize caches for enabled and unset controls */
1431 ret = wm_coeff_init_control_caches(dsp);
1435 /* Sync set controls */
1436 ret = wm_coeff_sync_controls(dsp);
1440 /* Start the core running */
1441 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1442 ADSP1_CORE_ENA | ADSP1_START,
1443 ADSP1_CORE_ENA | ADSP1_START);
1446 case SND_SOC_DAPM_PRE_PMD:
1448 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1449 ADSP1_CORE_ENA | ADSP1_START, 0);
1451 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
1452 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
1454 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1457 list_for_each_entry(ctl, &dsp->ctl_list, list)
1460 while (!list_empty(&dsp->alg_regions)) {
1461 alg_region = list_first_entry(&dsp->alg_regions,
1462 struct wm_adsp_alg_region,
1464 list_del(&alg_region->list);
1476 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1480 EXPORT_SYMBOL_GPL(wm_adsp1_event);
1482 static int wm_adsp2_ena(struct wm_adsp *dsp)
1487 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
1488 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
1492 /* Wait for the RAM to start, should be near instantaneous */
1493 for (count = 0; count < 10; ++count) {
1494 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
1499 if (val & ADSP2_RAM_RDY)
1505 if (!(val & ADSP2_RAM_RDY)) {
1506 adsp_err(dsp, "Failed to start DSP RAM\n");
1510 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
1515 static void wm_adsp2_boot_work(struct work_struct *work)
1517 struct wm_adsp *dsp = container_of(work,
1524 * For simplicity set the DSP clock rate to be the
1525 * SYSCLK rate rather than making it configurable.
1527 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
1529 adsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret);
1532 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
1533 >> ARIZONA_SYSCLK_FREQ_SHIFT;
1535 ret = regmap_update_bits_async(dsp->regmap,
1536 dsp->base + ADSP2_CLOCKING,
1537 ADSP2_CLK_SEL_MASK, val);
1539 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
1544 ret = regmap_read(dsp->regmap,
1545 dsp->base + ADSP2_CLOCKING, &val);
1547 adsp_err(dsp, "Failed to read clocking: %d\n", ret);
1551 if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
1552 ret = regulator_enable(dsp->dvfs);
1555 "Failed to enable supply: %d\n",
1560 ret = regulator_set_voltage(dsp->dvfs,
1565 "Failed to raise supply: %d\n",
1572 ret = wm_adsp2_ena(dsp);
1576 ret = wm_adsp_load(dsp);
1580 ret = wm_adsp_setup_algs(dsp);
1584 ret = wm_adsp_load_coeff(dsp);
1588 /* Initialize caches for enabled and unset controls */
1589 ret = wm_coeff_init_control_caches(dsp);
1593 /* Sync set controls */
1594 ret = wm_coeff_sync_controls(dsp);
1598 ret = regmap_update_bits_async(dsp->regmap,
1599 dsp->base + ADSP2_CONTROL,
1605 dsp->running = true;
1610 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1611 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
1614 int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
1615 struct snd_kcontrol *kcontrol, int event)
1617 struct snd_soc_codec *codec = w->codec;
1618 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1619 struct wm_adsp *dsp = &dsps[w->shift];
1621 dsp->card = codec->component.card;
1624 case SND_SOC_DAPM_PRE_PMU:
1625 queue_work(system_unbound_wq, &dsp->boot_work);
1633 EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
1635 int wm_adsp2_event(struct snd_soc_dapm_widget *w,
1636 struct snd_kcontrol *kcontrol, int event)
1638 struct snd_soc_codec *codec = w->codec;
1639 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1640 struct wm_adsp *dsp = &dsps[w->shift];
1641 struct wm_adsp_alg_region *alg_region;
1642 struct wm_coeff_ctl *ctl;
1646 case SND_SOC_DAPM_POST_PMU:
1647 flush_work(&dsp->boot_work);
1652 ret = regmap_update_bits(dsp->regmap,
1653 dsp->base + ADSP2_CONTROL,
1660 case SND_SOC_DAPM_PRE_PMD:
1661 dsp->running = false;
1663 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1664 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
1667 /* Make sure DMAs are quiesced */
1668 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
1669 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
1670 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
1673 ret = regulator_set_voltage(dsp->dvfs, 1200000,
1677 "Failed to lower supply: %d\n",
1680 ret = regulator_disable(dsp->dvfs);
1683 "Failed to enable supply: %d\n",
1687 list_for_each_entry(ctl, &dsp->ctl_list, list)
1690 while (!list_empty(&dsp->alg_regions)) {
1691 alg_region = list_first_entry(&dsp->alg_regions,
1692 struct wm_adsp_alg_region,
1694 list_del(&alg_region->list);
1698 adsp_dbg(dsp, "Shutdown complete\n");
1707 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1708 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
1711 EXPORT_SYMBOL_GPL(wm_adsp2_event);
1713 int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs)
1718 * Disable the DSP memory by default when in reset for a small
1721 ret = regmap_update_bits(adsp->regmap, adsp->base + ADSP2_CONTROL,
1724 adsp_err(adsp, "Failed to clear memory retention: %d\n", ret);
1728 INIT_LIST_HEAD(&adsp->alg_regions);
1729 INIT_LIST_HEAD(&adsp->ctl_list);
1730 INIT_WORK(&adsp->boot_work, wm_adsp2_boot_work);
1733 adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");
1734 if (IS_ERR(adsp->dvfs)) {
1735 ret = PTR_ERR(adsp->dvfs);
1736 adsp_err(adsp, "Failed to get DCVDD: %d\n", ret);
1740 ret = regulator_enable(adsp->dvfs);
1742 adsp_err(adsp, "Failed to enable DCVDD: %d\n", ret);
1746 ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000);
1748 adsp_err(adsp, "Failed to initialise DVFS: %d\n", ret);
1752 ret = regulator_disable(adsp->dvfs);
1754 adsp_err(adsp, "Failed to disable DCVDD: %d\n", ret);
1761 EXPORT_SYMBOL_GPL(wm_adsp2_init);
1763 MODULE_LICENSE("GPL v2");